96 lines
1.8 KiB
C
Executable File
96 lines
1.8 KiB
C
Executable File
/*
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* (C) Copyright 2019-2020
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* Stelian Pop <junbao.zhang@molchip.com>
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* Lead Tech Design <www.molchip.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <mach/hardware.h>
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#include <mach/clk.h>
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#include <mach/clock.h>
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#include <mach/spic.h>
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#include <mach/uart_drv.h>
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#include <mach/download.h>
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#include <mach/ddr.h>
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#include <mach/board.h>
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#include <mach/usb_boot.h>
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void s_init(void)
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{
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//timer clk init
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molchip_systimer_clk_enable();
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//uart0 clk init
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molchip_uart_clk_enable(REG_UART0_BASE);
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//uart1 clk init
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molchip_uart_clk_enable(REG_UART1_BASE);
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#ifdef CONFIG_TARGET_TS01
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//spic clk enable
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molchip_spic_clk_enable();
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#endif
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}
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/* This function prepares the hardware for
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* execution from system RAM (DRAM, DDR...) As system RAM may not
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* be available yet, , board_init_f() must use the current GD to
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* store any data which must be passed on to later stages. These
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* data include the relocation destination, the future stack, and
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* the future GD location.
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*
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* bss data not init
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*/
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void board_init_f(ulong dummy)
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{
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/* CPU/BUS CLK config if needed*/
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s_init();
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//uart_hw_init();
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#ifdef CONFIG_TARGET_TS01
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board_spic_init();
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#endif
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/* Bias config reset */
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// ana_bias_reset();
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/* DDR config if needed */
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DRAM_Init();
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//clock_init();
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mc_printf("CA7 frequency: %dhz\r\n",mc_get_cpu_clk());
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set_cpu_max_clk();
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}
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void board_init_r(gd_t *dummy1, ulong dummy2)
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{
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uint uart_port;
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unsigned int val;
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val = get_strap_status();
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if(val & 0x1){ //uart download
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uart_port = uart_identify();
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uart_preboot(uart_port);
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uart_boot(uart_port);
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}else{
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usb_identify();
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usb_preboot();
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usb_boot();
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}
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while(1);
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}
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void hang(void)
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{
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while(1);
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}
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