TMC32_QJB/Uart/UART_main.h

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2026-04-30 08:23:12 +00:00
/**
******************************************************************************
* @file TMC_UART.h
* @author TMC Terminal Team
* @version V1.0.0
* @date 06/21/2018
* @brief Header file of UART TMC module.
*
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, TMC SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2016 TMC</center></h2>
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef _TMC_UART_H
#define _TMC_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "global.h"
#include "camera_main.h"
#define UART_RECEIVE_TIMEOUT (12000 * 600)
typedef enum
{
TMC_UART_STATE_RESET = 0x01U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
TMC_UART_STATE_READY = 0x02U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
TMC_UART_STATE_BUSY = 0x04U, /*!< an internal process is ongoing
Value is allowed for gState only */
TMC_UART_STATE_BUSY_TX = 0x08U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
TMC_UART_STATE_BUSY_RX = 0x10U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
TMC_UART_STATE_TIMEOUT = 0x20U, /*!< Timeout state
Value is allowed for gState only */
TMC_UART_STATE_ERROR = 0x40U, /*!< Error
Value is allowed for gState only */
TMC_UART_STATE_RECEIVEFINISH = 0x80U,
} UART_StateTypeDef;
typedef struct
{
UART_TypeDef *UARTx; /*!< UART registers base address */
UART_InitTypeDef Init; /*!< UART communication parameters */
HAL_LockTypeDef Lock; /*!< UART locking object */
uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */
uint32_t TxXferSize; /*!< UART Tx Transfer size */
__IO uint32_t TxXferCount; /*!< UART Tx Transfer Counter */
uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */
uint32_t RxXferSize; /*!< UART Rx Transfer size */
__IO uint32_t RxXferCount; /*!< UART Rx Transfer Counter */
DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */
DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */
__IO UART_StateTypeDef gState; /*!< UART state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref UART_StateTypeDef */
__IO uint32_t ErrorCode; /*!< UART Error code
This parameter can be a value of @ref UART_error_status */
} UART_HandleTypeDef;
//9600,14400,38400,56000,57600,115200,128000,256000
typedef enum
{
BAUDRATE_9600 = 9600,
BAUDRATE_14400 = 14400,
BAUDRATE_56000 = 56000,
BAUDRATE_57600 = 57600,
BAUDRATE_115200 = 115200,
BAUDRATE_128000 = 128000,
BAUDRATE_256000 = 256000,
BAUDRATE_460800 = 460800,
} Uart_BaudRate_Value;
/*<2A><><EFBFBD><EFBFBD>Э<EFBFBD><D0AD>˵<EFBFBD><CBB5><EFBFBD><EFBFBD>
STX:0x5A
FID:0x00
LEN:0xXXXX
CMD:XXXX...
BCC:0xXX
ETX:0xA5
*/
typedef enum
{
UART_PROTOCOL_STX = 0x00,
UART_PROTOCOL_FID = 0x01,
UART_PROTOCOL_LEN = 0x02,
UART_PROTOCOL_DATA = 0x03,
UART_PROTOCOL_FINISH = 0x04,
} Uart_Receive_PROTOCOL;
//#define UART_PROTOCOL_STX_VALUE 0x5A //asc (Z)
#define UART_PROTOCOL_STX_VALUE 0x5B //asc ([)
#define UART_PROTOCOL_RECEIVE_FID_VALUE 0x00
#define UART_PROTOCOL_RESPONSE_FID_VALUE 0x01
#define UART_PROTOCOL_SEND_FID_VALUE 0x02
//#define UART_PROTOCOL_ETX_VALUE 0xA5
#define UART_PROTOCOL_ETX_VALUE 0x5D //asc (])
#define UART_PROTOCOL_INFO_LEN 0x06 //6ΪЭ<CEAA><D0AD><EFBFBD>ֽڳ<D6BD><DAB3>ȣ<EFBFBD>1<EFBFBD>ֽڿ<D6BD>ʼ<EFBFBD><CABC>־+1<>ֽ<EFBFBD>FID+2<>ֽڳ<D6BD><DAB3><EFBFBD>+1<>ֽ<EFBFBD>У<EFBFBD><D0A3>+1<>ֽڽ<D6BD><DABD><EFBFBD><EFBFBD><EFBFBD>־
#define UART_PROTOCOL_DAT_OFFS 0x04 // 5A+FID+LEN(2)+DAT
#define TMC_UART_ERROR_NONE 0x00000000U /*!< No error */
#define TMC_UART_ERROR_PE 0x00000001U /*!< Parity error */
#define TMC_UART_ERROR_FE 0x00000002U /*!< Frame error */
#define TMC_UART_ERROR_OFE 0x00000004U /*!< Overflow error */
#define TMC_UART_ERROR_DMA 0x00000008U /*!< DMA transfer error */
//-----------------------------------
//add by jjj
#define PACK_TYPEA 0x01
#define PACK_TYPEB 0x03
#define PACK_TYPEC 0x04
#define SYS_PACK_TYPE PACK_TYPEC
#define PACK_RECEIVE_START 0
#define PACK_RECEIVE_DATA 1
//------------------------------------
TMC_StatusTypeDef TMC_UART_Init(UART_HandleTypeDef *huart);
TMC_StatusTypeDef TMC_UART_DeInit(UART_HandleTypeDef *huart);
TMC_StatusTypeDef TMC_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint32_t Size);
TMC_StatusTypeDef TMC_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint32_t Size, uint32_t Timeout);
TMC_StatusTypeDef SET_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint32_t Size);
void TMC_UART_IRQHandler(UART_HandleTypeDef *huart);
void TMC_UART_MspInit(UART_HandleTypeDef *huart);
void TMC_UART_RxCpltCallback(UART_HandleTypeDef *huart);
void AppUartInit(uint32_t baudRate, uint32_t parityMode);
void TMC_UART_ErrorCallback(UART_HandleTypeDef *huart);
uint8_t AppUartSendData(uint8_t *buf, uint32_t len);
uint8_t AppUartSendDataComm(uint8_t *buf, uint32_t len);
uint8_t AppUartReceiveData(uint8_t *buf, uint32_t len);
uint8_t UARTRecieveData(void);
void UART_ClearState(UART_HandleTypeDef *huart);
#ifdef __cplusplus
}
#endif
#endif
/************************ (C) COPYRIGHT TMC *****END OF FILE****/