649 lines
26 KiB
C
649 lines
26 KiB
C
/**
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******************************************************************************
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* @file RCC.h
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* @author TMC Terminal Team
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* @version V1.0.0
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* @date 01/21/2016
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* @brief This file provides all the WDT firmware functions.
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******************************************************************************
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, TMC SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2016 TMC</center></h2>
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef _RCC_H
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#define _RCC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @addtogroup THM36x2_HAL_Driver
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* @{
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*/
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/** @addtogroup RCC
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* @brief RCC driver modules
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* @{
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*/
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/** @defgroup RCC_Exported_Types RCC Exported Types
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* @{
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*/
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/**
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* @brief RCC HSE configuration structure definition
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*/
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typedef struct
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{
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FunctionalState FeedbackResEanble; /*!< Enable or Disable Internal feedback Resistor */
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uint32_t HSE_ClockValue; /*!< The value of HSE input's clock */
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FunctionalState HSE_ByPass; /*!< Enable or Disable HSE bypass */
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} RCC_HSEConfigTypeDef;
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/**
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* @brief RCC PLL configuration structure definition
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*/
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typedef struct
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{
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uint32_t PLL_M; /*!< The value of PLL_M,the range is 1 to 4 */
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uint32_t PLL_N; /*!< The value of PLL_N,the range is 10 to 127 */
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uint32_t PLL_Q; /*!< The value of PLL_Q,the range is 2/4/6/8 */
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float SourceClockVaule; /*!< The value of Source Clock */
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uint32_t PLL_Input; /*!< The clock to be configured.
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This parameter can be a value of @ref PLL_source_clock_define */
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} RCC_PLL_InitTypeDef;
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/**
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* @brief RCC LSE configuration structure definition
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*/
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typedef struct
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{
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FunctionalState FeedbackResEanble; /*!< Enable or Disable Internal feedback Resistor */
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} RCC_LSEConfigTypeDef;
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/**
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* @}
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*/
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/** @defgroup RCC_Exported_Constants RCC Exported Constants
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* @{
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*/
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/** @defgroup AHB_peripheral AHB peripheral
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* @{
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*/
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#define RCC_AHBPeriph_DMA 0x00000001UL
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#define RCC_AHBPeriph_DCMI 0x00000004UL
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#define RCC_AHBPeriph_SPI2 0x00000008UL
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#define RCC_AHBPeriph_FLASHCACHE 0x00010000UL
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/**
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* @}
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*/
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/** @defgroup APB2_peripheral APB2 peripheral
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* @{
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*/
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#define RCC_APB2Periph_SPI1 0x00000001UL
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#define RCC_APB2Periph_SPI3 0x00000002UL
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#define RCC_APB2Periph_UART1 0x00000008UL
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#define RCC_APB2Periph_TIMER1_2 0x00000010UL
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#define RCC_APB2Periph_TIMER5_6 0x00000020UL
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#define RCC_APB2Periph_I2C 0x00000040UL
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#define RCC_APB2Periph_7816M1 0x00000080UL
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#define RCC_APB2Periph_ADC 0x00000100UL
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#define RCC_APB2Periph_CRC 0x00000200UL
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#define RCC_APB2Periph_WDT 0x00000400UL
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#define RCC_APB2Periph_PWM1 0x00000800UL
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#define RCC_APB2Periph_7816M3 0x00001000UL
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#define RCC_APB2Periph_UART3 0x00002000UL
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/**
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* @}
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*/
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/** @defgroup APB3_peripheral APB3 peripheral
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* @{
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*/
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#define RCC_APB3Periph_FSMC 0x00000001UL
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#define RCC_APB3Periph_UART4 0x00000002UL
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#define RCC_APB3Periph_UART2 0x00000004UL
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#define RCC_APB3Periph_TIMER3_4 0x00000008UL
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#define RCC_APB3Periph_GPIO 0x00000040UL
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#define RCC_APB3Periph_7816S 0x00000080UL
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#define RCC_APB3Periph_7816M2 0x00000200UL
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#define RCC_APB3Periph_PWM2 0x00000400UL
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/**
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* @}
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*/
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/** @defgroup Security1_peripheral Security1 peripheral
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* @{
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*/
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#define RCC_SEC1Periph_INT 0x00000002UL
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#define RCC_SEC1Periph_PWRC 0x00000004UL
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#define RCC_SEC1Periph_SM4 0x00000200UL
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#define RCC_SEC1Periph_AES 0x00001000UL
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#define RCC_SEC1Periph_DES 0x00002000UL
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#define RCC_SEC1Periph_PKE 0x00004000UL
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#define RCC_SEC1Periph_SWP 0x00008000UL
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#define RCC_SEC1Periph_TRNG 0x00010000UL
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#define RCC_SEC1Periph_ActiveShield 0x00080000UL
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#define RCC_SEC1Periph_ExternalVoltageGlitchDetection 0x00300000UL
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#define RCC_SEC1Periph_LightDerector 0x00400000UL
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#define RCC_SEC1Periph_FrequencyDerector 0x00800000UL
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#define RCC_SEC1Periph_VBSENSOR (1U<<28)//0x10000000UL
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/**
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* @}
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*/
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/** @defgroup Security2_peripheral Security2 peripheral
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* @{
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*/
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#define RCC_SEC2Periph_FLASH 0x00000002UL
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#define RCC_SEC2Periph_USB 0x00010000UL
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/**
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* @}
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*/
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/** @defgroup VBAT_security_module VBAT security module
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* @{
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*/
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#define RCC_BATS_SENSOR 0x00000020UL
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#define RCC_BATS_STDBYCON 0x00000004UL
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#define RCC_BATS_IWDT 0x00000001UL
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/**
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* @}
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*/
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/** @defgroup reset_define reset_define
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* @{
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*/
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#define RCC_RST_PIN 0x01UL
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#define RCC_RST_ALARM_WWDT 0x02UL
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#define RCC_RST_ALARM_IWDT 0x04UL
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#define RCC_RST_DBG 0x08UL
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#define RCC_RST_POR 0x10UL
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#define RCC_RST_S7816 0x20UL
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#define RCC_RST_ALARM_SENIP 0x40UL
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#define RCC_RST_ALARM_SEC 0x80UL
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/**
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* @}
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*/
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/** @defgroup USB_source_clock_define USB source clock
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* @{
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*/
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#define RCC_USB_CLKSRC_HSE 0x00000002UL
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#define RCC_USB_CLKSRC_USBPHY 0x00000001UL
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#define RCC_USB_CLKSRC_PLL_L 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup system_source_clock_define system source clock
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* @{
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*/
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#define RCC_SYS_CLKSRC_HSI 0x00000000UL
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#define RCC_SYS_CLKSRC_PLL_H 0x00000001UL
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#define RCC_SYS_CLKSRC_USBPHY 0x00000002UL
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#define RCC_SYS_CLKSRC_HSE 0x00000003UL
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/**
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* @}
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*/
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/** @defgroup PLL_source_clock_define PLL source clock
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* @{
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*/
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#define RCC_PLLC_PLLSRC_HSI 0x00000000UL
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#define RCC_PLLC_PLLSRC_HSE 0x00000001UL
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/**
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* @}
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*/
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/** @defgroup SPI2_source_clock_define SPI2 source clock
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* @{
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*/
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#define RCC_SPI2_CLKSRC_PLL_H 0x00000002UL
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#define RCC_SPI2_CLKSRC_HSE 0x00000001UL
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#define RCC_SPI2_CLKSRC_HSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup ADC_source_clock_define ADC source clock
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* @{
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*/
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#define RCC_ADC_CLKSRC_PLL_L 0x00000002UL
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#define RCC_ADC_CLKSRC_HSE 0x00000001UL
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#define RCC_ADC_CLKSRC_HSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup 7816M_source_clock_define 7816master source clock
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* @{
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*/
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#define RCC_7816M_CLKSRC_PLL_L 0x00000002UL
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#define RCC_7816M_CLKSRC_HSE 0x00000001UL
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#define RCC_7816M_CLKSRC_HSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup 7816M_interface_number_define 7816master interface number
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* @{
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*/
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#define INTERFACE_7816M1 0x00000000U
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#define INTERFACE_7816M2 0x00000001U
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#define INTERFACE_7816M3 0x00000002U
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/**
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* @}
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*/
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/** @defgroup PWM_source_clock_define PWM source clock define
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* @{
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*/
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#define RCC_PWM_CLKSRC_PLL_L 0x00000002UL
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#define RCC_PWM_CLKSRC_HSE 0x00000001UL
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#define RCC_PWM_CLKSRC_HSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup PWM_interface_number_define PWM interface number
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* @{
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*/
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#define INTERFACE_PWM1 0x00U
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#define INTERFACE_PWM2 0x01U
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/**
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* @}
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*/
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/** @defgroup SWP_source_clock_define SWP source clock
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* @{
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*/
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#define RCC_SWP_CLKSRC_PLL_L 0x00000003UL
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#define RCC_SWP_CLKSRC_HSE 0x00000002UL
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#define RCC_SWP_CLKSRC_HSISWP 0x00000001UL
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#define RCC_SWP_CLKSRC_HSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup TIMER_source_clock_define TIMER source clock
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* @{
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*/
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#define RCC_TIMER_CLKSRC_PLL_L 0x00000002UL
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#define RCC_TIMER_CLKSRC_HSE 0x00000001UL
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#define RCC_TIMER_CLKSRC_HSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup TIMER_peripheral_number_define TIMER peripheral number
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* @{
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*/
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#define PERIPHERAL_TIMER1 0x00000000UL
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#define PERIPHERAL_TIMER2 0x00000001UL
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#define PERIPHERAL_TIMER3 0x00000002UL
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#define PERIPHERAL_TIMER4 0x00000003UL
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#define PERIPHERAL_TIMER5 0x00000004UL
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#define PERIPHERAL_TIMER6 0x00000005UL
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#define PERIPHERAL_WWDT 0x00000006UL
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/**
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* @}
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*/
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/** @defgroup WWDT_source_clock_define WWDT source clock
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* @{
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*/
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#define RCC_WWDT_CLKSRC_PLL_L 0x00000002UL
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#define RCC_WWDT_CLKSRC_HSE 0x00000001UL
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#define RCC_WWDT_CLKSRC_HSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup system_timer_clock_define system timer clock
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* @{
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*/
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#define RCC_SYSTICK_CLKSRC_HSI 0x00000000UL
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#define RCC_SYSTICK_CLKSRC_PLL_H 0x00000001UL
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#define RCC_SYSTICK_CLKSRC_USBPHY 0x00000002UL
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#define RCC_SYSTICK_CLKSRC_HSE 0x00000003UL
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#define RCC_SYSTICK_CLKDIV_0 0x00000000UL
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#define RCC_SYSTICK_CLKDIV_2 0x00000001UL
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#define RCC_SYSTICK_CLKDIV_4 0x00000002UL
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#define RCC_SYSTICK_CLKDIV_8 0x00000003UL
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#define RCC_SYSTICK_CLKDIV_16 0x00000004UL
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#define RCC_SYSTICK_CLKDIV_32 0x00000005UL
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/**
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* @}
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*/
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/** @defgroup monitor_clock_define monitor clock
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* @{
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*/
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#define RCC_MONITOR_CLKSRC_HSI_SWP 0x00000007UL
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#define RCC_MONITOR_CLKSRC_LSE 0x00000006UL
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#define RCC_MONITOR_CLKSRC_LSI 0x00000005UL
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#define RCC_MONITOR_CLKSRC_USBPHY 0x00000004UL
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#define RCC_MONITOR_CLKSRC_PLL_H 0x00000003UL
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#define RCC_MONITOR_CLKSRC_PLL_L 0x00000002UL
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#define RCC_MONITOR_CLKSRC_HSE 0x00000001UL
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#define RCC_MONITOR_CLKSRC_HSI 0x00000000UL
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#define RCC_MONITOR_CLKDIV_0 0x00000000UL
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#define RCC_MONITOR_CLKDIV_2 0x00000001UL
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#define RCC_MONITOR_CLKDIV_4 0x00000002UL
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#define RCC_MONITOR_CLKDIV_8 0x00000003UL
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#define RCC_MONITOR_CLKDIV_16 0x00000004UL
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#define RCC_MONITOR_CLKDIV_32 0x00000005UL
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/**
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* @}
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*/
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/** @defgroup BAT_clock_define BAT clock define
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* @{
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*/
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#define RCC_BAT_CLKSRC_LSE 0x00000001UL
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#define RCC_BAT_CLKSRC_LSI 0x00000000UL
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#define RCC_BAT_CLKDIV_0 0x00000000UL
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#define RCC_BAT_CLKDIV_2 0x00000001UL
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#define RCC_RTC_CLKSRC_LSE 0x00000001UL
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#define RCC_RTC_CLKSRC_LSI 0x00000000UL
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/**
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* @}
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*/
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/** @defgroup alarm_reset_define alarm reset
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* @{
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*/
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#define RCC_ALARM_RSTEN_IWDT 0x00000002UL
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#define RCC_ALARM_RSTEN_WWDT 0x00000001UL
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/**
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* @}
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*/
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/** @defgroup BAT_reset_define BAT reset
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* @{
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*/
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#define RCC_BAT_RSTEN_VBSENSOR 0x00000020UL
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#define RCC_BAT_RSTEN_VBATGPIO 0x00000010UL
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#define RCC_BAT_RSTEN_STDBY 0x00000004UL
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#define RCC_BAT_RSTEN_RTC 0x00000002UL
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#define RCC_BAT_RSTEN_IWDT 0x00000001UL
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/**
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* @}
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*/
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/** @defgroup CLK_interrupt_define CLK interrupt
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* @{
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*/
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#define RCC_IT_PLLRDY 0x00000004UL
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#define RCC_IT_HSERDY 0x00000002UL
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#define RCC_IT_HSIRDY 0x00000001UL
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/**
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* @}
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*/
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/** @defgroup RCC_clockflag_define RCC clockflag
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* @{
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*/
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#define RCC_FLAG_HSIRDY 0x00000000UL
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#define RCC_FLAG_HSERDY 0x00000001UL
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#define RCC_FLAG_PLLRDY 0x00000002UL
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#define RCC_FLAG_LSIRDY 0x00000003UL
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#define RCC_FLAG_LSERDY 0x00000004UL
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @addtogroup RCC_Exported_Functions
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* @{
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*/
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void RCC_DeInit(void);
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void RCC_SystemClockConfig(uint32_t source, uint32_t division);
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uint32_t RCC_GetSystemClockSource(void);
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uint32_t RCC_GetSystemClockDivision(void);
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void RCC_USBClockConfig(uint32_t source, FunctionalState NewState);
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void RCC_SPI2ClockConfig(uint32_t source, FunctionalState NewState);
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void RCC_ADCClockConfig(uint32_t source, FunctionalState NewState);
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void RCC_7816MClockConfig(uint8_t interface, uint32_t source, uint32_t division, FunctionalState NewState);
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void RCC_PWMClockConfig(uint8_t interface, uint32_t source, uint32_t division, FunctionalState NewState);
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void RCC_SWPClockConfig(uint32_t source, uint32_t division, FunctionalState NewState);
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void RCC_TimerClockConfig(uint8_t peripheral, uint32_t source, uint32_t division, FunctionalState NewState);
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void RCC_WWDTClockConfig(uint32_t source, uint32_t division, FunctionalState NewState);
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void RCC_SysTickClockConfig(uint32_t source, uint32_t division, FunctionalState NewState);
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void RCC_MonitorClockConfig(uint32_t source, uint32_t division, FunctionalState NewState);
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void RCC_BATClockConfig(uint32_t source, uint32_t division);
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void RCC_RTCClockConfig(uint32_t source, FunctionalState NewState);
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void RCC_HSEConfig(RCC_HSEConfigTypeDef *HSE_Config,FunctionalState NewState);
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void RCC_HSICmd(FunctionalState NewState);
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void RCC_PLLConfig(RCC_PLL_InitTypeDef *PLL_Config);
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void RCC_PLLCmd(FunctionalState NewState);
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uint32_t RCC_GetPLLClockSource(void);
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void RCC_LSICmd(FunctionalState NewState);
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void RCC_LSECmd(FunctionalState NewState, FunctionalState ResState);
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FlagStatus RCC_GetFlagStatus(uint32_t RCC_FLAG);
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uint32_t RCC_GetSysClocksFreq(void);
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void RCC_ITConfig(uint32_t Msk,FunctionalState NewState);
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FlagStatus RCC_GetResetStatus(uint32_t status);
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void RCC_ClearResetStatus(uint32_t Status);
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void RCC_AHBClockCmd(uint32_t RCC_AHBPerfor, FunctionalState NewState);
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void RCC_AHBPerforClockCmdInSleepMode(uint32_t RCC_AHBPerfor, FunctionalState NewState);
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void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
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void RCC_APB2PeriphClockCmdInSleepMode(uint32_t RCC_APB2Periph, FunctionalState NewState);
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void RCC_APB3PeriphClockCmd(uint32_t RCC_APB3Periph, FunctionalState NewState);
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void RCC_APB3PeriphClockCmdInSleepMode(uint32_t RCC_APB3Periph, FunctionalState NewState);
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void RCC_Security1PeriphClockCmd(uint32_t RCC_SEC1Periph, FunctionalState NewState);
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void RCC_Security1PeriphClockSleepCmd(uint32_t RCC_SEC1Periph, FunctionalState NewState);
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void RCC_Security2PeriphClockCmd(uint32_t RCC_SEC2Periph, FunctionalState NewState);
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void RCC_Security2PeriphClockSleepCmd(uint32_t RCC_SEC2Periph, FunctionalState NewState);
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void RCC_BATSecurityClockCmd(uint32_t BAT_Security, FunctionalState NewState);
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void RCC_AHBPeriphSoftReset(uint32_t RCC_AHBPeriph);
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void RCC_APB2PeriphSoftReset(uint32_t RCC_APB2Periph);
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void RCC_APB3PeriphSoftReset(uint32_t RCC_APB3Periph);
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void RCC_Security1PeriphSoftReset(uint32_t RCC_SEC1Periph);
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void RCC_Security2PeriphSoftReset(uint32_t RCC_SEC2Periph);
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void RCC_WDTResetSystemCmd(uint32_t RCC_WDT, FunctionalState NewState);
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void RCC_BATSoftResetCmd(uint32_t RCC_BAT);
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FlagStatus RCC_AHBPeriphGetResetFlag(uint32_t RCC_AHBPeriph);
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FlagStatus RCC_APB2PeriphGetResetFlag(uint32_t RCC_APB2Periph);
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FlagStatus RCC_APB3PeriphGetResetFlag(uint32_t RCC_APB3Periph);
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FlagStatus RCC_Security1PeriphGetResetFlag(uint32_t RCC_SEC1Periph);
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FlagStatus RCC_Security2PeriphGetResetFlag(uint32_t RCC_SEC2Periph);
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uint32_t RCC_GetPLL_L_Clock(void);
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uint32_t RCC_GetSystermClkSource(void);
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uint32_t RCC_GetSystermClkDiv(void);
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uint32_t RCC_GetPLL_H_Clock(void);
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/**
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* @}
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*/
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/** @defgroup RCC_Private_Macros RCC Private Macros
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* @{
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*/
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#define IS_SYSTEM_DIVSION_PARAMETER_OUT(b) ((b>=0)||(b<32))
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#define IS_PLLQ_PARAMETR_OUT(b) ((b==2)||(b==4)||(b==6)||(b==8))
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#define IS_PLLM_PARAMETR_OUT(b) ((b==1)||(b==2)||(b==3)||(b==4))
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#define IS_PLLN_PARAMETR_OUT(b) ((b>=10)||(b<=127))
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#define IS_SYSTEM_DIV(b) (b<=31)
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#define IS_7816M_DIV(b) (b<=31)
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#define IS_MONITOR_DIV(b)(b<=5)
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#define IS_RCC_AHBPeriph(PERIPH) (((PERIPH) == RCC_AHBPeriph_DMA) || \
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((PERIPH) == RCC_AHBPeriph_DCMI) || \
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((PERIPH) == RCC_AHBPeriph_SPI2) || \
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((PERIPH) == RCC_AHBPeriph_FLASHCACHE))
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#define IS_RCC_APB2Periph(PERIPH) (((PERIPH) == RCC_APB2Periph_SPI1) || \
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((PERIPH) == RCC_APB2Periph_SPI3) || \
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((PERIPH) == RCC_APB2Periph_UART1) || \
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((PERIPH) == RCC_APB2Periph_TIMER1_2) || \
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((PERIPH) == RCC_APB2Periph_TIMER5_6) || \
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((PERIPH) == RCC_APB2Periph_I2C) || \
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((PERIPH) == RCC_APB2Periph_7816M1) || \
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((PERIPH) == RCC_APB2Periph_ADC) || \
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((PERIPH) == RCC_APB2Periph_CRC) || \
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((PERIPH) == RCC_APB2Periph_WDT) || \
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((PERIPH) == RCC_APB2Periph_PWM1) || \
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((PERIPH) == RCC_APB2Periph_7816M3) || \
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((PERIPH) == RCC_APB2Periph_UART3))
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#define IS_RCC_APB3Periph(PERIPH) (((PERIPH) == RCC_APB3Periph_FSMC) || \
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((PERIPH) == RCC_APB3Periph_UART4) || \
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((PERIPH) == RCC_APB3Periph_UART2) || \
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((PERIPH) == RCC_APB3Periph_TIMER3_4) || \
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((PERIPH) == RCC_APB3Periph_GPIO) || \
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((PERIPH) == RCC_APB3Periph_7816S) || \
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((PERIPH) == RCC_APB3Periph_UART4) || \
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((PERIPH) == RCC_APB3Periph_7816M2) || \
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((PERIPH) == RCC_APB3Periph_PWM2))
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#define IS_RCC_SEC1Periph(PERIPH) (((PERIPH) == RCC_SEC1Periph_INT) || \
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((PERIPH) == RCC_SEC1Periph_PWRC) || \
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((PERIPH) == RCC_SEC1Periph_SM4) || \
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((PERIPH) == RCC_SEC1Periph_AES) || \
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((PERIPH) == RCC_SEC1Periph_DES) || \
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((PERIPH) == RCC_SEC1Periph_PKE) || \
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((PERIPH) == RCC_SEC1Periph_SWP) || \
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((PERIPH) == RCC_SEC1Periph_TRNG) || \
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((PERIPH) == RCC_SEC1Periph_ActiveShield) || \
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((PERIPH) == RCC_SEC1Periph_ExternalVoltageGlitchDetection) || \
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((PERIPH) == RCC_SEC1Periph_LightDerector) || \
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((PERIPH) == RCC_SEC1Periph_FrequencyDerector) || \
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((PERIPH) == RCC_SEC1Periph_VBSENSOR))
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#define IS_RCC_SEC2Periph(PERIPH) (((PERIPH) == RCC_SEC2Periph_FLASH) || \
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((PERIPH) == RCC_SEC2Periph_USB))
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#define IS_RCC_BATFUNC(FUNCTION) (((FUNCTION) == RCC_BATS_SENSOR) || \
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((FUNCTION) == RCC_BATS_STDBYCON) || \
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((FUNCTION) == RCC_BATS_IWDT))
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#define IS_RCC_RESET(RESET) (((RESET) == RCC_RST_PIN) || \
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((RESET) == RCC_RST_ALARM_WWDT)|| \
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((RESET) == RCC_RST_ALARM_IWDT)|| \
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((RESET) == RCC_RST_DBG)|| \
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((RESET) == RCC_RST_POR)|| \
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((RESET) == RCC_RST_S7816)|| \
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((RESET) == RCC_RST_ALARM_SENIP)|| \
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((RESET) == RCC_RST_ALARM_SEC))
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#define IS_RCC_USB_CLKSOURCE(SOURCE) (((SOURCE) == RCC_USB_CLKSRC_USBPHY) || \
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((SOURCE) == RCC_USB_CLKSRC_PLL_L) || \
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((SOURCE) == RCC_USB_CLKSRC_HSE))
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#define IS_RCC_SYS_CLKSOURCE(SOURCE) (((SOURCE) == RCC_SYS_CLKSRC_HSI) || \
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((SOURCE) == RCC_SYS_CLKSRC_PLL_H) || \
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((SOURCE) == RCC_SYS_CLKSRC_USBPHY) || \
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((SOURCE) == RCC_SYS_CLKSRC_HSE))
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#define IS_RCC_PLL_CLKSOURCE(SOURCE) (((SOURCE) == RCC_PLLC_PLLSRC_HSI) || \
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((SOURCE) == RCC_PLLC_PLLSRC_HSE))
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#define IS_RCC_SPI2_CLKSOURCE(SOURCE) (((SOURCE) == RCC_SPI2_CLKSRC_PLL_H) || \
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((SOURCE) == RCC_SPI2_CLKSRC_HSE) || \
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((SOURCE) == RCC_SPI2_CLKSRC_HSI))
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#define IS_RCC_ADC_CLKSOURCE(SOURCE) (((SOURCE) == RCC_ADC_CLKSRC_PLL_L) || \
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((SOURCE) == RCC_ADC_CLKSRC_HSE) || \
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((SOURCE) == RCC_ADC_CLKSRC_HSI))
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#define IS_RCC_7816M_CLKSOURCE(SOURCE) (((SOURCE) == RCC_7816M_CLKSRC_PLL_L) || \
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((SOURCE) == RCC_7816M_CLKSRC_HSE) || \
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((SOURCE) == RCC_7816M_CLKSRC_HSI))
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#define IS_RCC_7816M_NUMBER(NUMBER) (((NUMBER) == INTERFACE_7816M1) || \
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((NUMBER) == INTERFACE_7816M2) || \
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((NUMBER) == INTERFACE_7816M3))
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#define IS_RCC_PWM_CLKSOURCE(SOURCE) (((SOURCE) == RCC_PWM_CLKSRC_PLL_L) || \
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((SOURCE) == RCC_PWM_CLKSRC_HSE) || \
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((SOURCE) == RCC_PWM_CLKSRC_HSI))
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#define IS_RCC_PWM_NUMBER(NUMBER) (((NUMBER) == INTERFACE_PWM1) || \
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((NUMBER) == INTERFACE_PWM2))
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#define IS_RCC_SWP_CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWP_CLKSRC_PLL_L) || \
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((SOURCE) == RCC_SWP_CLKSRC_HSE) || \
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((SOURCE) == RCC_SWP_CLKSRC_HSISWP) || \
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((SOURCE) == RCC_SWP_CLKSRC_HSI))
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#define IS_RCC_TIMER_CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIMER_CLKSRC_PLL_L) || \
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((SOURCE) == RCC_TIMER_CLKSRC_HSE) || \
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((SOURCE) == RCC_TIMER_CLKSRC_HSI))
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#define IS_RCC_TIMER_NUMBER(NUMBER) (((NUMBER) == PERIPHERAL_TIMER1) || \
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((NUMBER) == PERIPHERAL_TIMER2) || \
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((NUMBER) == PERIPHERAL_TIMER3) || \
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((NUMBER) == PERIPHERAL_TIMER4) ||\
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((NUMBER) == PERIPHERAL_TIMER5) ||\
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((NUMBER) == PERIPHERAL_TIMER6))
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#define IS_RCC_WWDT_CLKSOURCE(SOURCE) (((SOURCE) == RCC_WWDT_CLKSRC_PLL_L) || \
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((SOURCE) == RCC_WWDT_CLKSRC_HSE) || \
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((SOURCE) == RCC_WWDT_CLKSRC_HSI))
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|
#define IS_RCC_SYSTICK_CLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSTICK_CLKSRC_HSE) || \
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((SOURCE) == RCC_SYSTICK_CLKSRC_USBPHY)|| \
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((SOURCE) == RCC_SYSTICK_CLKSRC_PLL_H) || \
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((SOURCE) == RCC_SYSTICK_CLKSRC_HSI))
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|
#define IS_RCC_SYSTICK_CLKDIV(DIVISION) (((DIVISION) == RCC_SYSTICK_CLKDIV_0) || \
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((DIVISION) == RCC_SYSTICK_CLKDIV_2) || \
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((DIVISION) == RCC_SYSTICK_CLKDIV_4) || \
|
|
((DIVISION) == RCC_SYSTICK_CLKDIV_8) || \
|
|
((DIVISION) == RCC_SYSTICK_CLKDIV_16) || \
|
|
((DIVISION) == RCC_SYSTICK_CLKDIV_32))
|
|
|
|
#define IS_RCC_MONITOR_CLKSOURCE(SOURCE) (((SOURCE) == RCC_MONITOR_CLKSRC_PLL_L)||((SOURCE) == RCC_MONITOR_CLKSRC_HSE)||((SOURCE) == RCC_MONITOR_CLKSRC_HSI))
|
|
|
|
#define IS_RCC_MONITOR_CLKDIV(DIVISION) (((DIVISION) == RCC_MONITOR_CLKDIV_0) || \
|
|
((DIVISION) == RCC_MONITOR_CLKDIV_2) || \
|
|
((DIVISION) == RCC_MONITOR_CLKDIV_4) || \
|
|
((DIVISION) == RCC_MONITOR_CLKDIV_8) || \
|
|
((DIVISION) == RCC_MONITOR_CLKDIV_16) || \
|
|
((DIVISION) == RCC_MONITOR_CLKDIV_32))
|
|
#define IS_RCC_BAT_CLKSOURCE(SOURCE) (((SOURCE) == RCC_BAT_CLKSRC_LSE) || \
|
|
((SOURCE) == RCC_BAT_CLKSRC_LSI))
|
|
#define IS_RCC_BAT_CLKDIV(DIVISION) (((DIVISION) == RCC_BAT_CLKDIV_0) || \
|
|
((DIVISION) == RCC_BAT_CLKDIV_2))
|
|
#define IS_RCC_RTC_CLKSOURCE(SOURCE) (((SOURCE) == RCC_RTC_CLKSRC_LSE) || \
|
|
((SOURCE) == RCC_RTC_CLKSRC_LSI))
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
/**
|
|
* @}
|
|
*/
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
/************************ (C) COPYRIGHT TMC *****END OF FILE****/
|