78 lines
3.8 KiB
C
78 lines
3.8 KiB
C
/********************************************************************************
|
|
* Copyright (c) 2012, Beijing Tongfang Microelectroics Co., Ltd.
|
|
* All rights reserved.
|
|
* Module: I2C
|
|
* Author: yanghf
|
|
* Version: V1.0
|
|
* History:
|
|
* 2012-09-24 Original version
|
|
********************************************************************************/
|
|
|
|
#ifndef __IIC_MAIN_H_
|
|
#define __IIC_MAIN_H_
|
|
|
|
//CTRL
|
|
#define I2C_CTRL_ENS1_MASK ((uint8_t)0x40)
|
|
#define I2C_CTRL_STA_MASK ((uint8_t)0x20)
|
|
#define I2C_CTRL_STO_MASK ((uint8_t)0x10)
|
|
#define I2C_CTRL_SI_MASK ((uint8_t)0x08)
|
|
#define I2C_CTRL_AA_MASK ((uint8_t)0x04)
|
|
|
|
#define I2C_CTRL_SCLCLOCK_PCLK_256 ((uint8_t)0x00)
|
|
#define I2C_CTRL_SCLCLOCK_PCLK_224 ((uint8_t)0x01)
|
|
#define I2C_CTRL_SCLCLOCK_PCLK_192 ((uint8_t)0x02)
|
|
#define I2C_CTRL_SCLCLOCK_PCLK_160 ((uint8_t)0x03)
|
|
#define I2C_CTRL_SCLCLOCK_PCLK_960 ((uint8_t)0x80)
|
|
#define I2C_CTRL_SCLCLOCK_PCLK_120 ((uint8_t)0x81)
|
|
#define I2C_CTRL_SCLCLOCK_PCLK_60 ((uint8_t)0x82)
|
|
#define I2C_CTRL_SCLCLOCK_BCLK_8 ((uint8_t)0x83)
|
|
|
|
//STAT
|
|
/* -- MASTER STATES -- */
|
|
#define STAT_BUS_ERROR 0x00u /* Bus error during MST or selected slave modes */
|
|
#define STAT_I2C_IDLE 0xF8u /* No activity and no interrupt either... */
|
|
#define STAT_START 0x08u /* start condition sent */
|
|
#define STAT_RESTART 0x10u /* repeated start */
|
|
#define STAT_SLAW_ACK 0x18u /* SLA+W sent, ack received */
|
|
#define STAT_SLAW_NACK 0x20u /* SLA+W sent, nack received */
|
|
#define STAT_TX_DATA_ACK 0x28u /* Data sent, ACK'ed */
|
|
#define STAT_TX_DATA_NACK 0x30u /* Data sent, NACK'ed */
|
|
#define STAT_LOST_ARB 0x38u /* Master lost arbitration */
|
|
#define STAT_SLAR_ACK 0x40u /* SLA+R sent, ACK'ed */
|
|
#define STAT_SLAR_NACK 0x48u /* SLA+R sent, NACK'ed */
|
|
#define STAT_RX_DATA_ACK 0x50u /* Data received, ACK sent */
|
|
#define STAT_RX_DATA_NACK 0x58u /* Data received, NACK sent */
|
|
#define STAT_RESET_ACTIVATED 0xD0u /* Master reset is activated */
|
|
#define STAT_STOP_TRANSMIT 0xE0u /* Stop has been transmitted */
|
|
|
|
/* -- SLAVE STATES -- */
|
|
#define STAT_SLAVE_SLAW 0x60u /* SLA+W received */
|
|
#define STAT_SLAVE_SLAR_ACK 0xA8u /* SLA+R received, ACK returned */
|
|
#define STAT_SLV_LA 0x68u /* Slave lost arbitration */
|
|
#define STAT_GCA 0x70u /* GCA received */
|
|
#define STAT_GCA_LA 0x78u /* GCA lost arbitration */
|
|
#define STAT_RDATA 0x80u /* Data received */
|
|
#define STAT_SLA_NACK 0x88u /* Slave addressed, NACK returned */
|
|
#define STAT_GCA_ACK 0x90u /* Previously addresses with GCA, data ACKed */
|
|
#define STAT_GCA_NACK 0x98u /* GCA addressed, NACK returned */
|
|
#define STAT_RSTOP 0xA0u /* Stop received */
|
|
#define STAT_SLARW_LA 0xB0u /* Arbitration lost */
|
|
#define STAT_RACK 0xB8u /* Byte sent, ACK received */
|
|
#define STAT_SLAVE_RNACK 0xC0u /* Byte sent, NACK received */
|
|
#define STAT_FINAL 0xC8u /* Final byte sent, ACK received */
|
|
#define STAT_SLV_RST 0xD8u /* Slave reset state */
|
|
|
|
//DATA
|
|
#define DATA_WRITE_DIR 0x00u
|
|
#define DATA_READ_DIR 0x01u
|
|
|
|
|
|
void IIC_Slave_CFG(I2C_TypeDef* I2Cx, uint8_t clock_speed,uint8_t ser_address);
|
|
//void I2C_Master_SendBytes(I2C_TypeDef* I2Cx,uint8_t slaveaddr,uint8_t *bytes,uint16_t lens);
|
|
//void I2C_Master_ReceiveBytes(I2C_TypeDef* I2Cx,uint8_t slaveaddr,uint8_t *bytes,uint16_t lens);
|
|
void I2C_Slave_ReceiveBytes(I2C_TypeDef* I2Cx,uint8_t *bytes,uint16_t lens);
|
|
void I2C_Slave_SendBytes(I2C_TypeDef* I2Cx,uint8_t *bytes,uint16_t lens);
|
|
|
|
#endif
|
|
|