/dts-v1/;

/ {
	compatible = "rockchip,px30-evb-ddr4-v10", "rockchip,px30";
	interrupt-parent = <0x1>;
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	model = "Rockchip FSPX30002TV board";

	ddr_timing {
		compatible = "rockchip,ddr-timing";
		ddr2_speed_bin = <0x0>;
		ddr3_speed_bin = <0x15>;
		ddr4_speed_bin = <0xc>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		auto_pd_dis_freq = <0x42a>;
		auto_sr_dis_freq = <0x320>;
		ddr2_dll_dis_freq = <0x12c>;
		ddr3_dll_dis_freq = <0x12c>;
		ddr4_dll_dis_freq = <0x271>;
		phy_dll_dis_freq = <0x190>;
		ddr2_odt_dis_freq = <0x64>;
		phy_ddr2_odt_dis_freq = <0x64>;
		ddr2_drv = <0x1>;
		ddr2_odt = <0x96>;
		phy_ddr2_ca_drv = <0x15>;
		phy_ddr2_ck_drv = <0x12>;
		phy_ddr2_dq_drv = <0x15>;
		phy_ddr2_odt = <0x2>;
		ddr3_odt_dis_freq = <0x190>;
		phy_ddr3_odt_dis_freq = <0x190>;
		ddr3_drv = <0x28>;
		ddr3_odt = <0x78>;
		phy_ddr3_ca_drv = <0x15>;
		phy_ddr3_ck_drv = <0x12>;
		phy_ddr3_dq_drv = <0x15>;
		phy_ddr3_odt = <0x2>;
		phy_lpddr2_odt_dis_freq = <0x29a>;
		lpddr2_drv = <0x28>;
		phy_lpddr2_ca_drv = <0x16>;
		phy_lpddr2_ck_drv = <0x13>;
		phy_lpddr2_dq_drv = <0x16>;
		phy_lpddr2_odt = <0x0>;
		lpddr3_odt_dis_freq = <0x190>;
		phy_lpddr3_odt_dis_freq = <0x190>;
		lpddr3_drv = <0x28>;
		lpddr3_odt = <0xf0>;
		phy_lpddr3_ca_drv = <0x16>;
		phy_lpddr3_ck_drv = <0x13>;
		phy_lpddr3_dq_drv = <0x16>;
		phy_lpddr3_odt = <0x2>;
		lpddr4_odt_dis_freq = <0x320>;
		phy_lpddr4_odt_dis_freq = <0x320>;
		lpddr4_drv = <0x3c>;
		lpddr4_dq_odt = <0x28>;
		lpddr4_ca_odt = <0x28>;
		phy_lpddr4_ca_drv = <0x14>;
		phy_lpddr4_ck_cs_drv = <0x6>;
		phy_lpddr4_dq_drv = <0x6>;
		phy_lpddr4_odt = <0x10>;
		ddr4_odt_dis_freq = <0x29a>;
		phy_ddr4_odt_dis_freq = <0x29a>;
		ddr4_drv = <0x22>;
		ddr4_odt = <0xf0>;
		phy_ddr4_ca_drv = <0x16>;
		phy_ddr4_ck_drv = <0x13>;
		phy_ddr4_dq_drv = <0x16>;
		phy_ddr4_odt = <0x2>;
		ddr3a1_ddr4a9_de-skew = <0x6>;
		ddr3a0_ddr4a10_de-skew = <0x7>;
		ddr3a3_ddr4a6_de-skew = <0x7>;
		ddr3a2_ddr4a4_de-skew = <0x7>;
		ddr3a5_ddr4a8_de-skew = <0x7>;
		ddr3a4_ddr4a5_de-skew = <0x7>;
		ddr3a7_ddr4a11_de-skew = <0x7>;
		ddr3a6_ddr4a7_de-skew = <0x6>;
		ddr3a9_ddr4a0_de-skew = <0x7>;
		ddr3a8_ddr4a13_de-skew = <0x7>;
		ddr3a11_ddr4a3_de-skew = <0x7>;
		ddr3a10_ddr4cs0_de-skew = <0x7>;
		ddr3a13_ddr4a2_de-skew = <0x7>;
		ddr3a12_ddr4ba1_de-skew = <0x7>;
		ddr3a15_ddr4odt0_de-skew = <0x7>;
		ddr3a14_ddr4a1_de-skew = <0x7>;
		ddr3ba1_ddr4a15_de-skew = <0x7>;
		ddr3ba0_ddr4bg0_de-skew = <0x7>;
		ddr3ras_ddr4cke_de-skew = <0x7>;
		ddr3ba2_ddr4ba0_de-skew = <0x7>;
		ddr3we_ddr4bg1_de-skew = <0x7>;
		ddr3cas_ddr4a12_de-skew = <0x7>;
		ddr3ckn_ddr4ckn_de-skew = <0x7>;
		ddr3ckp_ddr4ckp_de-skew = <0x7>;
		ddr3cke_ddr4a16_de-skew = <0x7>;
		ddr3odt0_ddr4a14_de-skew = <0x7>;
		ddr3cs0_ddr4act_de-skew = <0x6>;
		ddr3reset_ddr4reset_de-skew = <0x7>;
		ddr3cs1_ddr4cs1_de-skew = <0x6>;
		ddr3odt1_ddr4odt1_de-skew = <0x7>;
		cs0_dm0_rx_de-skew = <0x7>;
		cs0_dm0_tx_de-skew = <0x7>;
		cs0_dq0_rx_de-skew = <0x8>;
		cs0_dq0_tx_de-skew = <0x8>;
		cs0_dq1_rx_de-skew = <0x9>;
		cs0_dq1_tx_de-skew = <0x8>;
		cs0_dq2_rx_de-skew = <0x8>;
		cs0_dq2_tx_de-skew = <0x8>;
		cs0_dq3_rx_de-skew = <0x8>;
		cs0_dq3_tx_de-skew = <0x8>;
		cs0_dq4_rx_de-skew = <0x9>;
		cs0_dq4_tx_de-skew = <0x8>;
		cs0_dq5_rx_de-skew = <0x9>;
		cs0_dq5_tx_de-skew = <0x8>;
		cs0_dq6_rx_de-skew = <0x9>;
		cs0_dq6_tx_de-skew = <0x8>;
		cs0_dq7_rx_de-skew = <0x8>;
		cs0_dq7_tx_de-skew = <0x8>;
		cs0_dqs0_rx_de-skew = <0x6>;
		cs0_dqs0p_tx_de-skew = <0x9>;
		cs0_dqs0n_tx_de-skew = <0x9>;
		cs0_dm1_rx_de-skew = <0x7>;
		cs0_dm1_tx_de-skew = <0x6>;
		cs0_dq8_rx_de-skew = <0x8>;
		cs0_dq8_tx_de-skew = <0x7>;
		cs0_dq9_rx_de-skew = <0x9>;
		cs0_dq9_tx_de-skew = <0x7>;
		cs0_dq10_rx_de-skew = <0x8>;
		cs0_dq10_tx_de-skew = <0x8>;
		cs0_dq11_rx_de-skew = <0x8>;
		cs0_dq11_tx_de-skew = <0x7>;
		cs0_dq12_rx_de-skew = <0x8>;
		cs0_dq12_tx_de-skew = <0x8>;
		cs0_dq13_rx_de-skew = <0x9>;
		cs0_dq13_tx_de-skew = <0x7>;
		cs0_dq14_rx_de-skew = <0x9>;
		cs0_dq14_tx_de-skew = <0x8>;
		cs0_dq15_rx_de-skew = <0x9>;
		cs0_dq15_tx_de-skew = <0x7>;
		cs0_dqs1_rx_de-skew = <0x7>;
		cs0_dqs1p_tx_de-skew = <0x9>;
		cs0_dqs1n_tx_de-skew = <0x9>;
		cs0_dm2_rx_de-skew = <0x7>;
		cs0_dm2_tx_de-skew = <0x7>;
		cs0_dq16_rx_de-skew = <0x9>;
		cs0_dq16_tx_de-skew = <0x9>;
		cs0_dq17_rx_de-skew = <0x7>;
		cs0_dq17_tx_de-skew = <0x9>;
		cs0_dq18_rx_de-skew = <0x7>;
		cs0_dq18_tx_de-skew = <0x8>;
		cs0_dq19_rx_de-skew = <0x7>;
		cs0_dq19_tx_de-skew = <0x9>;
		cs0_dq20_rx_de-skew = <0x9>;
		cs0_dq20_tx_de-skew = <0x9>;
		cs0_dq21_rx_de-skew = <0x9>;
		cs0_dq21_tx_de-skew = <0x9>;
		cs0_dq22_rx_de-skew = <0x8>;
		cs0_dq22_tx_de-skew = <0x9>;
		cs0_dq23_rx_de-skew = <0x8>;
		cs0_dq23_tx_de-skew = <0x9>;
		cs0_dqs2_rx_de-skew = <0x6>;
		cs0_dqs2p_tx_de-skew = <0x9>;
		cs0_dqs2n_tx_de-skew = <0x9>;
		cs0_dm3_rx_de-skew = <0x7>;
		cs0_dm3_tx_de-skew = <0x7>;
		cs0_dq24_rx_de-skew = <0x8>;
		cs0_dq24_tx_de-skew = <0x8>;
		cs0_dq25_rx_de-skew = <0x9>;
		cs0_dq25_tx_de-skew = <0x9>;
		cs0_dq26_rx_de-skew = <0x9>;
		cs0_dq26_tx_de-skew = <0x8>;
		cs0_dq27_rx_de-skew = <0x9>;
		cs0_dq27_tx_de-skew = <0x8>;
		cs0_dq28_rx_de-skew = <0x9>;
		cs0_dq28_tx_de-skew = <0x9>;
		cs0_dq29_rx_de-skew = <0x9>;
		cs0_dq29_tx_de-skew = <0x9>;
		cs0_dq30_rx_de-skew = <0x8>;
		cs0_dq30_tx_de-skew = <0x8>;
		cs0_dq31_rx_de-skew = <0x8>;
		cs0_dq31_tx_de-skew = <0x8>;
		cs0_dqs3_rx_de-skew = <0x7>;
		cs0_dqs3p_tx_de-skew = <0x9>;
		cs0_dqs3n_tx_de-skew = <0x9>;
		cs1_dm0_rx_de-skew = <0x7>;
		cs1_dm0_tx_de-skew = <0x7>;
		cs1_dq0_rx_de-skew = <0x8>;
		cs1_dq0_tx_de-skew = <0x8>;
		cs1_dq1_rx_de-skew = <0x9>;
		cs1_dq1_tx_de-skew = <0x8>;
		cs1_dq2_rx_de-skew = <0x8>;
		cs1_dq2_tx_de-skew = <0x8>;
		cs1_dq3_rx_de-skew = <0x8>;
		cs1_dq3_tx_de-skew = <0x8>;
		cs1_dq4_rx_de-skew = <0x8>;
		cs1_dq4_tx_de-skew = <0x8>;
		cs1_dq5_rx_de-skew = <0x9>;
		cs1_dq5_tx_de-skew = <0x8>;
		cs1_dq6_rx_de-skew = <0x9>;
		cs1_dq6_tx_de-skew = <0x8>;
		cs1_dq7_rx_de-skew = <0x8>;
		cs1_dq7_tx_de-skew = <0x8>;
		cs1_dqs0_rx_de-skew = <0x6>;
		cs1_dqs0p_tx_de-skew = <0x9>;
		cs1_dqs0n_tx_de-skew = <0x9>;
		cs1_dm1_rx_de-skew = <0x7>;
		cs1_dm1_tx_de-skew = <0x7>;
		cs1_dq8_rx_de-skew = <0x8>;
		cs1_dq8_tx_de-skew = <0x8>;
		cs1_dq9_rx_de-skew = <0x8>;
		cs1_dq9_tx_de-skew = <0x7>;
		cs1_dq10_rx_de-skew = <0x7>;
		cs1_dq10_tx_de-skew = <0x8>;
		cs1_dq11_rx_de-skew = <0x8>;
		cs1_dq11_tx_de-skew = <0x8>;
		cs1_dq12_rx_de-skew = <0x8>;
		cs1_dq12_tx_de-skew = <0x7>;
		cs1_dq13_rx_de-skew = <0x8>;
		cs1_dq13_tx_de-skew = <0x8>;
		cs1_dq14_rx_de-skew = <0x8>;
		cs1_dq14_tx_de-skew = <0x8>;
		cs1_dq15_rx_de-skew = <0x8>;
		cs1_dq15_tx_de-skew = <0x7>;
		cs1_dqs1_rx_de-skew = <0x7>;
		cs1_dqs1p_tx_de-skew = <0x9>;
		cs1_dqs1n_tx_de-skew = <0x9>;
		cs1_dm2_rx_de-skew = <0x7>;
		cs1_dm2_tx_de-skew = <0x8>;
		cs1_dq16_rx_de-skew = <0x8>;
		cs1_dq16_tx_de-skew = <0x9>;
		cs1_dq17_rx_de-skew = <0x8>;
		cs1_dq17_tx_de-skew = <0x9>;
		cs1_dq18_rx_de-skew = <0x7>;
		cs1_dq18_tx_de-skew = <0x8>;
		cs1_dq19_rx_de-skew = <0x8>;
		cs1_dq19_tx_de-skew = <0x9>;
		cs1_dq20_rx_de-skew = <0x9>;
		cs1_dq20_tx_de-skew = <0x9>;
		cs1_dq21_rx_de-skew = <0x9>;
		cs1_dq21_tx_de-skew = <0x9>;
		cs1_dq22_rx_de-skew = <0x8>;
		cs1_dq22_tx_de-skew = <0x9>;
		cs1_dq23_rx_de-skew = <0x8>;
		cs1_dq23_tx_de-skew = <0x9>;
		cs1_dqs2_rx_de-skew = <0x6>;
		cs1_dqs2p_tx_de-skew = <0x9>;
		cs1_dqs2n_tx_de-skew = <0x9>;
		cs1_dm3_rx_de-skew = <0x7>;
		cs1_dm3_tx_de-skew = <0x7>;
		cs1_dq24_rx_de-skew = <0x8>;
		cs1_dq24_tx_de-skew = <0x9>;
		cs1_dq25_rx_de-skew = <0x9>;
		cs1_dq25_tx_de-skew = <0x9>;
		cs1_dq26_rx_de-skew = <0x9>;
		cs1_dq26_tx_de-skew = <0x8>;
		cs1_dq27_rx_de-skew = <0x8>;
		cs1_dq27_tx_de-skew = <0x8>;
		cs1_dq28_rx_de-skew = <0x9>;
		cs1_dq28_tx_de-skew = <0x9>;
		cs1_dq29_rx_de-skew = <0x9>;
		cs1_dq29_tx_de-skew = <0x9>;
		cs1_dq30_rx_de-skew = <0x9>;
		cs1_dq30_tx_de-skew = <0x8>;
		cs1_dq31_rx_de-skew = <0x8>;
		cs1_dq31_tx_de-skew = <0x8>;
		cs1_dqs3_rx_de-skew = <0x7>;
		cs1_dqs3p_tx_de-skew = <0x9>;
		cs1_dqs3n_tx_de-skew = <0x9>;
		phandle = <0xb5>;
	};

	ddr3-params {
		version = <0x101>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x29a>;
		freq_1 = <0xc2>;
		freq_2 = <0x148>;
		freq_3 = <0x29a>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x12c>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x21>;
		phy_ca_drv_odten = <0x21>;
		phy_clk_drv_odten = <0x21>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x21>;
		phy_ca_drv_odtoff = <0x21>;
		phy_clk_drv_odtoff = <0x21>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x78>;
		phy_odt = <0x85>;
		phy_odt_puup_en = <0x1>;
		phy_odt_pudn_en = <0x1>;
		dram_dq_odt_en_freq = <0x14d>;
		phy_odt_en_freq = <0x14d>;
		phy_dq_sr_odten = <0xf>;
		phy_ca_sr_odten = <0x3>;
		phy_clk_sr_odten = <0x3>;
		phy_dq_sr_odtoff = <0xf>;
		phy_ca_sr_odtoff = <0x3>;
		phy_clk_sr_odtoff = <0x3>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0x15>;
		dram_ext_temp = <0x0>;
		byte_map = <0xb1>;
		dq_map_cs0_dq_l = <0x0>;
		dq_map_cs0_dq_h = <0x0>;
		dq_map_cs1_dq_l = <0x0>;
		dq_map_cs1_dq_h = <0x0>;
		phandle = <0xb6>;
	};

	ddr4-params {
		version = <0x101>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x29a>;
		freq_1 = <0xc2>;
		freq_2 = <0x148>;
		freq_3 = <0x29a>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x1f4>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x21>;
		phy_ca_drv_odten = <0x21>;
		phy_clk_drv_odten = <0x21>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x21>;
		phy_ca_drv_odtoff = <0x21>;
		phy_clk_drv_odtoff = <0x21>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x78>;
		phy_odt = <0x79>;
		phy_odt_puup_en = <0x1>;
		phy_odt_pudn_en = <0x1>;
		dram_dq_odt_en_freq = <0x1f4>;
		phy_odt_en_freq = <0x1f4>;
		phy_dq_sr_odten = <0xe>;
		phy_ca_sr_odten = <0x1>;
		phy_clk_sr_odten = <0x1>;
		phy_dq_sr_odtoff = <0xe>;
		phy_ca_sr_odtoff = <0x1>;
		phy_clk_sr_odtoff = <0x1>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0xc>;
		dram_ext_temp = <0x0>;
		byte_map = <0xb1>;
		dq_map_cs0_dq_l = <0x139b6273>;
		dq_map_cs0_dq_h = <0x272d6f42>;
		dq_map_cs1_dq_l = <0x46ce3726>;
		dq_map_cs1_dq_h = <0x72783a17>;
		phandle = <0xb7>;
	};

	lpddr2-params {
		version = <0x101>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x210>;
		freq_1 = <0xc2>;
		freq_2 = <0x148>;
		freq_3 = <0x210>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x0>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x21>;
		phy_ca_drv_odten = <0x21>;
		phy_clk_drv_odten = <0x21>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x21>;
		phy_ca_drv_odtoff = <0x21>;
		phy_clk_drv_odtoff = <0x21>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0x0>;
		phy_odt = <0x0>;
		phy_odt_puup_en = <0x0>;
		phy_odt_pudn_en = <0x0>;
		dram_dq_odt_en_freq = <0x271>;
		phy_odt_en_freq = <0x271>;
		phy_dq_sr_odten = <0xe>;
		phy_ca_sr_odten = <0x1>;
		phy_clk_sr_odten = <0x1>;
		phy_dq_sr_odtoff = <0xe>;
		phy_ca_sr_odtoff = <0x1>;
		phy_clk_sr_odtoff = <0x1>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0x0>;
		dram_ext_temp = <0x0>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x0>;
		dq_map_cs0_dq_h = <0x0>;
		dq_map_cs1_dq_l = <0x0>;
		dq_map_cs1_dq_h = <0x0>;
		phandle = <0xb8>;
	};

	lpddr3-params {
		version = <0x101>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x29a>;
		freq_1 = <0xc2>;
		freq_2 = <0x148>;
		freq_3 = <0x29a>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x0>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x21>;
		phy_ca_drv_odten = <0x21>;
		phy_clk_drv_odten = <0x21>;
		dram_dq_drv_odten = <0x22>;
		phy_dq_drv_odtoff = <0x21>;
		phy_ca_drv_odtoff = <0x21>;
		phy_clk_drv_odtoff = <0x21>;
		dram_dq_drv_odtoff = <0x22>;
		dram_odt = <0xf0>;
		phy_odt = <0x79>;
		phy_odt_puup_en = <0x1>;
		phy_odt_pudn_en = <0x1>;
		dram_dq_odt_en_freq = <0x14d>;
		phy_odt_en_freq = <0x14d>;
		phy_dq_sr_odten = <0x0>;
		phy_ca_sr_odten = <0x0>;
		phy_clk_sr_odten = <0x0>;
		phy_dq_sr_odtoff = <0x0>;
		phy_ca_sr_odtoff = <0x0>;
		phy_clk_sr_odtoff = <0x0>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0x0>;
		dram_ext_temp = <0x0>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x0>;
		dq_map_cs0_dq_h = <0x0>;
		dq_map_cs1_dq_l = <0x0>;
		dq_map_cs1_dq_h = <0x0>;
		phandle = <0xb9>;
	};

	lpddr4-params {
		version = <0x101>;
		expanded_version = <0x0>;
		reserved = <0x0>;
		freq_0 = <0x29a>;
		freq_1 = <0xc2>;
		freq_2 = <0x148>;
		freq_3 = <0x29a>;
		freq_4 = <0x0>;
		freq_5 = <0x0>;
		pd_idle = <0xd>;
		sr_idle = <0x5d>;
		sr_mc_gate_idle = <0x0>;
		srpd_lite_idle = <0x0>;
		standby_idle = <0x0>;
		pd_dis_freq = <0x42a>;
		sr_dis_freq = <0x320>;
		dram_dll_dis_freq = <0x0>;
		phy_dll_dis_freq = <0x0>;
		phy_dq_drv_odten = <0x23>;
		phy_ca_drv_odten = <0x26>;
		phy_clk_drv_odten = <0x2f>;
		dram_dq_drv_odten = <0x28>;
		phy_dq_drv_odtoff = <0x23>;
		phy_ca_drv_odtoff = <0x26>;
		phy_clk_drv_odtoff = <0x2f>;
		dram_dq_drv_odtoff = <0x28>;
		dram_odt = <0x3c>;
		phy_odt = <0x50>;
		phy_odt_puup_en = <0x0>;
		phy_odt_pudn_en = <0x0>;
		dram_dq_odt_en_freq = <0x320>;
		phy_odt_en_freq = <0x320>;
		phy_dq_sr_odten = <0x0>;
		phy_ca_sr_odten = <0x1>;
		phy_clk_sr_odten = <0x1>;
		phy_dq_sr_odtoff = <0x0>;
		phy_ca_sr_odtoff = <0x1>;
		phy_clk_sr_odtoff = <0x1>;
		ssmod_downspread = <0x0>;
		ssmod_div = <0x0>;
		ssmod_spread = <0x0>;
		mode_2t = <0x0>;
		speed_bin = <0x0>;
		dram_ext_temp = <0x0>;
		byte_map = <0xe4>;
		dq_map_cs0_dq_l = <0x0>;
		dq_map_cs0_dq_h = <0x0>;
		dq_map_cs1_dq_l = <0x0>;
		dq_map_cs1_dq_h = <0x0>;
		lp4_ca_odt = <0x78>;
		lp4_drv_pu_cal_odten = <0x0>;
		lp4_drv_pu_cal_odtoff = <0x0>;
		phy_lp4_drv_pulldown_en_odten = <0x0>;
		phy_lp4_drv_pulldown_en_odtoff = <0x0>;
		lp4_ca_odt_en_freq = <0x320>;
		phy_lp4_cs_drv_odten = <0x0>;
		phy_lp4_cs_drv_odtoff = <0x0>;
		lp4_odte_ck_en = <0x1>;
		lp4_odte_cs_en = <0x1>;
		lp4_odtd_ca_en = <0x0>;
		phy_lp4_dq_vref_odten = <0xc8>;
		lp4_dq_vref_odten = <0x114>;
		lp4_ca_vref_odten = <0x17c>;
		phy_lp4_dq_vref_odtoff = <0x154>;
		lp4_dq_vref_odtoff = <0x1a4>;
		lp4_ca_vref_odtoff = <0x1a4>;
		phandle = <0xba>;
	};

	aliases {
		ethernet0 = "/ethernet@ff360000";
		i2c0 = "/i2c@ff180000";
		i2c1 = "/i2c@ff190000";
		i2c2 = "/i2c@ff1a0000";
		i2c3 = "/i2c@ff1b0000";
		mmc0 = "/dwmmc@ff370000";
		mmc1 = "/dwmmc@ff380000";
		mmc2 = "/dwmmc@ff390000";
		serial0 = "/serial@ff030000";
		serial1 = "/serial@ff158000";
		serial2 = "/serial@ff160000";
		serial3 = "/serial@ff168000";
		serial4 = "/serial@ff170000";
		serial5 = "/serial@ff178000";
		spi0 = "/spi@ff1d0000";
		spi1 = "/spi@ff1d8000";
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x0>;
			enable-method = "psci";
			clocks = <0x2 0x7>;
			#cooling-cells = <0x2>;
			dynamic-power-coefficient = <0x5a>;
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4 0x5>;
			cpu-supply = <0x6>;
			phandle = <0x9>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x1>;
			enable-method = "psci";
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4 0x5>;
			phandle = <0xa>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x2>;
			enable-method = "psci";
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4 0x5>;
			phandle = <0xb>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a35", "arm,armv8";
			reg = <0x0 0x3>;
			enable-method = "psci";
			operating-points-v2 = <0x3>;
			cpu-idle-states = <0x4 0x5>;
			phandle = <0xc>;
		};

		idle-states {
			entry-method = "psci";

			cpu-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x10000>;
				entry-latency-us = <0x78>;
				exit-latency-us = <0xfa>;
				min-residency-us = <0x384>;
				phandle = <0x4>;
			};

			cluster-sleep {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x1010000>;
				entry-latency-us = <0x190>;
				exit-latency-us = <0x1f4>;
				min-residency-us = <0x7d0>;
				phandle = <0x5>;
			};
		};
	};

	cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x0>;
		rockchip,low-temp-min-volt = <0xf4240>;
		rockchip,low-temp-adjust-volt = <0x0 0x5e8 0xc350>;
		clocks = <0x2 0x1>;
		rockchip,avs-scale = <0x4>;
		rockchip,max-volt = <0x149970>;
		rockchip,evb-irdrop = <0x61a8>;
		nvmem-cells = <0x7 0x8>;
		nvmem-cell-names = "cpu_leakage", "performance";
		rockchip,bin-scaling-sel = <0x0 0xd 0x1 0xf>;
		rockchip,pvtm-voltage-sel = <0x0 0xc350 0x0 0xc351 0xd2f0 0x1 0xd2f1 0xea60 0x2 0xea61 0x1869f 0x3>;
		rockchip,pvtm-freq = <0x639c0>;
		rockchip,pvtm-volt = <0xf4240>;
		rockchip,pvtm-ch = <0x0 0x0>;
		rockchip,pvtm-sample-time = <0x3e8>;
		rockchip,pvtm-number = <0xa>;
		rockchip,pvtm-error = <0x3e8>;
		rockchip,pvtm-ref-temp = <0x28>;
		rockchip,pvtm-temp-prop = <0xffffffc8 0xffffffc8>;
		rockchip,thermal-zone = "soc-thermal";
		rockchip,avs = <0x1>;
		phandle = <0x3>;

		opp-408000000 {
			opp-hz = <0x0 0x18519600>;
			opp-microvolt = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L0 = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0x149970>;
			clock-latency-ns = <0x9c40>;
			opp-suspend;
		};

		opp-600000000 {
			opp-hz = <0x0 0x23c34600>;
			opp-microvolt = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L0 = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L1 = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L2 = <0xe7ef0 0xe7ef0 0x149970>;
			opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0x149970>;
			clock-latency-ns = <0x9c40>;
		};

		opp-816000000 {
			opp-hz = <0x0 0x30a32c00>;
			opp-microvolt = <0x100590 0x100590 0x149970>;
			opp-microvolt-L0 = <0x100590 0x100590 0x149970>;
			opp-microvolt-L1 = <0xf4240 0xf4240 0x149970>;
			opp-microvolt-L2 = <0xf4240 0xf4240 0x149970>;
			opp-microvolt-L3 = <0xe7ef0 0xe7ef0 0x149970>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1008000000 {
			opp-hz = <0x0 0x3c14dc00>;
			opp-microvolt = <0x11edd8 0x11edd8 0x149970>;
			opp-microvolt-L0 = <0x11edd8 0x11edd8 0x149970>;
			opp-microvolt-L1 = <0x112a88 0x112a88 0x149970>;
			opp-microvolt-L2 = <0x112a88 0x112a88 0x149970>;
			opp-microvolt-L3 = <0x100590 0x100590 0x149970>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1200000000 {
			opp-hz = <0x0 0x47868c00>;
			opp-microvolt = <0x13d620 0x13d620 0x149970>;
			opp-microvolt-L0 = <0x13d620 0x13d620 0x149970>;
			opp-microvolt-L1 = <0x137478 0x137478 0x149970>;
			opp-microvolt-L2 = <0x1312d0 0x1312d0 0x149970>;
			opp-microvolt-L3 = <0x124f80 0x124f80 0x149970>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1248000000 {
			opp-hz = <0x0 0x4a62f800>;
			opp-microvolt = <0x149970 0x149970 0x149970>;
			opp-microvolt-L0 = <0x149970 0x149970 0x149970>;
			opp-microvolt-L1 = <0x13d620 0x13d620 0x149970>;
			opp-microvolt-L2 = <0x137478 0x137478 0x149970>;
			opp-microvolt-L3 = <0x12b128 0x12b128 0x149970>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1296000000 {
			opp-hz = <0x0 0x4d3f6400>;
			opp-microvolt = <0x149970 0x149970 0x149970>;
			opp-microvolt-L0 = <0x149970 0x149970 0x149970>;
			opp-microvolt-L1 = <0x149970 0x149970 0x149970>;
			opp-microvolt-L2 = <0x13d620 0x13d620 0x149970>;
			opp-microvolt-L3 = <0x1312d0 0x1312d0 0x149970>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1416000000 {
			opp-hz = <0x0 0x54667200>;
			opp-microvolt = <0x149970 0x149970 0x149970>;
			opp-microvolt-L0 = <0x149970 0x149970 0x149970>;
			opp-microvolt-L1 = <0x149970 0x149970 0x149970>;
			opp-microvolt-L2 = <0x13d620 0x13d620 0x149970>;
			opp-microvolt-L3 = <0x1312d0 0x1312d0 0x149970>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1512000000 {
			opp-hz = <0x0 0x5a1f4a00>;
			opp-microvolt = <0x149970 0x149970 0x149970>;
			opp-microvolt-L0 = <0x149970 0x149970 0x149970>;
			opp-microvolt-L1 = <0x149970 0x149970 0x149970>;
			opp-microvolt-L2 = <0x13d620 0x13d620 0x149970>;
			opp-microvolt-L3 = <0x1312d0 0x1312d0 0x149970>;
			clock-latency-ns = <0x9c40>;
		};
	};

	px30s-cpu0-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		nvmem-cells = <0x7>;
		nvmem-cell-names = "cpu_leakage";
		rockchip,pvtm-voltage-sel = <0x0 0x110da 0x0 0x110db 0x12048 0x1 0x12049 0x12fb6 0x2 0x12fb7 0x13f24 0x3 0x13f25 0x1869f 0x4>;
		rockchip,pvtm-freq = <0x639c0>;
		rockchip,pvtm-volt = <0xdbba0>;
		rockchip,pvtm-ch = <0x0 0x0>;
		rockchip,pvtm-sample-time = <0x3e8>;
		rockchip,pvtm-number = <0xa>;
		rockchip,pvtm-error = <0x3e8>;
		rockchip,pvtm-ref-temp = <0x0>;
		rockchip,pvtm-temp-prop = <0x0 0x0>;
		rockchip,thermal-zone = "soc-thermal";
		phandle = <0xcd>;

		opp-408000000 {
			opp-hz = <0x0 0x18519600>;
			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
			opp-suspend;
		};

		opp-600000000 {
			opp-hz = <0x0 0x23c34600>;
			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-816000000 {
			opp-hz = <0x0 0x30a32c00>;
			opp-microvolt = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1008000000 {
			opp-hz = <0x0 0x3c14dc00>;
			opp-microvolt = <0xe7ef0 0xe7ef0 0x118c30>;
			opp-microvolt-L0 = <0xe7ef0 0xe7ef0 0x118c30>;
			opp-microvolt-L1 = <0xe1d48 0xe1d48 0x118c30>;
			opp-microvolt-L2 = <0xdbba0 0xdbba0 0x118c30>;
			opp-microvolt-L3 = <0xd59f8 0xd59f8 0x118c30>;
			opp-microvolt-L4 = <0xcf850 0xcf850 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1200000000 {
			opp-hz = <0x0 0x47868c00>;
			opp-microvolt = <0x100590 0x100590 0x118c30>;
			opp-microvolt-L0 = <0x100590 0x100590 0x118c30>;
			opp-microvolt-L1 = <0xfa3e8 0xfa3e8 0x118c30>;
			opp-microvolt-L2 = <0xf4240 0xf4240 0x118c30>;
			opp-microvolt-L3 = <0xee098 0xee098 0x118c30>;
			opp-microvolt-L4 = <0xe7ef0 0xe7ef0 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1248000000 {
			opp-hz = <0x0 0x4a62f800>;
			opp-microvolt = <0x106738 0x106738 0x118c30>;
			opp-microvolt-L0 = <0x106738 0x106738 0x118c30>;
			opp-microvolt-L1 = <0x100590 0x100590 0x118c30>;
			opp-microvolt-L2 = <0xfa3e8 0xfa3e8 0x118c30>;
			opp-microvolt-L3 = <0xf4240 0xf4240 0x118c30>;
			opp-microvolt-L4 = <0xee098 0xee098 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1296000000 {
			opp-hz = <0x0 0x4d3f6400>;
			opp-microvolt = <0x10c8e0 0x10c8e0 0x118c30>;
			opp-microvolt-L0 = <0x10c8e0 0x10c8e0 0x118c30>;
			opp-microvolt-L1 = <0x106738 0x106738 0x118c30>;
			opp-microvolt-L2 = <0x100590 0x100590 0x118c30>;
			opp-microvolt-L3 = <0xfa3e8 0xfa3e8 0x118c30>;
			opp-microvolt-L4 = <0xf4240 0xf4240 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1416000000 {
			opp-hz = <0x0 0x54667200>;
			opp-microvolt = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L0 = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L1 = <0x112a88 0x112a88 0x118c30>;
			opp-microvolt-L2 = <0x10c8e0 0x10c8e0 0x118c30>;
			opp-microvolt-L3 = <0x106738 0x106738 0x118c30>;
			opp-microvolt-L4 = <0x100590 0x100590 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};

		opp-1512000000 {
			opp-hz = <0x0 0x5a1f4a00>;
			opp-microvolt = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L0 = <0x118c30 0x118c30 0x118c30>;
			opp-microvolt-L1 = <0x112a88 0x112a88 0x118c30>;
			opp-microvolt-L2 = <0x10c8e0 0x10c8e0 0x118c30>;
			opp-microvolt-L3 = <0x106738 0x106738 0x118c30>;
			opp-microvolt-L4 = <0x100590 0x100590 0x118c30>;
			clock-latency-ns = <0x9c40>;
		};
	};

	arm-pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <0x0 0x64 0x4 0x0 0x65 0x4 0x0 0x66 0x4 0x0 0x67 0x4>;
		interrupt-affinity = <0x9 0xa 0xb 0xc>;
	};

	bus-apll {
		compatible = "rockchip,px30-bus";
		rockchip,busfreq-policy = "clkfreq";
		clocks = <0x2 0x1>;
		clock-names = "bus";
		operating-points-v2 = <0xd>;
		status = "okay";
		bus-supply = <0xe>;
		phandle = <0xce>;
	};

	bus-apll-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
		phandle = <0xd>;

		opp-1512000000 {
			opp-hz = <0x0 0x5a1f4a00>;
			opp-microvolt = <0xf4240>;
		};

		opp-1008000000 {
			opp-hz = <0x0 0x3c14dc00>;
			opp-microvolt = <0xe7ef0>;
		};
	};

	cpuinfo {
		compatible = "rockchip,cpuinfo";
		nvmem-cells = <0xf>;
		nvmem-cell-names = "id";
	};

	display-subsystem {
		compatible = "rockchip,display-subsystem";
		ports = <0x10 0x11>;
		status = "okay";
		logo-memory-region = <0x12>;
		phandle = <0xcf>;

		route {

			route-lvds {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x13>;
				phandle = <0xd0>;
			};

			route-dsi {
				status = "okay";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x14>;
				phandle = <0xd1>;
			};

			route-rgb {
				status = "disabled";
				logo,uboot = "logo.bmp";
				logo,kernel = "logo_kernel.bmp";
				logo,mode = "center";
				charge_logo,mode = "center";
				connect = <0x15>;
				phandle = <0xd2>;
			};
		};
	};

	firmware {

		optee {
			compatible = "linaro,optee-tz";
			method = "smc";
			phandle = <0xd3>;
		};

		scmi {
			compatible = "arm,scmi-smc";
			shmem = <0x16>;
			arm,smc-id = <0x82000010>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phandle = <0xd4>;

			protocol@14 {
				reg = <0x14>;
				#clock-cells = <0x1>;
				phandle = <0xd5>;
			};
		};

		sdei {
			compatible = "arm,sdei-1.0";
			method = "smc";
			phandle = <0xd6>;
		};
	};

	external-gmac-clock {
		compatible = "fixed-clock";
		clock-frequency = <0x2faf080>;
		clock-output-names = "gmac_clkin";
		#clock-cells = <0x0>;
		phandle = <0x90>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	rockchip-suspend {
		compatible = "rockchip,pm-px30";
		status = "okay";
		rockchip,sleep-debug-en = <0x1>;
		rockchip,sleep-mode-config = <0x20702>;
		rockchip,wakeup-config = <0x85>;
		phandle = <0xd7>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <0x1 0xd 0xf04 0x1 0xe 0xf04 0x1 0xb 0xf04 0x1 0xa 0xf04>;
	};

	xin24m {
		compatible = "fixed-clock";
		#clock-cells = <0x0>;
		clock-frequency = <0x16e3600>;
		clock-output-names = "xin24m";
		phandle = <0xd8>;
	};

	xin32k {
		compatible = "fixed-clock";
		#clock-cells = <0x0>;
		clock-frequency = <0x8000>;
		clock-output-names = "xin32k";
		phandle = <0xd9>;
	};

	scmi-shmem@10f000 {
		compatible = "arm,scmi-shmem";
		reg = <0x0 0x10f000 0x0 0x100>;
		phandle = <0x16>;
	};

	power-management@ff000000 {
		compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
		reg = <0x0 0xff000000 0x0 0x1000>;
		phandle = <0xda>;

		power-controller {
			compatible = "rockchip,px30-power-controller";
			#power-domain-cells = <0x1>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phandle = <0x8a>;

			pd_usb@5 {
				reg = <0x5>;
				clocks = <0x2 0x103 0x2 0x102 0x2 0x3c>;
				pm_qos = <0x17 0x18>;
			};

			pd_sdcard@7 {
				reg = <0x7>;
				clocks = <0x2 0xf7 0x2 0x3b>;
				pm_qos = <0x19>;
			};

			pd_gmac@9 {
				reg = <0x9>;
				clocks = <0x2 0xb2 0x2 0x143 0x2 0x40 0x2 0x3f>;
				pm_qos = <0x1a>;
			};

			pd_mmc_nand@10 {
				reg = <0xa>;
				clocks = <0x2 0xfe 0x2 0x100 0x2 0xff 0x2 0x101 0x2 0x39 0x2 0x37 0x2 0x38 0x2 0x3a>;
				pm_qos = <0x1b 0x1c 0x1d 0x1e>;
			};

			pd_vpu@11 {
				reg = <0xb>;
				clocks = <0x2 0xaf 0x2 0xf4 0x2 0x4b>;
				pm_qos = <0x1f 0x20>;
			};

			pd_vo@12 {
				reg = <0xc>;
				clocks = <0x2 0xb7 0x2 0xb5 0x2 0xb6 0x2 0x96 0x2 0x97 0x2 0xfd 0x2 0xfb 0x2 0xfc 0x2 0x144 0x2 0x35 0x2 0x36>;
				pm_qos = <0x21 0x22 0x23 0x24>;
			};

			pd_vi@13 {
				reg = <0xd>;
				clocks = <0x2 0xb3 0x2 0xb4 0x2 0xf9 0x2 0xfa 0x2 0x33>;
				pm_qos = <0x25 0x26 0x27 0x28 0x29>;
			};

			pd_gpu@14 {
				reg = <0xe>;
				clocks = <0x2 0x49>;
				pm_qos = <0x2a>;
			};
		};
	};

	syscon@ff010000 {
		compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
		reg = <0x0 0xff010000 0x0 0x1000>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		phandle = <0xb2>;

		io-domains {
			compatible = "rockchip,px30-pmu-io-voltage-domain";
			status = "okay";
			pmuio1-supply = <0x2b>;
			pmuio2-supply = <0x2b>;
			phandle = <0xdb>;
		};

		reboot-mode {
			compatible = "syscon-reboot-mode";
			offset = <0x200>;
			mode-bootloader = <0x5242c301>;
			mode-charge = <0x5242c30b>;
			mode-fastboot = <0x5242c309>;
			mode-loader = <0x5242c301>;
			mode-normal = <0x5242c300>;
			mode-recovery = <0x5242c303>;
			mode-ums = <0x5242c30c>;
			phandle = <0xdc>;
		};

		pmu-pvtm {
			compatible = "rockchip,px30-pmu-pvtm";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "okay";
			phandle = <0xdd>;

			pvtm@1 {
				reg = <0x1>;
				clocks = <0x2c 0x7>;
				clock-names = "clk";
			};
		};
	};

	serial@ff030000 {
		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff030000 0x0 0x100>;
		interrupts = <0x0 0xf 0x4>;
		clocks = <0x2c 0x6 0x2c 0x15>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x2d 0x0 0x2d 0x1>;
		pinctrl-names = "default";
		pinctrl-0 = <0x2e>;
		status = "okay";
		phandle = <0xde>;
	};

	i2s@ff060000 {
		compatible = "rockchip,px30-i2s-tdm";
		reg = <0x0 0xff060000 0x0 0x1000>;
		interrupts = <0x0 0xc 0x4>;
		clocks = <0x2 0x10 0x2 0x12 0x2 0x106>;
		clock-names = "mclk_tx", "mclk_rx", "hclk";
		dmas = <0x2d 0x10 0x2d 0x11>;
		dma-names = "tx", "rx";
		resets = <0x2 0x84 0x2 0xbf>;
		reset-names = "tx-m", "rx-m";
		rockchip,cru = <0x2>;
		rockchip,grf = <0x2f>;
		pinctrl-names = "default";
		pinctrl-0 = <0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b>;
		status = "disabled";
		phandle = <0xdf>;
	};

	i2s@ff070000 {
		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff070000 0x0 0x1000>;
		interrupts = <0x0 0xd 0x4>;
		clocks = <0x2 0x14 0x2 0x107>;
		clock-names = "i2s_clk", "i2s_hclk";
		dmas = <0x2d 0x12 0x2d 0x13>;
		dma-names = "tx", "rx";
		resets = <0x2 0x86 0x2 0x85>;
		reset-names = "reset-m", "reset-h";
		pinctrl-names = "default";
		pinctrl-0 = <0x3c 0x3d 0x3e 0x3f>;
		status = "okay";
		#sound-dai-cells = <0x0>;
		phandle = <0xc9>;
	};

	i2s@ff080000 {
		compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
		reg = <0x0 0xff080000 0x0 0x1000>;
		interrupts = <0x0 0xe 0x4>;
		clocks = <0x2 0x16 0x2 0x108>;
		clock-names = "i2s_clk", "i2s_hclk";
		dmas = <0x2d 0x14 0x2d 0x15>;
		dma-names = "tx", "rx";
		resets = <0x2 0x88 0x2 0x87>;
		reset-names = "reset-m", "reset-h";
		pinctrl-names = "default";
		pinctrl-0 = <0x40 0x41 0x42 0x43>;
		status = "disabled";
		phandle = <0xe0>;
	};

	pdm@ff0a0000 {
		compatible = "rockchip,px30-pdm";
		reg = <0x0 0xff0a0000 0x0 0x1000>;
		clocks = <0x2 0xf 0x2 0x105>;
		clock-names = "pdm_clk", "pdm_hclk";
		dmas = <0x2d 0x18>;
		dma-names = "rx";
		resets = <0x2 0x82>;
		reset-names = "pdm-m";
		pinctrl-names = "default";
		pinctrl-0 = <0x44 0x45 0x46 0x47 0x48 0x49>;
		status = "disabled";
		phandle = <0xe1>;
	};

	crypto@ff0b0000 {
		compatible = "rockchip,px30-crypto";
		reg = <0x0 0xff0b0000 0x0 0x400 0x0 0xff0b0480 0x0 0x3b80>;
		interrupts = <0x0 0x52 0x4>;
		clocks = <0x2 0xac 0x2 0xf1 0x2 0x30 0x2 0x31>;
		clock-names = "aclk", "hclk", "sclk", "apb_pclk";
		resets = <0x2 0x74>;
		reset-names = "crypto-rst";
		status = "disabled";
		phandle = <0xe2>;
	};

	rng@ff0b0000 {
		compatible = "rockchip,cryptov2-rng";
		reg = <0x0 0xff0b0400 0x0 0x80>;
		clocks = <0x2 0x30 0x2 0x31 0x2 0xac 0x2 0xf1>;
		clock-names = "clk_crypto", "clk_crypto_apk", "aclk_crypto", "hclk_crypto";
		assigned-clocks = <0x2 0x30 0x2 0x31 0x2 0xac 0x2 0xf1>;
		assigned-clock-rates = <0x8f0d180 0x8f0d180 0xbebc200 0xbebc200>;
		resets = <0x2 0x74>;
		reset-names = "reset";
		status = "okay";
		phandle = <0xe3>;
	};

	interrupt-controller@ff131000 {
		compatible = "arm,gic-400";
		#interrupt-cells = <0x3>;
		#address-cells = <0x0>;
		interrupt-controller;
		reg = <0x0 0xff131000 0x0 0x1000 0x0 0xff132000 0x0 0x2000 0x0 0xff134000 0x0 0x2000 0x0 0xff136000 0x0 0x2000>;
		interrupts = <0x1 0x9 0xf04>;
		phandle = <0x1>;
	};

	syscon@ff140000 {
		compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
		reg = <0x0 0xff140000 0x0 0x1000>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		phandle = <0x2f>;

		io-domains {
			compatible = "rockchip,px30-io-voltage-domain";
			status = "okay";
			vccio1-supply = <0x4a>;
			vccio2-supply = <0x4b>;
			vccio3-supply = <0x4c>;
			vccio4-supply = <0x2b>;
			vccio5-supply = <0x4c>;
			phandle = <0xe4>;
		};

		lvds {
			compatible = "rockchip,px30-lvds";
			phys = <0x4d>;
			phy-names = "phy";
			status = "disabled";
			phandle = <0xe5>;

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					endpoint@0 {
						reg = <0x0>;
						remote-endpoint = <0x13>;
						phandle = <0xa4>;
					};

					endpoint@1 {
						reg = <0x1>;
						remote-endpoint = <0x4e>;
						phandle = <0xa8>;
					};
				};
			};
		};

		rgb {
			compatible = "rockchip,px30-rgb";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <0x4f>;
			pinctrl-1 = <0x50>;
			status = "disabled";
			phandle = <0xe6>;

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;
					#address-cells = <0x1>;
					#size-cells = <0x0>;

					endpoint@0 {
						reg = <0x0>;
						remote-endpoint = <0x15>;
						phandle = <0xa6>;
					};

					endpoint@1 {
						reg = <0x1>;
						remote-endpoint = <0x51>;
						phandle = <0xaa>;
					};
				};
			};
		};
	};

	syscon@ff148000 {
		compatible = "syscon", "simple-mfd";
		reg = <0x0 0xff148000 0x0 0x1000>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		phandle = <0xe7>;

		pvtm {
			compatible = "rockchip,px30-pvtm";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			status = "okay";
			phandle = <0xe8>;

			pvtm@0 {
				reg = <0x0>;
				clocks = <0x2 0x4a>;
				clock-names = "clk";
			};
		};
	};

	serial@ff158000 {
		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff158000 0x0 0x100>;
		interrupts = <0x0 0x10 0x4>;
		clocks = <0x2 0x18 0x2 0x149>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x2d 0x2 0x2d 0x3>;
		pinctrl-names = "default";
		pinctrl-0 = <0x52>;
		status = "okay";
		phandle = <0xe9>;
	};

	serial@ff160000 {
		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff160000 0x0 0x100>;
		interrupts = <0x0 0x11 0x4>;
		clocks = <0x2 0x19 0x2 0x14a>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x2d 0x4 0x2d 0x5>;
		pinctrl-names = "default";
		pinctrl-0 = <0x53>;
		status = "disabled";
		phandle = <0xea>;
	};

	serial@ff168000 {
		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff168000 0x0 0x100>;
		interrupts = <0x0 0x12 0x4>;
		clocks = <0x2 0x1a 0x2 0x14b>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x2d 0x6 0x2d 0x7>;
		pinctrl-names = "default";
		pinctrl-0 = <0x54 0x55 0x56>;
		status = "disabled";
		phandle = <0xeb>;
	};

	serial@ff170000 {
		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff170000 0x0 0x100>;
		interrupts = <0x0 0x13 0x4>;
		clocks = <0x2 0x1b 0x2 0x14c>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x2d 0x8 0x2d 0x9>;
		pinctrl-names = "default";
		pinctrl-0 = <0x57>;
		status = "okay";
		phandle = <0xec>;
	};

	serial@ff178000 {
		compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
		reg = <0x0 0xff178000 0x0 0x100>;
		interrupts = <0x0 0x14 0x4>;
		clocks = <0x2 0x1c 0x2 0x14d>;
		clock-names = "baudclk", "apb_pclk";
		reg-shift = <0x2>;
		reg-io-width = <0x4>;
		dmas = <0x2d 0xa 0x2d 0xb>;
		pinctrl-names = "default";
		pinctrl-0 = <0x58 0x59 0x5a>;
		status = "disabled";
		phandle = <0xed>;
	};

	i2c@ff180000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff180000 0x0 0x1000>;
		clocks = <0x2 0x1d 0x2 0x14e>;
		clock-names = "i2c", "pclk";
		interrupts = <0x0 0x7 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <0x5b>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "okay";
		phandle = <0xee>;

		pmic@20 {
			compatible = "rockchip,rk809";
			reg = <0x20>;
			interrupt-parent = <0x5c>;
			interrupts = <0x7 0x8>;
			pinctrl-names = "default", "pmic-sleep", "pmic-power-off", "pmic-reset";
			pinctrl-0 = <0x5d>;
			pinctrl-1 = <0x5e 0x5f>;
			pinctrl-2 = <0x60 0x61>;
			pinctrl-3 = <0x62 0x63>;
			rockchip,system-power-controller;
			wakeup-source;
			#clock-cells = <0x1>;
			clock-output-names = "rk808-clkout1", "rk808-clkout2";
			pmic-reset-func = <0x1>;
			vcc1-supply = <0x64>;
			vcc2-supply = <0x64>;
			vcc3-supply = <0x64>;
			vcc4-supply = <0x64>;
			vcc5-supply = <0x65>;
			vcc6-supply = <0x65>;
			vcc7-supply = <0x65>;
			vcc8-supply = <0x65>;
			vcc9-supply = <0x64>;
			phandle = <0xef>;

			pwrkey {
				status = "okay";
			};

			pinctrl_rk8xx {
				gpio-controller;
				#gpio-cells = <0x2>;
				phandle = <0xf0>;

				rk817_slppin_null {
					pins = "gpio_slp";
					function = "pin_fun0";
					phandle = <0xf1>;
				};

				rk817_slppin_slp {
					pins = "gpio_slp";
					function = "pin_fun1";
					phandle = <0x5f>;
				};

				rk817_slppin_pwrdn {
					pins = "gpio_slp";
					function = "pin_fun2";
					phandle = <0x61>;
				};

				rk817_slppin_rst {
					pins = "gpio_slp";
					function = "pin_fun3";
					phandle = <0x63>;
				};
			};

			regulators {

				DCDC_REG1 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xcf850>;
					regulator-max-microvolt = <0x149970>;
					regulator-ramp-delay = <0x1771>;
					regulator-initial-mode = <0x2>;
					regulator-name = "vdd_logic";
					phandle = <0xe>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0xe7ef0>;
					};
				};

				DCDC_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xcf850>;
					regulator-max-microvolt = <0x149970>;
					regulator-ramp-delay = <0x1771>;
					regulator-initial-mode = <0x2>;
					regulator-name = "vdd_arm";
					phandle = <0x6>;

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0xe7ef0>;
					};
				};

				DCDC_REG3 {
					regulator-always-on;
					regulator-boot-on;
					regulator-initial-mode = <0x2>;
					regulator-name = "vcc_ddr";
					phandle = <0xf2>;

					regulator-state-mem {
						regulator-on-in-suspend;
					};
				};

				DCDC_REG4 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x2dc6c0>;
					regulator-max-microvolt = <0x2dc6c0>;
					regulator-initial-mode = <0x2>;
					regulator-name = "vcc_3v0";
					phandle = <0x4c>;

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0x2dc6c0>;
					};
				};

				LDO_REG1 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xf4240>;
					regulator-max-microvolt = <0xf4240>;
					regulator-initial-mode = <0x1>;
					regulator-name = "vcc_1v0";
					phandle = <0xf3>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0xf4240>;
					};
				};

				LDO_REG2 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcc1v8_soc";
					phandle = <0x4a>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				LDO_REG3 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0xf4240>;
					regulator-max-microvolt = <0xf4240>;
					regulator-name = "vcc1v0_soc";
					phandle = <0xf4>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0xf4240>;
					};
				};

				LDO_REG4 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x2dc6c0>;
					regulator-max-microvolt = <0x2dc6c0>;
					regulator-name = "vcc3v0_pmu";
					phandle = <0x2b>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x2dc6c0>;
					};
				};

				LDO_REG5 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vccio_sd";
					phandle = <0x4b>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x325aa0>;
					};
				};

				LDO_REG6 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vcc_sd";
					phandle = <0x98>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x325aa0>;
					};
				};

				LDO_REG7 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x2625a0>;
					regulator-max-microvolt = <0x2625a0>;
					regulator-name = "vcc2v8_dvp";
					phandle = <0xf5>;

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0x0>;
					};
				};

				LDO_REG8 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x1b7740>;
					regulator-max-microvolt = <0x1b7740>;
					regulator-name = "vcc1v8_dvp";
					phandle = <0xf6>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x1b7740>;
					};
				};

				LDO_REG9 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x124f80>;
					regulator-max-microvolt = <0x124f80>;
					regulator-name = "vdd1v5_dvp";
					phandle = <0xf7>;

					regulator-state-mem {
						regulator-off-in-suspend;
						regulator-suspend-microvolt = <0x124f80>;
					};
				};

				DCDC_REG5 {
					regulator-always-on;
					regulator-boot-on;
					regulator-min-microvolt = <0x325aa0>;
					regulator-max-microvolt = <0x325aa0>;
					regulator-name = "vcc3v3_sys";
					phandle = <0x65>;

					regulator-state-mem {
						regulator-on-in-suspend;
						regulator-suspend-microvolt = <0x325aa0>;
					};
				};

				SWITCH_REG2 {
					regulator-boot-on;
					regulator-name = "vcc3v3_lcd";
					phandle = <0x9f>;
				};
			};

			codec {
				#sound-dai-cells = <0x0>;
				compatible = "rockchip,rk809-codec", "rockchip,rk817-codec";
				clocks = <0x2 0x15>;
				clock-names = "mclk";
				pinctrl-names = "default";
				pinctrl-0 = <0x66>;
				hp-ctl-gpio = <0x67 0xc 0x0>;
				hp-volume = <0x14>;
				spk-volume = <0x3>;
				status = "okay";
				phandle = <0xca>;
			};
		};
	};

	i2c@ff190000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff190000 0x0 0x1000>;
		clocks = <0x2 0x1e 0x2 0x14f>;
		clock-names = "i2c", "pclk";
		interrupts = <0x0 0x8 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <0x68>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "okay";
		phandle = <0xf8>;

		goodix_ts@14 {
			compatible = "goodix,gt9xx";
			reg = <0x14>;
			touch-gpio = <0x5c 0x5 0x8>;
			reset-gpio = <0x5c 0xc 0x0>;
			max-x = <0x320>;
			max-y = <0x500>;
			tp-size = <0x64>;
		};

		rtc@51 {
			compatible = "rtc,hym8563";
			reg = <0x51>;
			phandle = <0xf9>;
		};
	};

	i2c@ff1a0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff1a0000 0x0 0x1000>;
		clocks = <0x2 0x1f 0x2 0x150>;
		clock-names = "i2c", "pclk";
		interrupts = <0x0 0x9 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <0x69>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "disabled";
		phandle = <0xfa>;
	};

	i2c@ff1b0000 {
		compatible = "rockchip,rk3399-i2c";
		reg = <0x0 0xff1b0000 0x0 0x1000>;
		clocks = <0x2 0x20 0x2 0x151>;
		clock-names = "i2c", "pclk";
		interrupts = <0x0 0xa 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <0x6a>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "disabled";
		phandle = <0xfb>;
	};

	spi@ff1d0000 {
		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xff1d0000 0x0 0x1000>;
		interrupts = <0x0 0x1a 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		clocks = <0x2 0x24 0x2 0x155>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <0x2d 0xc 0x2d 0xd>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <0x6b 0x6c 0x6d 0x6e>;
		pinctrl-1 = <0x6f 0x6c 0x70 0x71>;
		status = "disabled";
		phandle = <0xfc>;
	};

	spi@ff1d8000 {
		compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
		reg = <0x0 0xff1d8000 0x0 0x1000>;
		interrupts = <0x0 0x1b 0x4>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		clocks = <0x2 0x25 0x2 0x156>;
		clock-names = "spiclk", "apb_pclk";
		dmas = <0x2d 0xe 0x2d 0xf>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "high_speed";
		pinctrl-0 = <0x72 0x73 0x74 0x75 0x76>;
		pinctrl-1 = <0x77 0x73 0x74 0x78 0x79>;
		status = "disabled";
		phandle = <0xfd>;
	};

	watchdog@ff1e0000 {
		compatible = "snps,dw-wdt";
		reg = <0x0 0xff1e0000 0x0 0x100>;
		clocks = <0x2 0x15b>;
		interrupts = <0x0 0x25 0x4>;
		resets = <0x2 0xb5>;
		reset-names = "reset";
		status = "disabled";
		phandle = <0xfe>;
	};

	pwm@ff200000 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff200000 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x7a>;
		clocks = <0x2 0x22 0x2 0x153>;
		clock-names = "pwm", "pclk";
		status = "okay";
		phandle = <0xc8>;
	};

	pwm@ff200010 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff200010 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x7b>;
		clocks = <0x2 0x22 0x2 0x153>;
		clock-names = "pwm", "pclk";
		status = "okay";
		phandle = <0xff>;
	};

	pwm@ff200020 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff200020 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x7c>;
		clocks = <0x2 0x22 0x2 0x153>;
		clock-names = "pwm", "pclk";
		status = "disabled";
		phandle = <0x100>;
	};

	pwm@ff200030 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff200030 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x7d>;
		clocks = <0x2 0x22 0x2 0x153>;
		clock-names = "pwm", "pclk";
		status = "disabled";
		phandle = <0x101>;
	};

	pwm@ff208000 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff208000 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x7e>;
		clocks = <0x2 0x23 0x2 0x154>;
		clock-names = "pwm", "pclk";
		status = "disabled";
		phandle = <0x102>;
	};

	pwm@ff208010 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff208010 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x7f>;
		clocks = <0x2 0x23 0x2 0x154>;
		clock-names = "pwm", "pclk";
		status = "disabled";
		phandle = <0x103>;
	};

	pwm@ff208020 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff208020 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x80>;
		clocks = <0x2 0x23 0x2 0x154>;
		clock-names = "pwm", "pclk";
		status = "disabled";
		phandle = <0x104>;
	};

	pwm@ff208030 {
		compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
		reg = <0x0 0xff208030 0x0 0x10>;
		#pwm-cells = <0x3>;
		pinctrl-names = "active";
		pinctrl-0 = <0x81>;
		clocks = <0x2 0x23 0x2 0x154>;
		clock-names = "pwm", "pclk";
		status = "disabled";
		phandle = <0x105>;
	};

	rktimer@ff210000 {
		compatible = "rockchip,rk3288-timer";
		reg = <0x0 0xff210000 0x0 0x1000>;
		interrupts = <0x0 0x1e 0x4>;
		clocks = <0x2 0x159 0x2 0x26>;
		clock-names = "pclk", "timer";
		phandle = <0x106>;
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		dmac@ff240000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0x0 0xff240000 0x0 0x4000>;
			interrupts = <0x0 0x1 0x4 0x0 0x2 0x4>;
			clocks = <0x2 0xbb>;
			clock-names = "apb_pclk";
			#dma-cells = <0x1>;
			arm,pl330-periph-burst;
			phandle = <0x2d>;
		};
	};

	thermal-zones {
		phandle = <0x107>;

		soc-thermal {
			polling-delay-passive = <0x14>;
			polling-delay = <0x3e8>;
			sustainable-power = <0x2ee>;
			thermal-sensors = <0x82 0x0>;
			phandle = <0x108>;

			trips {

				trip-point-0 {
					temperature = <0x11170>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x109>;
				};

				trip-point-1 {
					temperature = <0x14c08>;
					hysteresis = <0x7d0>;
					type = "passive";
					phandle = <0x83>;
				};

				soc-crit {
					temperature = <0x1c138>;
					hysteresis = <0x7d0>;
					type = "critical";
					phandle = <0x10a>;
				};
			};

			cooling-maps {

				map0 {
					trip = <0x83>;
					cooling-device = <0x9 0xffffffff 0xffffffff>;
					contribution = <0x1000>;
				};

				map1 {
					trip = <0x83>;
					cooling-device = <0x84 0xffffffff 0xffffffff>;
					contribution = <0x1000>;
				};
			};
		};

		gpu-thermal {
			polling-delay-passive = <0x64>;
			polling-delay = <0x3e8>;
			thermal-sensors = <0x82 0x1>;
			phandle = <0x10b>;
		};
	};

	tsadc@ff280000 {
		compatible = "rockchip,px30-tsadc";
		reg = <0x0 0xff280000 0x0 0x100>;
		interrupts = <0x0 0x24 0x4>;
		rockchip,grf = <0x2f>;
		clocks = <0x2 0x2c 0x2 0x158>;
		clock-names = "tsadc", "apb_pclk";
		assigned-clocks = <0x2 0x2c>;
		assigned-clock-rates = <0xc350>;
		resets = <0x2 0xa8>;
		reset-names = "tsadc-apb";
		#thermal-sensor-cells = <0x1>;
		rockchip,hw-tshut-temp = <0x1d4c0>;
		status = "okay";
		pinctrl-names = "gpio", "otpout";
		pinctrl-0 = <0x85>;
		pinctrl-1 = <0x86>;
		phandle = <0x82>;
	};

	saradc@ff288000 {
		compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
		reg = <0x0 0xff288000 0x0 0x100>;
		interrupts = <0x0 0x54 0x4>;
		#io-channel-cells = <0x1>;
		clocks = <0x2 0x2d 0x2 0x157>;
		clock-names = "saradc", "apb_pclk";
		resets = <0x2 0xa5>;
		reset-names = "saradc-apb";
		status = "okay";
		vref-supply = <0x4a>;
		phandle = <0xc7>;
	};

	otp@ff290000 {
		compatible = "rockchip,px30-otp";
		reg = <0x0 0xff290000 0x0 0x4000>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		clocks = <0x2 0x2f 0x2 0x15a 0x2 0x161>;
		clock-names = "otp", "apb_pclk", "phy";
		resets = <0x2 0xb4>;
		reset-names = "otp_phy";
		phandle = <0x10c>;

		id@7 {
			reg = <0x7 0x10>;
			phandle = <0xf>;
		};

		cpu-leakage@17 {
			reg = <0x17 0x1>;
			phandle = <0x7>;
		};

		performance@1e {
			reg = <0x1e 0x1>;
			bits = <0x4 0x3>;
			phandle = <0x8>;
		};
	};

	clock-controller@ff2b0000 {
		compatible = "rockchip,px30-cru";
		reg = <0x0 0xff2b0000 0x0 0x1000>;
		rockchip,grf = <0x2f>;
		rockchip,boost = <0x87>;
		#clock-cells = <0x1>;
		#reset-cells = <0x1>;
		phandle = <0x2>;
	};

	cpu-boost@ff2b8000 {
		compatible = "syscon";
		reg = <0x0 0xff2b8000 0x0 0x1000>;
		rockchip,boost-low-con0 = <0x1032>;
		rockchip,boost-low-con1 = <0x1441>;
		rockchip,boost-high-con0 = <0x1036>;
		rockchip,boost-high-con1 = <0x1441>;
		rockchip,boost-backup-pll = <0x1>;
		rockchip,boost-backup-pll-usage = <0x0>;
		rockchip,boost-switch-threshold = <0x249f00>;
		rockchip,boost-statis-threshold = <0x100>;
		rockchip,boost-statis-enable = <0x0>;
		rockchip,boost-enable = <0x0>;
		phandle = <0x87>;
	};

	pmu-clock-controller@ff2bc000 {
		compatible = "rockchip,px30-pmucru";
		reg = <0x0 0xff2bc000 0x0 0x1000>;
		rockchip,grf = <0x2f>;
		#clock-cells = <0x1>;
		#reset-cells = <0x1>;
		assigned-clocks = <0x2c 0x1 0x2c 0x8 0x2c 0x5 0x2 0x7 0x2 0xab 0x2 0xb0 0x2 0xf0 0x2 0xf5 0x2 0x140 0x2 0x49>;
		assigned-clock-rates = <0x47868c00 0x5f5e100 0x18cba80 0x23c34600 0xbebc200 0xbebc200 0x8f0d180 0x8f0d180 0x5f5e100 0xbebc200>;
		phandle = <0x2c>;
	};

	syscon@ff2c0000 {
		compatible = "rockchip,px30-usb2phy-grf", "syscon", "simple-mfd";
		reg = <0x0 0xff2c0000 0x0 0x10000>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		phandle = <0x10d>;

		usb2-phy@100 {
			compatible = "rockchip,px30-usb2phy", "rockchip,rk3328-usb2phy";
			reg = <0x100 0x10>;
			clocks = <0x2c 0xa>;
			clock-names = "phyclk";
			#clock-cells = <0x0>;
			assigned-clocks = <0x2 0xe 0x2 0x55>;
			assigned-clock-parents = <0x88 0x2 0xe>;
			clock-output-names = "usb480m_phy";
			status = "okay";
			phandle = <0x88>;

			host-port {
				#phy-cells = <0x0>;
				interrupts = <0x0 0x44 0x4>;
				interrupt-names = "linestate";
				status = "okay";
				phy-supply = <0x89>;
				phandle = <0x8c>;
			};

			otg-port {
				#phy-cells = <0x0>;
				interrupts = <0x0 0x42 0x4 0x0 0x41 0x4 0x0 0x40 0x4>;
				interrupt-names = "otg-bvalid", "otg-id", "linestate";
				status = "okay";
				phandle = <0x8b>;
			};
		};
	};

	video-phy@ff2e0000 {
		compatible = "rockchip,px30-video-phy";
		reg = <0x0 0xff2e0000 0x0 0x10000 0x0 0xff450000 0x0 0x10000>;
		clocks = <0x2c 0xb 0x2 0x145 0x2 0x144>;
		clock-names = "ref", "pclk_phy", "pclk_host";
		#clock-cells = <0x0>;
		resets = <0x2 0x3e>;
		reset-names = "rst";
		power-domains = <0x8a 0xc>;
		#phy-cells = <0x0>;
		status = "okay";
		phandle = <0x4d>;
	};

	mipi-dphy-rx0@ff2f0000 {
		compatible = "rockchip,rk3326-mipi-dphy";
		reg = <0x0 0xff2f0000 0x0 0x4000>;
		clocks = <0x2 0x146>;
		clock-names = "dphy-ref";
		power-domains = <0x8a 0xd>;
		rockchip,grf = <0x2f>;
		status = "disabled";
		phandle = <0x10e>;
	};

	usb@ff300000 {
		compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", "snps,dwc2";
		reg = <0x0 0xff300000 0x0 0x40000>;
		interrupts = <0x0 0x3e 0x4>;
		clocks = <0x2 0x102>;
		clock-names = "otg";
		power-domains = <0x8a 0x5>;
		dr_mode = "otg";
		g-np-tx-fifo-size = <0x10>;
		g-rx-fifo-size = <0x118>;
		g-tx-fifo-size = <0x100 0x80 0x80 0x40 0x20 0x10>;
		g-use-dma;
		phys = <0x8b>;
		phy-names = "usb2-phy";
		status = "okay";
		phandle = <0x10f>;
	};

	usb@ff340000 {
		compatible = "generic-ehci";
		reg = <0x0 0xff340000 0x0 0x10000>;
		interrupts = <0x0 0x3c 0x4>;
		clocks = <0x2 0x103 0x88>;
		clock-names = "usbhost", "utmi";
		power-domains = <0x8a 0x5>;
		phys = <0x8c>;
		phy-names = "usb";
		status = "okay";
		phandle = <0x110>;
	};

	usb@ff350000 {
		compatible = "generic-ohci";
		reg = <0x0 0xff350000 0x0 0x10000>;
		interrupts = <0x0 0x3d 0x4>;
		clocks = <0x2 0x103 0x88>;
		clock-names = "usbhost", "utmi";
		power-domains = <0x8a 0x5>;
		phys = <0x8c>;
		phy-names = "usb";
		status = "okay";
		phandle = <0x111>;
	};

	ethernet@ff360000 {
		compatible = "rockchip,px30-gmac";
		reg = <0x0 0xff360000 0x0 0x10000>;
		rockchip,grf = <0x2f>;
		interrupts = <0x0 0x2b 0x4>;
		interrupt-names = "macirq";
		clocks = <0x2 0x3e 0x2 0x3f 0x2 0x3f 0x2 0x40 0x2 0x41 0x2 0xb2 0x2 0x143 0x2 0x4c>;
		clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", "pclk_mac", "clk_mac_speed";
		phy-mode = "rmii";
		pinctrl-names = "default";
		pinctrl-0 = <0x8d 0x8e>;
		resets = <0x2 0x5e>;
		reset-names = "stmmaceth";
		power-domains = <0x8a 0x9>;
		status = "okay";
		phy-supply = <0x8f>;
		assigned-clocks = <0x2 0x3e>;
		assigned-clock-parents = <0x90>;
		clock_in_out = "input";
		snps,reset-gpio = <0x67 0xd 0x1>;
		snps,reset-active-low;
		snps,reset-delays-us = <0x0 0xc350 0xc350>;
		tx_delay = <0x0>;
		rx_delay = <0x0>;
		phandle = <0x112>;
	};

	dwmmc@ff370000 {
		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xff370000 0x0 0x4000>;
		max-frequency = <0x8f0d180>;
		clocks = <0x2 0xf7 0x2 0x3b 0x2 0x43 0x2 0x44>;
		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
		assigned-clocks = <0x2 0x3b>;
		assigned-clock-parents = <0x2 0x57>;
		power-domains = <0x8a 0x7>;
		fifo-depth = <0x100>;
		interrupts = <0x0 0x36 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <0x91 0x92 0x93 0x94>;
		status = "disabled";
		phandle = <0x113>;
	};

	dwmmc@ff380000 {
		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xff380000 0x0 0x4000>;
		max-frequency = <0x8f0d180>;
		clocks = <0x2 0xff 0x2 0x38 0x2 0x45 0x2 0x46>;
		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
		assigned-clocks = <0x2 0x38>;
		assigned-clock-parents = <0x2 0x51>;
		power-domains = <0x8a 0xa>;
		fifo-depth = <0x100>;
		interrupts = <0x0 0x37 0x4>;
		pinctrl-names = "default";
		pinctrl-0 = <0x95 0x96 0x97>;
		status = "okay";
		bus-width = <0x4>;
		cap-mmc-highspeed;
		cap-sd-highspeed;
		supports-sd;
		card-detect-delay = <0x320>;
		ignore-pm-notify;
		cd-gpios = <0x5c 0x3 0x1>;
		sd-uhs-sdr12;
		sd-uhs-sdr25;
		sd-uhs-sdr50;
		sd-uhs-sdr104;
		vqmmc-supply = <0x4b>;
		vmmc-supply = <0x98>;
		phandle = <0x114>;
	};

	dwmmc@ff390000 {
		compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
		reg = <0x0 0xff390000 0x0 0x4000>;
		max-frequency = <0x8f0d180>;
		clocks = <0x2 0x100 0x2 0x39 0x2 0x47 0x2 0x48>;
		clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
		assigned-clocks = <0x2 0x39>;
		assigned-clock-parents = <0x2 0x53>;
		power-domains = <0x8a 0xa>;
		fifo-depth = <0x100>;
		interrupts = <0x0 0x35 0x4>;
		status = "okay";
		bus-width = <0x8>;
		cap-mmc-highspeed;
		mmc-hs200-1_8v;
		supports-emmc;
		disable-wp;
		non-removable;
		num-slots = <0x1>;
		phandle = <0x115>;
	};

	nandc@ff3b0000 {
		compatible = "rockchip,rk-nandc";
		reg = <0x0 0xff3b0000 0x0 0x4000>;
		interrupts = <0x0 0x39 0x4>;
		nandc_id = <0x0>;
		clocks = <0x2 0x37 0x2 0xfe>;
		clock-names = "clk_nandc", "hclk_nandc";
		assigned-clocks = <0x2 0x37>;
		assigned-clock-parents = <0x2 0x4f>;
		power-domains = <0x8a 0xa>;
		status = "okay";
		phandle = <0x116>;
	};

	gpu@ff400000 {
		compatible = "arm,mali-bifrost";
		reg = <0x0 0xff400000 0x0 0x4000>;
		interrupts = <0x0 0x2d 0x4 0x0 0x2e 0x4 0x0 0x2f 0x4>;
		interrupt-names = "GPU", "MMU", "JOB";
		upthreshold = <0x28>;
		downdifferential = <0xa>;
		clocks = <0x2 0x49>;
		clock-names = "clk_mali";
		power-domains = <0x8a 0xe>;
		#cooling-cells = <0x2>;
		operating-points-v2 = <0x99>;
		status = "okay";
		mali-supply = <0xe>;
		phandle = <0x84>;

		power_model {
			compatible = "arm,mali-simple-power-model";
			static-coefficient = <0x64578>;
			dynamic-coefficient = <0x2dd>;
			ts = <0x7d00 0x125c 0xffffffb0 0x2>;
			thermal-zone = "gpu-thermal";
		};
	};

	gpu-opp-table {
		compatible = "operating-points-v2";
		rockchip,thermal-zone = "soc-thermal";
		rockchip,temp-hysteresis = <0x1388>;
		rockchip,low-temp = <0x0>;
		rockchip,low-temp-min-volt = <0xf4240>;
		rockchip,low-temp-adjust-volt = <0x0 0x1e0 0xc350>;
		rockchip,max-volt = <0x11edd8>;
		rockchip,evb-irdrop = <0x61a8>;
		rockchip,pvtm-voltage-sel = <0x0 0xc350 0x0 0xc351 0xd2f0 0x1 0xd2f1 0xea60 0x2 0xea61 0x1869f 0x3>;
		rockchip,pvtm-ch = <0x0 0x0>;
		phandle = <0x99>;

		opp-200000000 {
			opp-hz = <0x0 0xbebc200>;
			opp-microvolt = <0xe7ef0>;
			opp-microvolt-L0 = <0xe7ef0>;
			opp-microvolt-L1 = <0xe7ef0>;
			opp-microvolt-L2 = <0xe7ef0>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-300000000 {
			opp-hz = <0x0 0x11e1a300>;
			opp-microvolt = <0xee098>;
			opp-microvolt-L0 = <0xee098>;
			opp-microvolt-L1 = <0xe7ef0>;
			opp-microvolt-L2 = <0xe7ef0>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-400000000 {
			opp-hz = <0x0 0x17d78400>;
			opp-microvolt = <0x100590>;
			opp-microvolt-L0 = <0x100590>;
			opp-microvolt-L1 = <0xfa3e8>;
			opp-microvolt-L2 = <0xee098>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-480000000 {
			opp-hz = <0x0 0x1c9c3800>;
			opp-microvolt = <0x112a88>;
			opp-microvolt-L0 = <0x112a88>;
			opp-microvolt-L1 = <0x10c8e0>;
			opp-microvolt-L2 = <0x100590>;
			opp-microvolt-L3 = <0xf4240>;
		};
	};

	px30s-gpu-opp-table {
		compatible = "operating-points-v2";
		rockchip,pvtm-voltage-sel = <0x0 0x110da 0x0 0x110db 0x12048 0x1 0x12049 0x12fb6 0x2 0x12fb7 0x13f24 0x3 0x13f25 0x1869f 0x4>;
		rockchip,pvtm-ch = <0x0 0x0>;
		phandle = <0x117>;

		opp-200000000 {
			opp-hz = <0x0 0xbebc200>;
			opp-microvolt = <0xe7ef0>;
		};

		opp-300000000 {
			opp-hz = <0x0 0x11e1a300>;
			opp-microvolt = <0xe7ef0>;
		};

		opp-400000000 {
			opp-hz = <0x0 0x17d78400>;
			opp-microvolt = <0xe7ef0>;
		};

		opp-520000000 {
			opp-hz = <0x0 0x1efe9200>;
			opp-microvolt = <0xf4240>;
			opp-microvolt-L0 = <0xf4240>;
			opp-microvolt-L1 = <0xee098>;
			opp-microvolt-L2 = <0xe7ef0>;
			opp-microvolt-L3 = <0xe7ef0>;
			opp-microvolt-L4 = <0xe7ef0>;
		};
	};

	mpp-srv {
		compatible = "rockchip,mpp-service";
		rockchip,taskqueue-count = <0x1>;
		rockchip,resetgroup-count = <0x1>;
		rockchip,grf = <0x2f>;
		rockchip,grf-offset = <0x410>;
		rockchip,grf-values = <0x80008000 0x80000000 0x80000000>;
		rockchip,grf-names = "grf_rkvdec", "grf_vdpu2", "grf_vepu2";
		status = "okay";
		phandle = <0x9b>;
	};

	vdpu@ff442400 {
		compatible = "rockchip,vpu-decoder-px30";
		reg = <0x0 0xff442400 0x0 0x400>;
		interrupts = <0x0 0x4f 0x4>;
		interrupt-names = "irq_dec";
		clocks = <0x2 0xaf 0x2 0xf4>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		resets = <0x2 0x24 0x2 0x26>;
		reset-names = "shared_video_a", "shared_video_h";
		iommus = <0x9a>;
		power-domains = <0x8a 0xb>;
		rockchip,srv = <0x9b>;
		rockchip,taskqueue-node = <0x0>;
		rockchip,resetgroup-node = <0x0>;
		status = "okay";
		phandle = <0x118>;
	};

	iommu@ff442800 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff442800 0x0 0x100>;
		interrupts = <0x0 0x51 0x4>;
		interrupt-names = "vpu_mmu";
		clocks = <0x2 0xaf 0x2 0xf4>;
		clock-names = "aclk", "iface";
		power-domains = <0x8a 0xb>;
		#iommu-cells = <0x0>;
		status = "okay";
		phandle = <0x9a>;
	};

	vepu@ff442000 {
		compatible = "rockchip,vpu-encoder-px30";
		reg = <0x0 0xff442000 0x0 0x400>;
		interrupts = <0x0 0x50 0x4>;
		interrupt-names = "irq_enc";
		clocks = <0x2 0xaf 0x2 0xf4>;
		clock-names = "aclk_vcodec", "hclk_vcodec";
		resets = <0x2 0x24 0x2 0x26>;
		reset-names = "shared_video_a", "shared_video_h";
		iommus = <0x9a>;
		power-domains = <0x8a 0xb>;
		rockchip,srv = <0x9b>;
		rockchip,taskqueue-node = <0x0>;
		rockchip,resetgroup-node = <0x0>;
		status = "okay";
		phandle = <0x119>;
	};

	hevc@ff440000 {
		compatible = "rockchip,hevc-decoder-px30";
		reg = <0x0 0xff440000 0x0 0x400>;
		interrupts = <0x0 0x31 0x4>;
		interrupt-names = "irq_dec";
		clocks = <0x2 0xaf 0x2 0xf4 0x2 0x4b>;
		clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
		resets = <0x2 0x24 0x2 0x26 0x2 0x25 0x2 0x27 0x2 0x3f>;
		reset-names = "shared_video_a", "shared_video_h", "niu_a", "niu_h", "video_core";
		iommus = <0x9c>;
		rockchip,srv = <0x9b>;
		rockchip,taskqueue-node = <0x0>;
		rockchip,resetgroup-node = <0x0>;
		power-domains = <0x8a 0xb>;
		status = "okay";
		phandle = <0x11a>;
	};

	iommu@ff440440 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff440440 0x0 0x40 0x0 0xff440480 0x0 0x40>;
		interrupts = <0x0 0x32 0x4>;
		interrupt-names = "hevc_mmu";
		clocks = <0x2 0xaf 0x2 0xf4>;
		clock-names = "aclk", "iface";
		power-domains = <0x8a 0xb>;
		#iommu-cells = <0x0>;
		status = "okay";
		phandle = <0x9c>;
	};

	dsi@ff450000 {
		compatible = "rockchip,px30-mipi-dsi";
		reg = <0x0 0xff450000 0x0 0x10000>;
		interrupts = <0x0 0x4b 0x4>;
		clocks = <0x2 0x144 0x4d>;
		clock-names = "pclk", "hs_clk";
		resets = <0x2 0x3d>;
		reset-names = "apb";
		phys = <0x4d>;
		phy-names = "mipi_dphy";
		power-domains = <0x8a 0xc>;
		rockchip,grf = <0x2f>;
		#address-cells = <0x1>;
		#size-cells = <0x0>;
		status = "okay";
		phandle = <0x11b>;

		ports {
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			port@0 {
				reg = <0x0>;
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				endpoint@0 {
					reg = <0x0>;
					remote-endpoint = <0x14>;
					status = "okay";
					phandle = <0xa5>;
				};

				endpoint@1 {
					reg = <0x1>;
					remote-endpoint = <0x9d>;
					status = "disabled";
					phandle = <0xa9>;
				};
			};

			port@1 {
				reg = <0x1>;

				endpoint {
					remote-endpoint = <0x9e>;
					phandle = <0xa2>;
				};
			};
		};

		panel@0 {
			compatible = "sitronix,st7703", "simple-panel-dsi";
			reg = <0x0>;
			power-supply = <0x9f>;
			backlight = <0xa0>;
			prepare-delay-ms = <0x2>;
			reset-delay-ms = <0x1>;
			init-delay-ms = <0x14>;
			enable-delay-ms = <0x78>;
			disable-delay-ms = <0x32>;
			unprepare-delay-ms = <0x14>;
			width-mm = <0x44>;
			height-mm = <0x79>;
			dsi,flags = <0xa03>;
			dsi,format = <0x0>;
			dsi,lanes = <0x4>;
			panel-init-sequence = [15 0a 02 e0 00 15 00 02 e1 93 15 00 02 e2 65 15 00 02 e3 f8 15 00 02 80 03 15 00 02 e0 01 15 00 02 00 00 15 00 02 01 38 15 00 02 0c 74 15 00 02 17 00 15 00 02 18 af 15 00 02 19 00 15 00 02 1a 00 15 00 02 1b af 15 00 02 1c 00 15 00 02 35 26 15 00 02 37 09 15 00 02 38 04 15 00 02 39 00 15 00 02 3a 01 15 00 02 3c 78 15 00 02 3d ff 15 00 02 3e ff 15 00 02 3f 7f 15 00 02 40 06 15 00 02 41 a0 15 00 02 42 81 15 00 02 43 14 15 00 02 44 23 15 00 02 45 28 15 00 02 55 02 15 00 02 57 69 15 00 02 59 0a 15 00 02 5a 2a 15 00 02 5b 17 15 00 02 5d 7f 15 00 02 5e 6a 15 00 02 5f 5b 15 00 02 60 4f 15 00 02 61 4a 15 00 02 62 3d 15 00 02 63 41 15 00 02 64 2a 15 00 02 65 44 15 00 02 66 43 15 00 02 67 44 15 00 02 68 62 15 00 02 69 52 15 00 02 6a 59 15 00 02 6b 4c 15 00 02 6c 48 15 00 02 6d 3a 15 00 02 6e 26 15 00 02 6f 00 15 00 02 70 7f 15 00 02 71 6a 15 00 02 72 5b 15 00 02 73 4f 15 00 02 74 4a 15 00 02 75 3d 15 00 02 76 41 15 00 02 77 2a 15 00 02 78 44 15 00 02 79 43 15 00 02 7a 44 15 00 02 7b 62 15 00 02 7c 52 15 00 02 7d 59 15 00 02 7e 4c 15 00 02 7f 48 15 00 02 80 3a 15 00 02 81 26 15 00 02 82 00 15 00 02 e0 02 15 00 02 00 02 15 00 02 01 02 15 00 02 02 00 15 00 02 03 00 15 00 02 04 1e 15 00 02 05 1e 15 00 02 06 1f 15 00 02 07 1f 15 00 02 08 1f 15 00 02 09 17 15 00 02 0a 17 15 00 02 0b 37 15 00 02 0c 37 15 00 02 0d 47 15 00 02 0e 47 15 00 02 0f 45 15 00 02 10 45 15 00 02 11 4b 15 00 02 12 4b 15 00 02 13 49 15 00 02 14 49 15 00 02 15 1f 15 00 02 16 01 15 00 02 17 01 15 00 02 18 00 15 00 02 19 00 15 00 02 1a 1e 15 00 02 1b 1e 15 00 02 1c 1f 15 00 02 1d 1f 15 00 02 1e 1f 15 00 02 1f 17 15 00 02 20 17 15 00 02 21 37 15 00 02 22 37 15 00 02 23 46 15 00 02 24 46 15 00 02 25 44 15 00 02 26 44 15 00 02 27 4a 15 00 02 28 4a 15 00 02 29 48 15 00 02 2a 48 15 00 02 2b 1f 15 00 02 2c 01 15 00 02 2d 01 15 00 02 2e 00 15 00 02 2f 00 15 00 02 30 1f 15 00 02 31 1f 15 00 02 32 1e 15 00 02 33 1e 15 00 02 34 1f 15 00 02 35 17 15 00 02 36 17 15 00 02 37 37 15 00 02 38 37 15 00 02 39 08 15 00 02 3a 08 15 00 02 3b 0a 15 00 02 3c 0a 15 00 02 3d 04 15 00 02 3e 04 15 00 02 3f 06 15 00 02 40 06 15 00 02 41 1f 15 00 02 42 02 15 00 02 43 02 15 00 02 44 00 15 00 02 45 00 15 00 02 46 1f 15 00 02 47 1f 15 00 02 48 1e 15 00 02 49 1e 15 00 02 4a 1f 15 00 02 4b 17 15 00 02 4c 17 15 00 02 4d 37 15 00 02 4e 37 15 00 02 4f 09 15 00 02 50 09 15 00 02 51 0b 15 00 02 52 0b 15 00 02 53 05 15 00 02 54 05 15 00 02 55 07 15 00 02 56 07 15 00 02 57 1f 15 00 02 58 40 15 00 02 5b 30 15 00 02 5c 16 15 00 02 5d 34 15 00 02 5e 05 15 00 02 5f 02 15 00 02 63 00 15 00 02 64 6a 15 00 02 67 73 15 00 02 68 1d 15 00 02 69 08 15 00 02 6a 6a 15 00 02 6b 08 15 00 02 6c 00 15 00 02 6d 00 15 00 02 6e 00 15 00 02 6f 88 15 00 02 75 ff 15 00 02 77 dd 15 00 02 78 3f 15 00 02 79 15 15 00 02 7a 17 15 00 02 7d 14 15 00 02 7e 82 15 00 02 e0 04 15 00 02 00 0e 15 00 02 02 b3 15 00 02 09 61 15 00 02 0e 48 15 00 02 e0 00 15 00 02 e6 02 15 00 02 e7 0c 15 00 02 11 00 15 78 02 29 00 15 05 02 35 00];

			display-timings {
				native-mode = <0xa1>;

				timing1 {
					clock-frequency = <0x43b5fc0>;
					hactive = <0x320>;
					vactive = <0x500>;
					hfront-porch = <0x30>;
					hsync-len = <0x8>;
					hback-porch = <0x2a>;
					vfront-porch = <0xf>;
					vsync-len = <0x6>;
					vback-porch = <0x10>;
					hsync-active = <0x0>;
					vsync-active = <0x0>;
					de-active = <0x1>;
					pixelclk-active = <0x0>;
					swap-rb = <0x0>;
					swap-rg = <0x1>;
					swap-gb = <0x1>;
					phandle = <0xa1>;
				};
			};

			ports {
				#address-cells = <0x1>;
				#size-cells = <0x0>;

				port@0 {
					reg = <0x0>;

					endpoint {
						remote-endpoint = <0xa2>;
						phandle = <0x9e>;
					};
				};
			};
		};
	};

	vop@ff460000 {
		compatible = "rockchip,px30-vop-big";
		reg = <0x0 0xff460000 0x0 0x1fc 0x0 0xff460a00 0x0 0x400>;
		rockchip,grf = <0x2f>;
		reg-names = "regs", "gamma_lut";
		interrupts = <0x0 0x4d 0x4>;
		clocks = <0x2 0xb5 0x2 0x96 0x2 0xfb>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <0x8a 0xc>;
		iommus = <0xa3>;
		status = "okay";
		phandle = <0x11c>;

		port {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phandle = <0x10>;

			endpoint@0 {
				reg = <0x0>;
				remote-endpoint = <0xa4>;
				phandle = <0x13>;
			};

			endpoint@1 {
				reg = <0x1>;
				remote-endpoint = <0xa5>;
				phandle = <0x14>;
			};

			endpoint@2 {
				reg = <0x2>;
				remote-endpoint = <0xa6>;
				phandle = <0x15>;
			};
		};
	};

	iommu@ff460f00 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff460f00 0x0 0x100>;
		interrupts = <0x0 0x4d 0x4>;
		interrupt-names = "vopb_mmu";
		clocks = <0x2 0xb5 0x2 0xfb>;
		clock-names = "aclk", "iface";
		power-domains = <0x8a 0xc>;
		#iommu-cells = <0x0>;
		rockchip,disable-device-link-resume;
		status = "okay";
		phandle = <0xa3>;
	};

	vop@ff470000 {
		compatible = "rockchip,px30-vop-lit";
		reg = <0x0 0xff470000 0x0 0x1fc 0x0 0xff470a00 0x0 0x400>;
		rockchip,grf = <0x2f>;
		reg-names = "regs", "gamma_lut";
		interrupts = <0x0 0x4e 0x4>;
		clocks = <0x2 0xb6 0x2 0x97 0x2 0xfc>;
		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
		power-domains = <0x8a 0xc>;
		iommus = <0xa7>;
		status = "okay";
		phandle = <0x11d>;

		port {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phandle = <0x11>;

			endpoint@0 {
				reg = <0x0>;
				remote-endpoint = <0xa8>;
				phandle = <0x4e>;
			};

			endpoint@1 {
				reg = <0x1>;
				remote-endpoint = <0xa9>;
				phandle = <0x9d>;
			};

			endpoint@2 {
				reg = <0x2>;
				remote-endpoint = <0xaa>;
				phandle = <0x51>;
			};
		};
	};

	iommu@ff470f00 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff470f00 0x0 0x100>;
		interrupts = <0x0 0x4e 0x4>;
		interrupt-names = "vopl_mmu";
		clocks = <0x2 0xb6 0x2 0xfc>;
		clock-names = "aclk", "iface";
		power-domains = <0x8a 0xc>;
		#iommu-cells = <0x0>;
		rockchip,disable-device-link-resume;
		status = "okay";
		phandle = <0xa7>;
	};

	rk_rga@ff480000 {
		compatible = "rockchip,rga2";
		reg = <0x0 0xff480000 0x0 0x1000>;
		interrupts = <0x0 0x4c 0x4>;
		clocks = <0x2 0xb7 0x2 0xfd 0x2 0x35>;
		clock-names = "aclk_rga", "hclk_rga", "clk_rga";
		power-domains = <0x8a 0xc>;
		status = "okay";
		phandle = <0x11e>;
	};

	cif@ff490000 {
		compatible = "rockchip,cif";
		reg = <0x0 0xff490000 0x0 0x200>;
		interrupts = <0x0 0x45 0x4>;
		clocks = <0x2 0xb3 0x2 0xf9 0x2 0x160 0x2 0x34>;
		clock-names = "aclk_cif0", "hclk_cif0", "pclk_cif", "cif0_out";
		resets = <0x2 0x2c 0x2 0x2d 0x2 0x2e>;
		reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
		power-domains = <0x8a 0xd>;
		pinctrl-names = "cif_pin_all";
		pinctrl-0 = <0xab>;
		iommus = <0xac>;
		status = "disabled";
		phandle = <0x11f>;
	};

	cif-new@ff490000 {
		compatible = "rockchip,px30-cif";
		reg = <0x0 0xff490000 0x0 0x200>;
		interrupts = <0x0 0x45 0x4>;
		clocks = <0x2 0xb3 0x2 0xf9 0x2 0x160 0x2 0x34>;
		clock-names = "aclk_cif", "hclk_cif", "pclk_cif", "cif_out";
		resets = <0x2 0x2c 0x2 0x2d 0x2 0x2e>;
		reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_pclkin";
		power-domains = <0x8a 0xd>;
		iommus = <0xac>;
		status = "disabled";
		phandle = <0x120>;
	};

	iommu@ff490800 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff490800 0x0 0x100>;
		interrupts = <0x0 0x45 0x4>;
		interrupt-names = "vip_mmu";
		clocks = <0x2 0xb3 0x2 0xf9>;
		clock-names = "aclk", "iface";
		power-domains = <0x8a 0xd>;
		rk_iommu,disable_reset_quirk;
		#iommu-cells = <0x0>;
		status = "disabled";
		phandle = <0xac>;
	};

	rk_isp@ff4a0000 {
		compatible = "rockchip,px30-isp", "rockchip,isp";
		reg = <0x0 0xff4a0000 0x0 0x8000>;
		interrupts = <0x0 0x46 0x4>;
		clocks = <0x2 0xb4 0x2 0xfa 0x2 0x33 0x2 0x33 0x2 0x15f 0x2 0x34 0x2 0x34 0x2 0x146>;
		clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_pll", "clk_cif_out", "pclk_dphyrx";
		resets = <0x2 0x2b 0x2 0x2f>;
		reset-names = "rst_isp", "rst_mipicsiphy";
		power-domains = <0x8a 0xd>;
		pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit";
		pinctrl-0 = <0xad>;
		pinctrl-1 = <0xab>;
		pinctrl-2 = <0xab 0xae>;
		pinctrl-3 = <0xaf 0xab 0xae>;
		rockchip,isp,mipiphy = <0x1>;
		rockchip,isp,csiphy,reg = <0xff2f0000 0x4000>;
		rockchip,grf = <0x2f>;
		rockchip,cru = <0x2>;
		rockchip,isp,iommu-enable = <0x1>;
		iommus = <0xb0>;
		status = "disabled";
		phandle = <0x121>;
	};

	rkisp1@ff4a0000 {
		compatible = "rockchip,rk3326-rkisp1";
		reg = <0x0 0xff4a0000 0x0 0x8000>;
		interrupts = <0x0 0x46 0x4 0x0 0x49 0x4 0x0 0x4a 0x4>;
		interrupt-names = "isp_irq", "mi_irq", "mipi_irq";
		clocks = <0x2 0xb4 0x2 0xfa 0x2 0x33 0x2 0x15f>;
		clock-names = "aclk_isp", "hclk_isp", "clk_isp", "pclk_isp";
		devfreq = <0xb1>;
		power-domains = <0x8a 0xd>;
		iommus = <0xb0>;
		rockchip,grf = <0x2f>;
		status = "disabled";
		phandle = <0x122>;
	};

	iommu@ff4a8000 {
		compatible = "rockchip,iommu";
		reg = <0x0 0xff4a8000 0x0 0x100>;
		interrupts = <0x0 0x46 0x4>;
		interrupt-names = "isp_mmu";
		clocks = <0x2 0xb4 0x2 0xfa>;
		clock-names = "aclk", "iface";
		power-domains = <0x8a 0xd>;
		rk_iommu,disable_reset_quirk;
		#iommu-cells = <0x0>;
		status = "disabled";
		phandle = <0xb0>;
	};

	qos@ff518000 {
		compatible = "syscon";
		reg = <0x0 0xff518000 0x0 0x20>;
		phandle = <0x1a>;
	};

	qos@ff520000 {
		compatible = "syscon";
		reg = <0x0 0xff520000 0x0 0x20>;
		phandle = <0x2a>;
	};

	qos@ff52c000 {
		compatible = "syscon";
		reg = <0x0 0xff52c000 0x0 0x20>;
		phandle = <0x19>;
	};

	qos@ff538000 {
		compatible = "syscon";
		reg = <0x0 0xff538000 0x0 0x20>;
		phandle = <0x1b>;
	};

	qos@ff538080 {
		compatible = "syscon";
		reg = <0x0 0xff538080 0x0 0x20>;
		phandle = <0x1c>;
	};

	qos@ff538100 {
		compatible = "syscon";
		reg = <0x0 0xff538100 0x0 0x20>;
		phandle = <0x1d>;
	};

	qos@ff538180 {
		compatible = "syscon";
		reg = <0x0 0xff538180 0x0 0x20>;
		phandle = <0x1e>;
	};

	qos@ff540000 {
		compatible = "syscon";
		reg = <0x0 0xff540000 0x0 0x20>;
		phandle = <0x17>;
	};

	qos@ff540080 {
		compatible = "syscon";
		reg = <0x0 0xff540080 0x0 0x20>;
		phandle = <0x18>;
	};

	qos@ff548000 {
		compatible = "syscon";
		reg = <0x0 0xff548000 0x0 0x20>;
		phandle = <0x25>;
	};

	qos@ff548080 {
		compatible = "syscon";
		reg = <0x0 0xff548080 0x0 0x20>;
		phandle = <0x26>;
	};

	qos@ff548100 {
		compatible = "syscon";
		reg = <0x0 0xff548100 0x0 0x20>;
		phandle = <0x27>;
	};

	qos@ff548180 {
		compatible = "syscon";
		reg = <0x0 0xff548180 0x0 0x20>;
		phandle = <0x28>;
	};

	qos@ff548200 {
		compatible = "syscon";
		reg = <0x0 0xff548200 0x0 0x20>;
		phandle = <0x29>;
	};

	qos@ff550000 {
		compatible = "syscon";
		reg = <0x0 0xff550000 0x0 0x20>;
		phandle = <0x21>;
	};

	qos@ff550080 {
		compatible = "syscon";
		reg = <0x0 0xff550080 0x0 0x20>;
		phandle = <0x22>;
	};

	qos@ff550100 {
		compatible = "syscon";
		reg = <0x0 0xff550100 0x0 0x20>;
		phandle = <0x23>;
	};

	qos@ff550180 {
		compatible = "syscon";
		reg = <0x0 0xff550180 0x0 0x20>;
		phandle = <0x24>;
	};

	qos@ff558000 {
		compatible = "syscon";
		reg = <0x0 0xff558000 0x0 0x20>;
		phandle = <0x1f>;
	};

	qos@ff558080 {
		compatible = "syscon";
		reg = <0x0 0xff558080 0x0 0x20>;
		phandle = <0x20>;
	};

	dfi@ff610000 {
		reg = <0x0 0xff610000 0x0 0x400>;
		compatible = "rockchip,px30-dfi";
		rockchip,pmugrf = <0xb2>;
		status = "disabled";
		phandle = <0xb3>;
	};

	dmc {
		compatible = "rockchip,px30-dmc";
		interrupts = <0x0 0x69 0x4>;
		interrupt-names = "complete_irq";
		devfreq-events = <0xb3>;
		clocks = <0x2 0x54>;
		clock-names = "dmc_clk";
		operating-points-v2 = <0xb4>;
		ddr_timing = <0xb5>;
		upthreshold = <0x28>;
		downdifferential = <0x14>;
		system-status-freq = <0x1 0x80e80 0x8 0x6ddd0 0x2 0x2f5d0 0x20 0x6ddd0 0x1000 0x80e80 0x4000 0xa2990 0x2000 0x101d00>;
		auto-min-freq = <0x50140>;
		auto-freq-en = <0x1>;
		#cooling-cells = <0x2>;
		status = "disabled";
		phandle = <0xb1>;

		ddr_power_model {
			compatible = "ddr_power_model";
			dynamic-power-coefficient = <0x78>;
			static-power-coefficient = <0xc8>;
			ts = <0x7d00 0x125c 0xffffffb0 0x2>;
			thermal-zone = "soc-thermal";
			phandle = <0x123>;
		};
	};

	dmc-fsp {
		compatible = "rockchip,px30s-dmc-fsp";
		debug_print_level = <0x0>;
		phy_de_skew_en = <0x1>;
		ddr3_params = <0xb6>;
		ddr4_params = <0xb7>;
		lpddr2_params = <0xb8>;
		lpddr3_params = <0xb9>;
		lpddr4_params = <0xba>;
		ddr_timing = <0xb5>;
		status = "okay";
		phandle = <0x124>;
	};

	dmc-opp-table {
		compatible = "operating-points-v2";
		rockchip,max-volt = <0x118c30>;
		rockchip,evb-irdrop = <0x61a8>;
		rockchip,pvtm-voltage-sel = <0x0 0xc350 0x0 0xc351 0xd2f0 0x1 0xd2f1 0xea60 0x2 0xea61 0x1869f 0x3>;
		rockchip,pvtm-ch = <0x0 0x0>;
		phandle = <0xb4>;

		opp-194000000 {
			opp-hz = <0x0 0xb903480>;
			opp-microvolt = <0xe7ef0>;
			opp-microvolt-L0 = <0xe7ef0>;
			opp-microvolt-L1 = <0xe7ef0>;
			opp-microvolt-L2 = <0xe7ef0>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-328000000 {
			opp-hz = <0x0 0x138ce200>;
			opp-microvolt = <0xe7ef0>;
			opp-microvolt-L0 = <0xe7ef0>;
			opp-microvolt-L1 = <0xe7ef0>;
			opp-microvolt-L2 = <0xe7ef0>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-450000000 {
			opp-hz = <0x0 0x1ad27480>;
			opp-microvolt = <0xe7ef0>;
			opp-microvolt-L0 = <0xe7ef0>;
			opp-microvolt-L1 = <0xe7ef0>;
			opp-microvolt-L2 = <0xe7ef0>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-528000000 {
			opp-hz = <0x0 0x1f78a400>;
			opp-microvolt = <0xee098>;
			opp-microvolt-L0 = <0xee098>;
			opp-microvolt-L1 = <0xee098>;
			opp-microvolt-L2 = <0xe7ef0>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-666000000 {
			opp-hz = <0x0 0x27b25a80>;
			opp-microvolt = <0x100590>;
			opp-microvolt-L0 = <0x100590>;
			opp-microvolt-L1 = <0xf4240>;
			opp-microvolt-L2 = <0xee098>;
			opp-microvolt-L3 = <0xe7ef0>;
		};

		opp-786000000 {
			opp-hz = <0x0 0x2ed96880>;
			opp-microvolt = <0x10c8e0>;
			opp-microvolt-L0 = <0x10c8e0>;
			opp-microvolt-L1 = <0x100590>;
			opp-microvolt-L2 = <0xfa3e8>;
			opp-microvolt-L3 = <0xf4240>;
			status = "disabled";
		};
	};

	px30s-dmc-opp-table {
		compatible = "operating-points-v2";
		phandle = <0x125>;

		opp-194000000 {
			opp-hz = <0x0 0xb903480>;
			opp-microvolt = <0xe7ef0>;
		};

		opp-328000000 {
			opp-hz = <0x0 0x138ce200>;
			opp-microvolt = <0xe7ef0>;
		};

		opp-528000000 {
			opp-hz = <0x0 0x1f78a400>;
			opp-microvolt = <0xe7ef0>;
			status = "disabled";
		};

		opp-666000000 {
			opp-hz = <0x0 0x27b25a80>;
			opp-microvolt = <0xe7ef0>;
		};

		opp-786000000 {
			opp-hz = <0x0 0x2ed96880>;
			opp-microvolt = <0xe7ef0>;
			status = "disabled";
		};

		opp-924000000 {
			opp-hz = <0x0 0x37131f00>;
			opp-microvolt = <0xe7ef0>;
			status = "disabled";
		};

		opp-1056000000 {
			opp-hz = <0x0 0x3ef14800>;
			opp-microvolt = <0xe7ef0>;
			status = "disabled";
		};
	};

	dmcdbg {
		compatible = "rockchip,px30-dmcdbg";
		status = "okay";
		phandle = <0x126>;
	};

	rockchip-system-monitor {
		compatible = "rockchip,system-monitor";
		rockchip,thermal-zone = "soc-thermal";
		rockchip,polling-delay = <0xc8>;
		phandle = <0x127>;
	};

	pinctrl {
		compatible = "rockchip,px30-pinctrl";
		rockchip,grf = <0x2f>;
		rockchip,pmu = <0xb2>;
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;
		phandle = <0x128>;

		gpio0@ff040000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff040000 0x0 0x100>;
			interrupts = <0x0 0x3 0x4>;
			clocks = <0x2c 0x14>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x5c>;
		};

		gpio1@ff250000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff250000 0x0 0x100>;
			interrupts = <0x0 0x4 0x4>;
			clocks = <0x2 0x15c>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0xcc>;
		};

		gpio2@ff260000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff260000 0x0 0x100>;
			interrupts = <0x0 0x5 0x4>;
			clocks = <0x2 0x15d>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x67>;
		};

		gpio3@ff270000 {
			compatible = "rockchip,gpio-bank";
			reg = <0x0 0xff270000 0x0 0x100>;
			interrupts = <0x0 0x6 0x4>;
			clocks = <0x2 0x15e>;
			gpio-controller;
			#gpio-cells = <0x2>;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			phandle = <0x129>;
		};

		pcfg-pull-up {
			bias-pull-up;
			phandle = <0xbd>;
		};

		pcfg-pull-down {
			bias-pull-down;
			phandle = <0x12a>;
		};

		pcfg-pull-none {
			bias-disable;
			phandle = <0xbc>;
		};

		pcfg-pull-none-2ma {
			bias-disable;
			drive-strength = <0x2>;
			phandle = <0x12b>;
		};

		pcfg-pull-up-2ma {
			bias-pull-up;
			drive-strength = <0x2>;
			phandle = <0x12c>;
		};

		pcfg-pull-up-4ma {
			bias-pull-up;
			drive-strength = <0x4>;
			phandle = <0xbe>;
		};

		pcfg-pull-none-4ma {
			bias-disable;
			drive-strength = <0x4>;
			phandle = <0x12d>;
		};

		pcfg-pull-down-4ma {
			bias-pull-down;
			drive-strength = <0x4>;
			phandle = <0x12e>;
		};

		pcfg-pull-none-8ma {
			bias-disable;
			drive-strength = <0x8>;
			phandle = <0xc1>;
		};

		pcfg-pull-up-8ma {
			bias-pull-up;
			drive-strength = <0x8>;
			phandle = <0xbf>;
		};

		pcfg-pull-none-12ma {
			bias-disable;
			drive-strength = <0xc>;
			phandle = <0xc5>;
		};

		pcfg-pull-up-12ma {
			bias-pull-up;
			drive-strength = <0xc>;
			phandle = <0xc4>;
		};

		pcfg-pull-none-smt {
			bias-disable;
			input-schmitt-enable;
			phandle = <0xbb>;
		};

		pcfg-output-high {
			output-high;
			phandle = <0x12f>;
		};

		pcfg-output-low {
			output-low;
			phandle = <0xc6>;
		};

		pcfg-input-high {
			bias-pull-up;
			input-enable;
			phandle = <0xc0>;
		};

		pcfg-input {
			input-enable;
			phandle = <0x130>;
		};

		i2c0 {

			i2c0-xfer {
				rockchip,pins = <0x0 0x8 0x1 0xbb 0x0 0x9 0x1 0xbb>;
				phandle = <0x5b>;
			};
		};

		i2c1 {

			i2c1-xfer {
				rockchip,pins = <0x0 0x12 0x1 0xbb 0x0 0x13 0x1 0xbb>;
				phandle = <0x68>;
			};
		};

		i2c2 {

			i2c2-xfer {
				rockchip,pins = <0x2 0xf 0x2 0xbb 0x2 0x10 0x2 0xbb>;
				phandle = <0x69>;
			};
		};

		i2c3 {

			i2c3-xfer {
				rockchip,pins = <0x1 0xc 0x4 0xbb 0x1 0xd 0x4 0xbb>;
				phandle = <0x6a>;
			};
		};

		tsadc {

			tsadc-otp-gpio {
				rockchip,pins = <0x0 0x6 0x0 0xbc>;
				phandle = <0x85>;
			};

			tsadc-otp-out {
				rockchip,pins = <0x0 0x6 0x1 0xbc>;
				phandle = <0x86>;
			};
		};

		uart0 {

			uart0-xfer {
				rockchip,pins = <0x0 0xa 0x1 0xbd 0x0 0xb 0x1 0xbd>;
				phandle = <0x2e>;
			};

			uart0-cts {
				rockchip,pins = <0x0 0xc 0x1 0xbc>;
				phandle = <0x131>;
			};

			uart0-rts {
				rockchip,pins = <0x0 0xd 0x1 0xbc>;
				phandle = <0x132>;
			};

			uart0-rts-gpio {
				rockchip,pins = <0x0 0xd 0x0 0xbc>;
				phandle = <0x133>;
			};
		};

		uart1 {

			uart1-xfer {
				rockchip,pins = <0x1 0x11 0x1 0xbd 0x1 0x10 0x1 0xbd>;
				phandle = <0x52>;
			};

			uart1-cts {
				rockchip,pins = <0x1 0x12 0x1 0xbc>;
				phandle = <0x134>;
			};

			uart1-rts {
				rockchip,pins = <0x1 0x13 0x1 0xbc>;
				phandle = <0x135>;
			};

			uart1-rts-gpio {
				rockchip,pins = <0x1 0x13 0x0 0xbc>;
				phandle = <0x136>;
			};
		};

		uart2-m0 {

			uart2m0-xfer {
				rockchip,pins = <0x1 0x1a 0x2 0xbd 0x1 0x1b 0x2 0xbd>;
				phandle = <0x53>;
			};
		};

		uart2-m1 {

			uart2m1-xfer {
				rockchip,pins = <0x2 0xc 0x2 0xbd 0x2 0xe 0x2 0xbd>;
				phandle = <0x137>;
			};
		};

		uart3-m0 {

			uart3m0-xfer {
				rockchip,pins = <0x0 0x10 0x2 0xbd 0x0 0x11 0x2 0xbd>;
				phandle = <0x138>;
			};

			uart3m0-cts {
				rockchip,pins = <0x0 0x12 0x2 0xbc>;
				phandle = <0x139>;
			};

			uart3m0-rts {
				rockchip,pins = <0x0 0x13 0x2 0xbc>;
				phandle = <0x13a>;
			};

			uart3m0-rts-gpio {
				rockchip,pins = <0x0 0x13 0x0 0xbc>;
				phandle = <0x13b>;
			};
		};

		uart3-m1 {

			uart3m1-xfer {
				rockchip,pins = <0x1 0xe 0x2 0xbd 0x1 0xf 0x2 0xbd>;
				phandle = <0x54>;
			};

			uart3m1-cts {
				rockchip,pins = <0x1 0xc 0x2 0xbc>;
				phandle = <0x55>;
			};

			uart3m1-rts {
				rockchip,pins = <0x1 0xd 0x2 0xbc>;
				phandle = <0x56>;
			};

			uart3m1-rts-gpio {
				rockchip,pins = <0x1 0xd 0x0 0xbc>;
				phandle = <0x13c>;
			};
		};

		uart4 {

			uart4-xfer {
				rockchip,pins = <0x1 0x1c 0x2 0xbd 0x1 0x1d 0x2 0xbd>;
				phandle = <0x57>;
			};

			uart4-cts {
				rockchip,pins = <0x1 0x1e 0x2 0xbc>;
				phandle = <0x13d>;
			};

			uart4-rts {
				rockchip,pins = <0x1 0x1f 0x2 0xbc>;
				phandle = <0x13e>;
			};
		};

		uart5 {

			uart5-xfer {
				rockchip,pins = <0x3 0x2 0x4 0xbd 0x3 0x1 0x4 0xbd>;
				phandle = <0x58>;
			};

			uart5-cts {
				rockchip,pins = <0x3 0x3 0x4 0xbc>;
				phandle = <0x59>;
			};

			uart5-rts {
				rockchip,pins = <0x3 0x5 0x4 0xbc>;
				phandle = <0x5a>;
			};
		};

		spi0 {

			spi0-clk {
				rockchip,pins = <0x1 0xf 0x3 0xbe>;
				phandle = <0x6b>;
			};

			spi0-csn {
				rockchip,pins = <0x1 0xe 0x3 0xbe>;
				phandle = <0x6c>;
			};

			spi0-miso {
				rockchip,pins = <0x1 0xd 0x3 0xbe>;
				phandle = <0x6d>;
			};

			spi0-mosi {
				rockchip,pins = <0x1 0xc 0x3 0xbe>;
				phandle = <0x6e>;
			};

			spi0-clk-hs {
				rockchip,pins = <0x1 0xf 0x3 0xbf>;
				phandle = <0x6f>;
			};

			spi0-miso-hs {
				rockchip,pins = <0x1 0xd 0x3 0xbf>;
				phandle = <0x70>;
			};

			spi0-mosi-hs {
				rockchip,pins = <0x1 0xc 0x3 0xbf>;
				phandle = <0x71>;
			};
		};

		spi1 {

			spi1-clk {
				rockchip,pins = <0x3 0xf 0x4 0xbe>;
				phandle = <0x72>;
			};

			spi1-csn0 {
				rockchip,pins = <0x3 0x9 0x4 0xbe>;
				phandle = <0x73>;
			};

			spi1-csn1 {
				rockchip,pins = <0x3 0xa 0x2 0xbe>;
				phandle = <0x74>;
			};

			spi1-miso {
				rockchip,pins = <0x3 0xe 0x4 0xbe>;
				phandle = <0x75>;
			};

			spi1-mosi {
				rockchip,pins = <0x3 0xc 0x4 0xbe>;
				phandle = <0x76>;
			};

			spi1-clk-hs {
				rockchip,pins = <0x3 0xf 0x4 0xbf>;
				phandle = <0x77>;
			};

			spi1-miso-hs {
				rockchip,pins = <0x3 0xe 0x4 0xbf>;
				phandle = <0x78>;
			};

			spi1-mosi-hs {
				rockchip,pins = <0x3 0xc 0x4 0xbf>;
				phandle = <0x79>;
			};
		};

		pdm {

			pdm-clk0m0 {
				rockchip,pins = <0x3 0x16 0x2 0xbc>;
				phandle = <0x44>;
			};

			pdm-clk0m1 {
				rockchip,pins = <0x2 0x16 0x1 0xbc>;
				phandle = <0x13f>;
			};

			pdm-clk1 {
				rockchip,pins = <0x3 0x17 0x2 0xbc>;
				phandle = <0x45>;
			};

			pdm-sdi0m0 {
				rockchip,pins = <0x3 0x1b 0x2 0xbc>;
				phandle = <0x46>;
			};

			pdm-sdi0m1 {
				rockchip,pins = <0x2 0x15 0x2 0xbc>;
				phandle = <0x140>;
			};

			pdm-sdi1 {
				rockchip,pins = <0x3 0x18 0x2 0xbc>;
				phandle = <0x47>;
			};

			pdm-sdi2 {
				rockchip,pins = <0x3 0x19 0x2 0xbc>;
				phandle = <0x48>;
			};

			pdm-sdi3 {
				rockchip,pins = <0x3 0x1a 0x2 0xbc>;
				phandle = <0x49>;
			};

			pdm-clk0m0-sleep {
				rockchip,pins = <0x3 0x16 0x0 0xc0>;
				phandle = <0x141>;
			};

			pdm-clk0m1-sleep {
				rockchip,pins = <0x2 0x16 0x0 0xc0>;
				phandle = <0x142>;
			};

			pdm-clk1-sleep {
				rockchip,pins = <0x3 0x17 0x0 0xc0>;
				phandle = <0x143>;
			};

			pdm-sdi0m0-sleep {
				rockchip,pins = <0x3 0x1b 0x0 0xc0>;
				phandle = <0x144>;
			};

			pdm-sdi0m1-sleep {
				rockchip,pins = <0x2 0x15 0x0 0xc0>;
				phandle = <0x145>;
			};

			pdm-sdi1-sleep {
				rockchip,pins = <0x3 0x18 0x0 0xc0>;
				phandle = <0x146>;
			};

			pdm-sdi2-sleep {
				rockchip,pins = <0x3 0x19 0x0 0xc0>;
				phandle = <0x147>;
			};

			pdm-sdi3-sleep {
				rockchip,pins = <0x3 0x1a 0x0 0xc0>;
				phandle = <0x148>;
			};
		};

		i2s0 {

			i2s0-8ch-mclk {
				rockchip,pins = <0x3 0x11 0x2 0xbc>;
				phandle = <0x149>;
			};

			i2s0-8ch-sclktx {
				rockchip,pins = <0x3 0x13 0x2 0xbc>;
				phandle = <0x30>;
			};

			i2s0-8ch-sclkrx {
				rockchip,pins = <0x3 0xc 0x2 0xbc>;
				phandle = <0x31>;
			};

			i2s0-8ch-lrcktx {
				rockchip,pins = <0x3 0x12 0x2 0xbc>;
				phandle = <0x32>;
			};

			i2s0-8ch-lrckrx {
				rockchip,pins = <0x3 0xd 0x2 0xbc>;
				phandle = <0x33>;
			};

			i2s0-8ch-sdo0 {
				rockchip,pins = <0x3 0x14 0x2 0xbc>;
				phandle = <0x38>;
			};

			i2s0-8ch-sdo1 {
				rockchip,pins = <0x3 0x10 0x2 0xbc>;
				phandle = <0x39>;
			};

			i2s0-8ch-sdo2 {
				rockchip,pins = <0x3 0xf 0x2 0xbc>;
				phandle = <0x3a>;
			};

			i2s0-8ch-sdo3 {
				rockchip,pins = <0x3 0xe 0x2 0xbc>;
				phandle = <0x3b>;
			};

			i2s0-8ch-sdi0 {
				rockchip,pins = <0x3 0x15 0x2 0xbc>;
				phandle = <0x34>;
			};

			i2s0-8ch-sdi1 {
				rockchip,pins = <0x3 0xb 0x2 0xbc>;
				phandle = <0x35>;
			};

			i2s0-8ch-sdi2 {
				rockchip,pins = <0x3 0x9 0x2 0xbc>;
				phandle = <0x36>;
			};

			i2s0-8ch-sdi3 {
				rockchip,pins = <0x3 0x8 0x2 0xbc>;
				phandle = <0x37>;
			};
		};

		i2s1 {

			i2s1-2ch-mclk {
				rockchip,pins = <0x2 0x13 0x1 0xbc>;
				phandle = <0x66>;
			};

			i2s1-2ch-sclk {
				rockchip,pins = <0x2 0x12 0x1 0xbc>;
				phandle = <0x3c>;
			};

			i2s1-2ch-lrck {
				rockchip,pins = <0x2 0x11 0x1 0xbc>;
				phandle = <0x3d>;
			};

			i2s1-2ch-sdi {
				rockchip,pins = <0x2 0x15 0x1 0xbc>;
				phandle = <0x3e>;
			};

			i2s1-2ch-sdo {
				rockchip,pins = <0x2 0x14 0x1 0xbc>;
				phandle = <0x3f>;
			};
		};

		i2s2 {

			i2s2-2ch-mclk {
				rockchip,pins = <0x3 0x1 0x2 0xbc>;
				phandle = <0x14a>;
			};

			i2s2-2ch-sclk {
				rockchip,pins = <0x3 0x2 0x2 0xbc>;
				phandle = <0x40>;
			};

			i2s2-2ch-lrck {
				rockchip,pins = <0x3 0x3 0x2 0xbc>;
				phandle = <0x41>;
			};

			i2s2-2ch-sdi {
				rockchip,pins = <0x3 0x5 0x2 0xbc>;
				phandle = <0x42>;
			};

			i2s2-2ch-sdo {
				rockchip,pins = <0x3 0x7 0x2 0xbc>;
				phandle = <0x43>;
			};
		};

		sdmmc {

			sdmmc-clk {
				rockchip,pins = <0x1 0x1e 0x1 0xc1>;
				phandle = <0x91>;
			};

			sdmmc-cmd {
				rockchip,pins = <0x1 0x1f 0x1 0xbf>;
				phandle = <0x92>;
			};

			sdmmc-det {
				rockchip,pins = <0x0 0x3 0x1 0xbf>;
				phandle = <0x93>;
			};

			sdmmc-bus1 {
				rockchip,pins = <0x1 0x1a 0x1 0xbf>;
				phandle = <0x14b>;
			};

			sdmmc-bus4 {
				rockchip,pins = <0x1 0x1a 0x1 0xbf 0x1 0x1b 0x1 0xbf 0x1 0x1c 0x1 0xbf 0x1 0x1d 0x1 0xbf>;
				phandle = <0x94>;
			};

			sdmmc-gpio {
				rockchip,pins = <0x1 0x1a 0x0 0xbe 0x1 0x1b 0x0 0xbe 0x1 0x1c 0x0 0xbe 0x1 0x1d 0x0 0xbe 0x1 0x1e 0x0 0xbe 0x1 0x1f 0x0 0xbe>;
				phandle = <0x14c>;
			};
		};

		sdio {

			sdio-clk {
				rockchip,pins = <0x1 0x15 0x1 0xbc>;
				phandle = <0x97>;
			};

			sdio-cmd {
				rockchip,pins = <0x1 0x14 0x1 0xbd>;
				phandle = <0x96>;
			};

			sdio-bus4 {
				rockchip,pins = <0x1 0x16 0x1 0xbd 0x1 0x17 0x1 0xbd 0x1 0x18 0x1 0xbd 0x1 0x19 0x1 0xbd>;
				phandle = <0x95>;
			};

			sdio-gpio {
				rockchip,pins = <0x1 0x16 0x0 0xbd 0x1 0x17 0x0 0xbd 0x1 0x18 0x0 0xbd 0x1 0x19 0x0 0xbd 0x1 0x14 0x0 0xbd 0x1 0x15 0x0 0xbd>;
				phandle = <0x14d>;
			};
		};

		emmc {

			emmc-clk {
				rockchip,pins = <0x1 0x9 0x2 0xc2>;
				phandle = <0x14e>;
			};

			emmc-cmd {
				rockchip,pins = <0x1 0xa 0x2 0xc3>;
				phandle = <0x14f>;
			};

			emmc-pwren {
				rockchip,pins = <0x1 0x8 0x2 0xbc>;
				phandle = <0x150>;
			};

			emmc-rstnout {
				rockchip,pins = <0x1 0xb 0x2 0xbc>;
				phandle = <0x151>;
			};

			emmc-bus1 {
				rockchip,pins = <0x1 0x0 0x2 0xc3>;
				phandle = <0x152>;
			};

			emmc-bus4 {
				rockchip,pins = <0x1 0x0 0x2 0xc3 0x1 0x1 0x2 0xc3 0x1 0x2 0x2 0xc3 0x1 0x3 0x2 0xc3>;
				phandle = <0x153>;
			};

			emmc-bus8 {
				rockchip,pins = <0x1 0x0 0x2 0xc3 0x1 0x1 0x2 0xc3 0x1 0x2 0x2 0xc3 0x1 0x3 0x2 0xc3 0x1 0x4 0x2 0xc3 0x1 0x5 0x2 0xc3 0x1 0x6 0x2 0xc3 0x1 0x7 0x2 0xc3>;
				phandle = <0x154>;
			};
		};

		flash {

			flash-cs0 {
				rockchip,pins = <0x1 0x8 0x1 0xbc>;
				phandle = <0x155>;
			};

			flash-rdy {
				rockchip,pins = <0x1 0x9 0x1 0xbc>;
				phandle = <0x156>;
			};

			flash-dqs {
				rockchip,pins = <0x1 0xa 0x1 0xbc>;
				phandle = <0x157>;
			};

			flash-ale {
				rockchip,pins = <0x1 0xb 0x1 0xbc>;
				phandle = <0x158>;
			};

			flash-cle {
				rockchip,pins = <0x1 0xc 0x1 0xbc>;
				phandle = <0x159>;
			};

			flash-wrn {
				rockchip,pins = <0x1 0xd 0x1 0xbc>;
				phandle = <0x15a>;
			};

			flash-csl {
				rockchip,pins = <0x1 0xe 0x1 0xbc>;
				phandle = <0x15b>;
			};

			flash-rdn {
				rockchip,pins = <0x1 0xf 0x1 0xbc>;
				phandle = <0x15c>;
			};

			flash-bus8 {
				rockchip,pins = <0x1 0x0 0x1 0xc4 0x1 0x1 0x1 0xc4 0x1 0x2 0x1 0xc4 0x1 0x3 0x1 0xc4 0x1 0x4 0x1 0xc4 0x1 0x5 0x1 0xc4 0x1 0x6 0x1 0xc4 0x1 0x7 0x1 0xc4>;
				phandle = <0x15d>;
			};
		};

		lcdc {

			lcdc-m0-rgb-pins {
				rockchip,pins = <0x3 0x0 0x1 0xc1 0x3 0x1 0x1 0xc1 0x3 0x2 0x1 0xc1 0x3 0x3 0x1 0xc1 0x3 0x4 0x1 0xc1 0x3 0x5 0x1 0xc1 0x3 0x6 0x1 0xc1 0x3 0x7 0x1 0xc1 0x3 0x8 0x1 0xc1 0x3 0x9 0x1 0xc1 0x3 0xa 0x1 0xc1 0x3 0xb 0x1 0xc1 0x3 0xc 0x1 0xc1 0x3 0xd 0x1 0xc1 0x3 0xe 0x1 0xc1 0x3 0xf 0x1 0xc1 0x3 0x10 0x1 0xc1 0x3 0x11 0x1 0xc1 0x3 0x12 0x1 0xc1 0x3 0x13 0x1 0xc1 0x3 0x14 0x1 0xc1 0x3 0x15 0x1 0xc1 0x3 0x16 0x1 0xc1 0x3 0x17 0x1 0xc1 0x3 0x18 0x1 0xc1 0x3 0x19 0x1 0xc1 0x3 0x1a 0x1 0xc1 0x3 0x1b 0x1 0xc1>;
				phandle = <0x4f>;
			};

			lcdc-m0-sleep-pins {
				rockchip,pins = <0x3 0x0 0x0 0xbc 0x3 0x1 0x0 0xbc 0x3 0x2 0x0 0xbc 0x3 0x3 0x0 0xbc 0x3 0x4 0x0 0xbc 0x3 0x5 0x0 0xbc 0x3 0x6 0x0 0xbc 0x3 0x7 0x0 0xbc 0x3 0x8 0x0 0xbc 0x3 0x9 0x0 0xbc 0x3 0xa 0x0 0xbc 0x3 0xb 0x0 0xbc 0x3 0xc 0x0 0xbc 0x3 0xd 0x0 0xbc 0x3 0xe 0x0 0xbc 0x3 0xf 0x0 0xbc 0x3 0x10 0x0 0xbc 0x3 0x11 0x0 0xbc 0x3 0x12 0x0 0xbc 0x3 0x13 0x0 0xbc 0x3 0x14 0x0 0xbc 0x3 0x15 0x0 0xbc 0x3 0x16 0x0 0xbc 0x3 0x17 0x0 0xbc 0x3 0x18 0x0 0xbc 0x3 0x19 0x0 0xbc 0x3 0x1a 0x0 0xbc 0x3 0x1b 0x0 0xbc>;
				phandle = <0x50>;
			};
		};

		pwm0 {

			pwm0-pin {
				rockchip,pins = <0x0 0xf 0x1 0xbc>;
				phandle = <0x7a>;
			};
		};

		pwm1 {

			pwm1-pin {
				rockchip,pins = <0x0 0x10 0x1 0xbc>;
				phandle = <0x7b>;
			};
		};

		pwm2 {

			pwm2-pin {
				rockchip,pins = <0x2 0xd 0x1 0xbc>;
				phandle = <0x7c>;
			};
		};

		pwm3 {

			pwm3-pin {
				rockchip,pins = <0x0 0x11 0x1 0xbc>;
				phandle = <0x7d>;
			};
		};

		pwm4 {

			pwm4-pin {
				rockchip,pins = <0x3 0x12 0x3 0xbc>;
				phandle = <0x7e>;
			};
		};

		pwm5 {

			pwm5-pin {
				rockchip,pins = <0x3 0x13 0x3 0xbc>;
				phandle = <0x7f>;
			};
		};

		pwm6 {

			pwm6-pin {
				rockchip,pins = <0x3 0x14 0x3 0xbc>;
				phandle = <0x80>;
			};
		};

		pwm7 {

			pwm7-pin {
				rockchip,pins = <0x3 0x15 0x3 0xbc>;
				phandle = <0x81>;
			};
		};

		gmac {

			rmii-pins {
				rockchip,pins = <0x2 0x0 0x2 0xc5 0x2 0x1 0x2 0xc5 0x2 0x2 0x2 0xc5 0x2 0x3 0x2 0xbc 0x2 0x4 0x2 0xbc 0x2 0x5 0x2 0xbc 0x2 0x6 0x2 0xbc 0x2 0x7 0x2 0xbc 0x2 0x9 0x2 0xbc>;
				phandle = <0x8d>;
			};

			mac-refclk-12ma {
				rockchip,pins = <0x2 0xa 0x2 0xc5>;
				phandle = <0x15e>;
			};

			mac-refclk {
				rockchip,pins = <0x2 0xa 0x2 0xbc>;
				phandle = <0x8e>;
			};
		};

		cif-m0 {

			cif-clkout-m0 {
				rockchip,pins = <0x2 0xb 0x1 0xc5>;
				phandle = <0xad>;
			};

			dvp-d2d9-m0 {
				rockchip,pins = <0x2 0x0 0x1 0xbc 0x2 0x1 0x1 0xbc 0x2 0x2 0x1 0xbc 0x2 0x3 0x1 0xbc 0x2 0x4 0x1 0xbc 0x2 0x5 0x1 0xbc 0x2 0x6 0x1 0xbc 0x2 0x7 0x1 0xbc 0x2 0x8 0x1 0xbc 0x2 0x9 0x1 0xbc 0x2 0xa 0x1 0xbc 0x2 0xb 0x1 0xbc>;
				phandle = <0xab>;
			};

			dvp-d0d1-m0 {
				rockchip,pins = <0x2 0xc 0x1 0xbc 0x2 0xe 0x1 0xbc>;
				phandle = <0xaf>;
			};

			d10-d11-m0 {
				rockchip,pins = <0x2 0xf 0x1 0xbc 0x2 0x10 0x1 0xbc>;
				phandle = <0xae>;
			};
		};

		cif-m1 {

			cif-clkout-m1 {
				rockchip,pins = <0x3 0x18 0x3 0xbc>;
				phandle = <0x15f>;
			};

			dvp-d2d9-m1 {
				rockchip,pins = <0x3 0x3 0x3 0xbc 0x3 0x5 0x3 0xbc 0x3 0x7 0x3 0xbc 0x3 0x8 0x3 0xbc 0x3 0x9 0x3 0xbc 0x3 0xc 0x3 0xbc 0x3 0xe 0x3 0xbc 0x3 0xf 0x3 0xbc 0x3 0x19 0x3 0xbc 0x3 0x1a 0x3 0xbc 0x3 0x1b 0x3 0xbc 0x3 0x18 0x3 0xbc>;
				phandle = <0x160>;
			};

			dvp-d0d1-m1 {
				rockchip,pins = <0x3 0x1 0x3 0xbc 0x3 0x2 0x3 0xbc>;
				phandle = <0x161>;
			};

			d10-d11-m1 {
				rockchip,pins = <0x3 0x16 0x3 0xbc 0x3 0x17 0x3 0xbc>;
				phandle = <0x162>;
			};
		};

		isp {

			isp-prelight {
				rockchip,pins = <0x3 0x19 0x4 0xbc>;
				phandle = <0x163>;
			};
		};

		pmic {

			pmic_int {
				rockchip,pins = <0x0 0x7 0x0 0xbd>;
				phandle = <0x5d>;
			};

			soc_slppin_gpio {
				rockchip,pins = <0x0 0x4 0x0 0xc6>;
				phandle = <0x60>;
			};

			soc_slppin_slp {
				rockchip,pins = <0x0 0x4 0x1 0xbc>;
				phandle = <0x5e>;
			};

			soc_slppin_rst {
				rockchip,pins = <0x0 0x4 0x2 0xbc>;
				phandle = <0x62>;
			};
		};

		usb2 {

			host-vbus-drv {
				rockchip,pins = <0x0 0x0 0x0 0xbc>;
				phandle = <0xcb>;
			};
		};
	};

	pcfg-for-s {

		pcfg-pull-none-n-4ma {
			bias-disable;
			drive-strength-s = <0x4>;
			phandle = <0x164>;
		};

		pcfg-pull-up-n-4ma {
			bias-pull-up;
			drive-strength-s = <0x4>;
			phandle = <0x165>;
		};

		pcfg-pull-down-n-4ma {
			bias-pull-down;
			drive-strength-s = <0x4>;
			phandle = <0x166>;
		};

		pcfg-pull-none-0-6ma {
			bias-disable;
			drive-strength-s = <0x6>;
			phandle = <0x167>;
		};

		pcfg-pull-up-0-6ma {
			bias-pull-up;
			drive-strength-s = <0x6>;
			phandle = <0x168>;
		};

		pcfg-pull-down-0-6ma {
			bias-pull-down;
			drive-strength-s = <0x6>;
			phandle = <0x169>;
		};

		pcfg-pull-none-4-6ma {
			bias-disable;
			drive-strength = <0x4>;
			drive-strength-s = <0x6>;
			phandle = <0x16a>;
		};

		pcfg-pull-up-4-6ma {
			bias-pull-up;
			drive-strength = <0x4>;
			drive-strength-s = <0x6>;
			phandle = <0x16b>;
		};

		pcfg-pull-down-4-6ma {
			bias-pull-down;
			drive-strength = <0x4>;
			drive-strength-s = <0x6>;
			phandle = <0x16c>;
		};

		pcfg-pull-none-8-6ma {
			bias-disable;
			drive-strength = <0x8>;
			drive-strength-s = <0x6>;
			phandle = <0xc2>;
		};

		pcfg-pull-up-8-6ma {
			bias-pull-up;
			drive-strength = <0x8>;
			drive-strength-s = <0x6>;
			phandle = <0xc3>;
		};

		pcfg-pull-down-8-6ma {
			bias-pull-down;
			drive-strength = <0x8>;
			drive-strength-s = <0x6>;
			phandle = <0x16d>;
		};

		pcfg-pull-none-8-4ma {
			bias-disable;
			drive-strength = <0x8>;
			drive-strength-s = <0x4>;
			phandle = <0x16e>;
		};

		pcfg-pull-up-8-4ma {
			bias-pull-up;
			drive-strength = <0x8>;
			drive-strength-s = <0x4>;
			phandle = <0x16f>;
		};

		pcfg-pull-down-8-4ma {
			bias-pull-down;
			drive-strength = <0x8>;
			drive-strength-s = <0x4>;
			phandle = <0x170>;
		};

		pcfg-pull-none-12-4ma {
			bias-disable;
			drive-strength = <0xc>;
			drive-strength-s = <0x4>;
			phandle = <0x171>;
		};

		pcfg-pull-up-12-4ma {
			bias-pull-up;
			drive-strength = <0xc>;
			drive-strength-s = <0x4>;
			phandle = <0x172>;
		};

		pcfg-pull-down-12-4ma {
			bias-pull-down;
			drive-strength = <0xc>;
			drive-strength-s = <0x4>;
			phandle = <0x173>;
		};

		pcfg-pull-none-12-6ma {
			bias-disable;
			drive-strength = <0xc>;
			drive-strength-s = <0x6>;
			phandle = <0x174>;
		};

		pcfg-pull-up-12-6ma {
			bias-pull-up;
			drive-strength = <0xc>;
			drive-strength-s = <0x6>;
			phandle = <0x175>;
		};

		pcfg-pull-down-12-6ma {
			bias-pull-down;
			drive-strength = <0xc>;
			drive-strength-s = <0x6>;
			phandle = <0x176>;
		};
	};

	chosen {
		bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootwait";
	};

	fiq-debugger {
		compatible = "rockchip,fiq-debugger";
		rockchip,serial-id = <0x2>;
		rockchip,wake-irq = <0x0>;
		rockchip,irq-mode-enable = <0x0>;
		rockchip,baudrate = <0x16e360>;
		interrupts = <0x0 0x7f 0x8>;
		pinctrl-names = "default";
		pinctrl-0 = <0x53>;
		status = "okay";
	};

	reserved-memory {
		#address-cells = <0x2>;
		#size-cells = <0x2>;
		ranges;

		drm-logo@00000000 {
			compatible = "rockchip,drm-logo";
			reg = <0x0 0x0 0x0 0x0>;
			phandle = <0x12>;
		};
	};

	adc-keys {
		compatible = "adc-keys";
		io-channels = <0xc7 0x2>;
		io-channel-names = "buttons";
		poll-interval = <0x64>;
		keyup-threshold-microvolt = <0x1b7740>;

		esc-key {
			linux,code = <0x1>;
			label = "esc";
			press-threshold-microvolt = <0x13fd30>;
		};

		home-key {
			linux,code = <0x66>;
			label = "home";
			press-threshold-microvolt = <0x98580>;
		};

		menu-key {
			linux,code = <0x8b>;
			label = "menu";
			press-threshold-microvolt = <0xf0f78>;
		};

		vol-down-key {
			linux,code = <0x72>;
			label = "volume down";
			press-threshold-microvolt = <0x493e0>;
		};

		vol-up-key {
			linux,code = <0x73>;
			label = "volume up";
			press-threshold-microvolt = <0x4268>;
		};
	};

	backlight {
		compatible = "pwm-backlight";
		pwms = <0xc8 0x0 0x61a8 0x0>;
		brightness-levels = <0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3a 0x3b 0x3c 0x3d 0x3e 0x3f 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4a 0x4b 0x4c 0x4d 0x4e 0x4f 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5a 0x5b 0x5c 0x5d 0x5e 0x5f 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6a 0x6b 0x6c 0x6d 0x6e 0x6f 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7a 0x7b 0x7c 0x7d 0x7e 0x7f 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8a 0x8b 0x8c 0x8d 0x8e 0x8f 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9a 0x9b 0x9c 0x9d 0x9e 0x9f 0xa0 0xa1 0xa2 0xa3 0xa4 0xa5 0xa6 0xa7 0xa8 0xa9 0xaa 0xab 0xac 0xad 0xae 0xaf 0xb0 0xb1 0xb2 0xb3 0xb4 0xb5 0xb6 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 0xc1 0xc2 0xc3 0xc4 0xc5 0xc6 0xc7 0xc8 0xc9 0xca 0xcb 0xcc 0xcd 0xce 0xcf 0xd0 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 0xd8 0xd9 0xda 0xdb 0xdc 0xdd 0xde 0xdf 0xe0 0xe1 0xe2 0xe3 0xe4 0xe5 0xe6 0xe7 0xe8 0xe9 0xea 0xeb 0xec 0xed 0xee 0xef 0xf0 0xf1 0xf2 0xf3 0xf4 0xf5 0xf6 0xf7 0xf8 0xf9 0xfa 0xfb 0xfc 0xfd 0xfe 0xff>;
		default-brightness-level = <0x64>;
		phandle = <0xa0>;
	};

	rk809-sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,name = "rockchip,rk809-codec";
		simple-audio-card,mclk-fs = <0x100>;
		simple-audio-card,widgets = "Microphone", "Mic Jack", "Headphone", "Headphone Jack";
		simple-audio-card,routing = "Mic Jack", "MICBIAS1", "IN1P", "Mic Jack", "Headphone Jack", "HPOL", "Headphone Jack", "HPOR";

		simple-audio-card,cpu {
			sound-dai = <0xc9>;
		};

		simple-audio-card,codec {
			sound-dai = <0xca>;
		};
	};

	vcc-phy-regulator {
		compatible = "regulator-fixed";
		regulator-name = "vcc_phy";
		regulator-always-on;
		regulator-boot-on;
		phandle = <0x8f>;
	};

	vccsys {
		compatible = "regulator-fixed";
		regulator-name = "vcc5v0_sys";
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <0x4c4b40>;
		regulator-max-microvolt = <0x4c4b40>;
		phandle = <0x64>;
	};

	vcc5v0-host-regulator {
		compatible = "regulator-fixed";
		gpio = <0x5c 0x0 0x1>;
		enable-active-low;
		pinctrl-names = "default";
		pinctrl-0 = <0xcb>;
		regulator-name = "vcc5v0_host";
		regulator-always-on;
		phandle = <0x89>;
	};

	vcc5v0-usb-regulator {
		compatible = "regulator-fixed";
		gpio = <0xcc 0x1f 0x0>;
		enable-active-high;
		pinctrl-names = "default";
		regulator-name = "vcc5v_usb";
		regulator-always-on;
		phandle = <0x177>;
	};

	vcc3v3_wifi-rst {
		compatible = "regulator-fixed";
		gpio = <0xcc 0x13 0x0>;
		enable-active-high;
		pinctrl-names = "default";
		regulator-name = "vcc3v3_wifi-rst";
		regulator-always-on;
		phandle = <0x178>;
	};

	vcc3v3_wifi-en {
		compatible = "regulator-fixed";
		gpio = <0x67 0x8 0x0>;
		enable-active-high;
		pinctrl-names = "default";
		regulator-name = "vcc3v3_wifi_en";
		regulator-always-on;
		phandle = <0x179>;
	};

	__symbols__ {
		ddr_timing = "/ddr_timing";
		ddr3_params = "/ddr3-params";
		ddr4_params = "/ddr4-params";
		lpddr2_params = "/lpddr2-params";
		lpddr3_params = "/lpddr3-params";
		lpddr4_params = "/lpddr4-params";
		cpu0 = "/cpus/cpu@0";
		cpu1 = "/cpus/cpu@1";
		cpu2 = "/cpus/cpu@2";
		cpu3 = "/cpus/cpu@3";
		CPU_SLEEP = "/cpus/idle-states/cpu-sleep";
		CLUSTER_SLEEP = "/cpus/idle-states/cluster-sleep";
		cpu0_opp_table = "/cpu0-opp-table";
		px30s_cpu0_opp_table = "/px30s-cpu0-opp-table";
		bus_apll = "/bus-apll";
		bus_apll_opp_table = "/bus-apll-opp-table";
		display_subsystem = "/display-subsystem";
		route_lvds = "/display-subsystem/route/route-lvds";
		route_dsi = "/display-subsystem/route/route-dsi";
		route_rgb = "/display-subsystem/route/route-rgb";
		optee = "/firmware/optee";
		scmi = "/firmware/scmi";
		scmi_clk = "/firmware/scmi/protocol@14";
		sdei = "/firmware/sdei";
		gmac_clkin = "/external-gmac-clock";
		rockchip_suspend = "/rockchip-suspend";
		xin24m = "/xin24m";
		xin32k = "/xin32k";
		scmi_shmem = "/scmi-shmem@10f000";
		pmu = "/power-management@ff000000";
		power = "/power-management@ff000000/power-controller";
		pmugrf = "/syscon@ff010000";
		pmu_io_domains = "/syscon@ff010000/io-domains";
		reboot_mode = "/syscon@ff010000/reboot-mode";
		pmu_pvtm = "/syscon@ff010000/pmu-pvtm";
		uart0 = "/serial@ff030000";
		i2s0_8ch = "/i2s@ff060000";
		i2s1_2ch = "/i2s@ff070000";
		i2s2_2ch = "/i2s@ff080000";
		pdm = "/pdm@ff0a0000";
		crypto = "/crypto@ff0b0000";
		rng = "/rng@ff0b0000";
		gic = "/interrupt-controller@ff131000";
		grf = "/syscon@ff140000";
		io_domains = "/syscon@ff140000/io-domains";
		lvds = "/syscon@ff140000/lvds";
		lvds_in_vopb = "/syscon@ff140000/lvds/ports/port@0/endpoint@0";
		lvds_in_vopl = "/syscon@ff140000/lvds/ports/port@0/endpoint@1";
		rgb = "/syscon@ff140000/rgb";
		rgb_in_vopb = "/syscon@ff140000/rgb/ports/port@0/endpoint@0";
		rgb_in_vopl = "/syscon@ff140000/rgb/ports/port@0/endpoint@1";
		core_grf = "/syscon@ff148000";
		pvtm = "/syscon@ff148000/pvtm";
		uart1 = "/serial@ff158000";
		uart2 = "/serial@ff160000";
		uart3 = "/serial@ff168000";
		uart4 = "/serial@ff170000";
		uart5 = "/serial@ff178000";
		i2c0 = "/i2c@ff180000";
		rk809 = "/i2c@ff180000/pmic@20";
		pinctrl_rk8xx = "/i2c@ff180000/pmic@20/pinctrl_rk8xx";
		rk817_slppin_null = "/i2c@ff180000/pmic@20/pinctrl_rk8xx/rk817_slppin_null";
		rk817_slppin_slp = "/i2c@ff180000/pmic@20/pinctrl_rk8xx/rk817_slppin_slp";
		rk817_slppin_pwrdn = "/i2c@ff180000/pmic@20/pinctrl_rk8xx/rk817_slppin_pwrdn";
		rk817_slppin_rst = "/i2c@ff180000/pmic@20/pinctrl_rk8xx/rk817_slppin_rst";
		vdd_logic = "/i2c@ff180000/pmic@20/regulators/DCDC_REG1";
		vdd_arm = "/i2c@ff180000/pmic@20/regulators/DCDC_REG2";
		vcc_ddr = "/i2c@ff180000/pmic@20/regulators/DCDC_REG3";
		vcc_3v0 = "/i2c@ff180000/pmic@20/regulators/DCDC_REG4";
		vcc_1v0 = "/i2c@ff180000/pmic@20/regulators/LDO_REG1";
		vcc1v8_soc = "/i2c@ff180000/pmic@20/regulators/LDO_REG2";
		vdd1v0_soc = "/i2c@ff180000/pmic@20/regulators/LDO_REG3";
		vcc3v0_pmu = "/i2c@ff180000/pmic@20/regulators/LDO_REG4";
		vccio_sd = "/i2c@ff180000/pmic@20/regulators/LDO_REG5";
		vcc_sd = "/i2c@ff180000/pmic@20/regulators/LDO_REG6";
		vcc2v8_dvp = "/i2c@ff180000/pmic@20/regulators/LDO_REG7";
		vcc1v8_dvp = "/i2c@ff180000/pmic@20/regulators/LDO_REG8";
		vdd1v5_dvp = "/i2c@ff180000/pmic@20/regulators/LDO_REG9";
		vcc3v3_sys = "/i2c@ff180000/pmic@20/regulators/DCDC_REG5";
		vcc3v3_lcd = "/i2c@ff180000/pmic@20/regulators/SWITCH_REG2";
		rk809_codec = "/i2c@ff180000/pmic@20/codec";
		i2c1 = "/i2c@ff190000";
		rtc = "/i2c@ff190000/rtc@51";
		i2c2 = "/i2c@ff1a0000";
		i2c3 = "/i2c@ff1b0000";
		spi0 = "/spi@ff1d0000";
		spi1 = "/spi@ff1d8000";
		wdt = "/watchdog@ff1e0000";
		pwm0 = "/pwm@ff200000";
		pwm1 = "/pwm@ff200010";
		pwm2 = "/pwm@ff200020";
		pwm3 = "/pwm@ff200030";
		pwm4 = "/pwm@ff208000";
		pwm5 = "/pwm@ff208010";
		pwm6 = "/pwm@ff208020";
		pwm7 = "/pwm@ff208030";
		rktimer = "/rktimer@ff210000";
		dmac = "/amba/dmac@ff240000";
		thermal_zones = "/thermal-zones";
		soc_thermal = "/thermal-zones/soc-thermal";
		threshold = "/thermal-zones/soc-thermal/trips/trip-point-0";
		target = "/thermal-zones/soc-thermal/trips/trip-point-1";
		soc_crit = "/thermal-zones/soc-thermal/trips/soc-crit";
		gpu_thermal = "/thermal-zones/gpu-thermal";
		tsadc = "/tsadc@ff280000";
		saradc = "/saradc@ff288000";
		otp = "/otp@ff290000";
		otp_id = "/otp@ff290000/id@7";
		cpu_leakage = "/otp@ff290000/cpu-leakage@17";
		performance = "/otp@ff290000/performance@1e";
		cru = "/clock-controller@ff2b0000";
		cpu_boost = "/cpu-boost@ff2b8000";
		pmucru = "/pmu-clock-controller@ff2bc000";
		usb2phy_grf = "/syscon@ff2c0000";
		u2phy = "/syscon@ff2c0000/usb2-phy@100";
		u2phy_host = "/syscon@ff2c0000/usb2-phy@100/host-port";
		u2phy_otg = "/syscon@ff2c0000/usb2-phy@100/otg-port";
		video_phy = "/video-phy@ff2e0000";
		mipi_dphy_rx0 = "/mipi-dphy-rx0@ff2f0000";
		usb20_otg = "/usb@ff300000";
		usb_host0_ehci = "/usb@ff340000";
		usb_host0_ohci = "/usb@ff350000";
		gmac = "/ethernet@ff360000";
		sdmmc = "/dwmmc@ff370000";
		sdio = "/dwmmc@ff380000";
		emmc = "/dwmmc@ff390000";
		nandc0 = "/nandc@ff3b0000";
		gpu = "/gpu@ff400000";
		gpu_opp_table = "/gpu-opp-table";
		px30s_gpu_opp_table = "/px30s-gpu-opp-table";
		mpp_srv = "/mpp-srv";
		vdpu = "/vdpu@ff442400";
		vpu_mmu = "/iommu@ff442800";
		vepu = "/vepu@ff442000";
		hevc = "/hevc@ff440000";
		hevc_mmu = "/iommu@ff440440";
		dsi = "/dsi@ff450000";
		dsi_in_vopb = "/dsi@ff450000/ports/port@0/endpoint@0";
		dsi_in_vopl = "/dsi@ff450000/ports/port@0/endpoint@1";
		dsi_out_panel = "/dsi@ff450000/ports/port@1/endpoint";
		timing1 = "/dsi@ff450000/panel@0/display-timings/timing1";
		panel_in_dsi = "/dsi@ff450000/panel@0/ports/port@0/endpoint";
		vopb = "/vop@ff460000";
		vopb_out = "/vop@ff460000/port";
		vopb_out_lvds = "/vop@ff460000/port/endpoint@0";
		vopb_out_dsi = "/vop@ff460000/port/endpoint@1";
		vopb_out_rgb = "/vop@ff460000/port/endpoint@2";
		vopb_mmu = "/iommu@ff460f00";
		vopl = "/vop@ff470000";
		vopl_out = "/vop@ff470000/port";
		vopl_out_lvds = "/vop@ff470000/port/endpoint@0";
		vopl_out_dsi = "/vop@ff470000/port/endpoint@1";
		vopl_out_rgb = "/vop@ff470000/port/endpoint@2";
		vopl_mmu = "/iommu@ff470f00";
		rk_rga = "/rk_rga@ff480000";
		cif = "/cif@ff490000";
		cif_new = "/cif-new@ff490000";
		vip_mmu = "/iommu@ff490800";
		rk_isp = "/rk_isp@ff4a0000";
		rkisp1 = "/rkisp1@ff4a0000";
		isp_mmu = "/iommu@ff4a8000";
		qos_gmac = "/qos@ff518000";
		qos_gpu = "/qos@ff520000";
		qos_sdmmc = "/qos@ff52c000";
		qos_emmc = "/qos@ff538000";
		qos_nand = "/qos@ff538080";
		qos_sdio = "/qos@ff538100";
		qos_sfc = "/qos@ff538180";
		qos_usb_host = "/qos@ff540000";
		qos_usb_otg = "/qos@ff540080";
		qos_isp_128 = "/qos@ff548000";
		qos_isp_rd = "/qos@ff548080";
		qos_isp_wr = "/qos@ff548100";
		qos_isp_m1 = "/qos@ff548180";
		qos_vip = "/qos@ff548200";
		qos_rga_rd = "/qos@ff550000";
		qos_rga_wr = "/qos@ff550080";
		qos_vop_m0 = "/qos@ff550100";
		qos_vop_m1 = "/qos@ff550180";
		qos_vpu = "/qos@ff558000";
		qos_vpu_r128 = "/qos@ff558080";
		dfi = "/dfi@ff610000";
		dmc = "/dmc";
		ddr_power_model = "/dmc/ddr_power_model";
		dmc_fsp = "/dmc-fsp";
		dmc_opp_table = "/dmc-opp-table";
		px30s_dmc_opp_table = "/px30s-dmc-opp-table";
		dmcdbg = "/dmcdbg";
		rockchip_system_monitor = "/rockchip-system-monitor";
		pinctrl = "/pinctrl";
		gpio0 = "/pinctrl/gpio0@ff040000";
		gpio1 = "/pinctrl/gpio1@ff250000";
		gpio2 = "/pinctrl/gpio2@ff260000";
		gpio3 = "/pinctrl/gpio3@ff270000";
		pcfg_pull_up = "/pinctrl/pcfg-pull-up";
		pcfg_pull_down = "/pinctrl/pcfg-pull-down";
		pcfg_pull_none = "/pinctrl/pcfg-pull-none";
		pcfg_pull_none_2ma = "/pinctrl/pcfg-pull-none-2ma";
		pcfg_pull_up_2ma = "/pinctrl/pcfg-pull-up-2ma";
		pcfg_pull_up_4ma = "/pinctrl/pcfg-pull-up-4ma";
		pcfg_pull_none_4ma = "/pinctrl/pcfg-pull-none-4ma";
		pcfg_pull_down_4ma = "/pinctrl/pcfg-pull-down-4ma";
		pcfg_pull_none_8ma = "/pinctrl/pcfg-pull-none-8ma";
		pcfg_pull_up_8ma = "/pinctrl/pcfg-pull-up-8ma";
		pcfg_pull_none_12ma = "/pinctrl/pcfg-pull-none-12ma";
		pcfg_pull_up_12ma = "/pinctrl/pcfg-pull-up-12ma";
		pcfg_pull_none_smt = "/pinctrl/pcfg-pull-none-smt";
		pcfg_output_high = "/pinctrl/pcfg-output-high";
		pcfg_output_low = "/pinctrl/pcfg-output-low";
		pcfg_input_high = "/pinctrl/pcfg-input-high";
		pcfg_input = "/pinctrl/pcfg-input";
		i2c0_xfer = "/pinctrl/i2c0/i2c0-xfer";
		i2c1_xfer = "/pinctrl/i2c1/i2c1-xfer";
		i2c2_xfer = "/pinctrl/i2c2/i2c2-xfer";
		i2c3_xfer = "/pinctrl/i2c3/i2c3-xfer";
		tsadc_otp_gpio = "/pinctrl/tsadc/tsadc-otp-gpio";
		tsadc_otp_out = "/pinctrl/tsadc/tsadc-otp-out";
		uart0_xfer = "/pinctrl/uart0/uart0-xfer";
		uart0_cts = "/pinctrl/uart0/uart0-cts";
		uart0_rts = "/pinctrl/uart0/uart0-rts";
		uart0_rts_gpio = "/pinctrl/uart0/uart0-rts-gpio";
		uart1_xfer = "/pinctrl/uart1/uart1-xfer";
		uart1_cts = "/pinctrl/uart1/uart1-cts";
		uart1_rts = "/pinctrl/uart1/uart1-rts";
		uart1_rts_gpio = "/pinctrl/uart1/uart1-rts-gpio";
		uart2m0_xfer = "/pinctrl/uart2-m0/uart2m0-xfer";
		uart2m1_xfer = "/pinctrl/uart2-m1/uart2m1-xfer";
		uart3m0_xfer = "/pinctrl/uart3-m0/uart3m0-xfer";
		uart3m0_cts = "/pinctrl/uart3-m0/uart3m0-cts";
		uart3m0_rts = "/pinctrl/uart3-m0/uart3m0-rts";
		uart3m0_rts_gpio = "/pinctrl/uart3-m0/uart3m0-rts-gpio";
		uart3m1_xfer = "/pinctrl/uart3-m1/uart3m1-xfer";
		uart3m1_cts = "/pinctrl/uart3-m1/uart3m1-cts";
		uart3m1_rts = "/pinctrl/uart3-m1/uart3m1-rts";
		uart3m1_rts_gpio = "/pinctrl/uart3-m1/uart3m1-rts-gpio";
		uart4_xfer = "/pinctrl/uart4/uart4-xfer";
		uart4_cts = "/pinctrl/uart4/uart4-cts";
		uart4_rts = "/pinctrl/uart4/uart4-rts";
		uart5_xfer = "/pinctrl/uart5/uart5-xfer";
		uart5_cts = "/pinctrl/uart5/uart5-cts";
		uart5_rts = "/pinctrl/uart5/uart5-rts";
		spi0_clk = "/pinctrl/spi0/spi0-clk";
		spi0_csn = "/pinctrl/spi0/spi0-csn";
		spi0_miso = "/pinctrl/spi0/spi0-miso";
		spi0_mosi = "/pinctrl/spi0/spi0-mosi";
		spi0_clk_hs = "/pinctrl/spi0/spi0-clk-hs";
		spi0_miso_hs = "/pinctrl/spi0/spi0-miso-hs";
		spi0_mosi_hs = "/pinctrl/spi0/spi0-mosi-hs";
		spi1_clk = "/pinctrl/spi1/spi1-clk";
		spi1_csn0 = "/pinctrl/spi1/spi1-csn0";
		spi1_csn1 = "/pinctrl/spi1/spi1-csn1";
		spi1_miso = "/pinctrl/spi1/spi1-miso";
		spi1_mosi = "/pinctrl/spi1/spi1-mosi";
		spi1_clk_hs = "/pinctrl/spi1/spi1-clk-hs";
		spi1_miso_hs = "/pinctrl/spi1/spi1-miso-hs";
		spi1_mosi_hs = "/pinctrl/spi1/spi1-mosi-hs";
		pdm_clk0m0 = "/pinctrl/pdm/pdm-clk0m0";
		pdm_clk0m1 = "/pinctrl/pdm/pdm-clk0m1";
		pdm_clk1 = "/pinctrl/pdm/pdm-clk1";
		pdm_sdi0m0 = "/pinctrl/pdm/pdm-sdi0m0";
		pdm_sdi0m1 = "/pinctrl/pdm/pdm-sdi0m1";
		pdm_sdi1 = "/pinctrl/pdm/pdm-sdi1";
		pdm_sdi2 = "/pinctrl/pdm/pdm-sdi2";
		pdm_sdi3 = "/pinctrl/pdm/pdm-sdi3";
		pdm_clk0m0_sleep = "/pinctrl/pdm/pdm-clk0m0-sleep";
		pdm_clk0m_sleep1 = "/pinctrl/pdm/pdm-clk0m1-sleep";
		pdm_clk1_sleep = "/pinctrl/pdm/pdm-clk1-sleep";
		pdm_sdi0m0_sleep = "/pinctrl/pdm/pdm-sdi0m0-sleep";
		pdm_sdi0m1_sleep = "/pinctrl/pdm/pdm-sdi0m1-sleep";
		pdm_sdi1_sleep = "/pinctrl/pdm/pdm-sdi1-sleep";
		pdm_sdi2_sleep = "/pinctrl/pdm/pdm-sdi2-sleep";
		pdm_sdi3_sleep = "/pinctrl/pdm/pdm-sdi3-sleep";
		i2s0_8ch_mclk = "/pinctrl/i2s0/i2s0-8ch-mclk";
		i2s0_8ch_sclktx = "/pinctrl/i2s0/i2s0-8ch-sclktx";
		i2s0_8ch_sclkrx = "/pinctrl/i2s0/i2s0-8ch-sclkrx";
		i2s0_8ch_lrcktx = "/pinctrl/i2s0/i2s0-8ch-lrcktx";
		i2s0_8ch_lrckrx = "/pinctrl/i2s0/i2s0-8ch-lrckrx";
		i2s0_8ch_sdo0 = "/pinctrl/i2s0/i2s0-8ch-sdo0";
		i2s0_8ch_sdo1 = "/pinctrl/i2s0/i2s0-8ch-sdo1";
		i2s0_8ch_sdo2 = "/pinctrl/i2s0/i2s0-8ch-sdo2";
		i2s0_8ch_sdo3 = "/pinctrl/i2s0/i2s0-8ch-sdo3";
		i2s0_8ch_sdi0 = "/pinctrl/i2s0/i2s0-8ch-sdi0";
		i2s0_8ch_sdi1 = "/pinctrl/i2s0/i2s0-8ch-sdi1";
		i2s0_8ch_sdi2 = "/pinctrl/i2s0/i2s0-8ch-sdi2";
		i2s0_8ch_sdi3 = "/pinctrl/i2s0/i2s0-8ch-sdi3";
		i2s1_2ch_mclk = "/pinctrl/i2s1/i2s1-2ch-mclk";
		i2s1_2ch_sclk = "/pinctrl/i2s1/i2s1-2ch-sclk";
		i2s1_2ch_lrck = "/pinctrl/i2s1/i2s1-2ch-lrck";
		i2s1_2ch_sdi = "/pinctrl/i2s1/i2s1-2ch-sdi";
		i2s1_2ch_sdo = "/pinctrl/i2s1/i2s1-2ch-sdo";
		i2s2_2ch_mclk = "/pinctrl/i2s2/i2s2-2ch-mclk";
		i2s2_2ch_sclk = "/pinctrl/i2s2/i2s2-2ch-sclk";
		i2s2_2ch_lrck = "/pinctrl/i2s2/i2s2-2ch-lrck";
		i2s2_2ch_sdi = "/pinctrl/i2s2/i2s2-2ch-sdi";
		i2s2_2ch_sdo = "/pinctrl/i2s2/i2s2-2ch-sdo";
		sdmmc_clk = "/pinctrl/sdmmc/sdmmc-clk";
		sdmmc_cmd = "/pinctrl/sdmmc/sdmmc-cmd";
		sdmmc_det = "/pinctrl/sdmmc/sdmmc-det";
		sdmmc_bus1 = "/pinctrl/sdmmc/sdmmc-bus1";
		sdmmc_bus4 = "/pinctrl/sdmmc/sdmmc-bus4";
		sdmmc_gpio = "/pinctrl/sdmmc/sdmmc-gpio";
		sdio_clk = "/pinctrl/sdio/sdio-clk";
		sdio_cmd = "/pinctrl/sdio/sdio-cmd";
		sdio_bus4 = "/pinctrl/sdio/sdio-bus4";
		sdio_gpio = "/pinctrl/sdio/sdio-gpio";
		emmc_clk = "/pinctrl/emmc/emmc-clk";
		emmc_cmd = "/pinctrl/emmc/emmc-cmd";
		emmc_pwren = "/pinctrl/emmc/emmc-pwren";
		emmc_rstnout = "/pinctrl/emmc/emmc-rstnout";
		emmc_bus1 = "/pinctrl/emmc/emmc-bus1";
		emmc_bus4 = "/pinctrl/emmc/emmc-bus4";
		emmc_bus8 = "/pinctrl/emmc/emmc-bus8";
		flash_cs0 = "/pinctrl/flash/flash-cs0";
		flash_rdy = "/pinctrl/flash/flash-rdy";
		flash_dqs = "/pinctrl/flash/flash-dqs";
		flash_ale = "/pinctrl/flash/flash-ale";
		flash_cle = "/pinctrl/flash/flash-cle";
		flash_wrn = "/pinctrl/flash/flash-wrn";
		flash_csl = "/pinctrl/flash/flash-csl";
		flash_rdn = "/pinctrl/flash/flash-rdn";
		flash_bus8 = "/pinctrl/flash/flash-bus8";
		lcdc_m0_rgb_pins = "/pinctrl/lcdc/lcdc-m0-rgb-pins";
		lcdc_m0_sleep_pins = "/pinctrl/lcdc/lcdc-m0-sleep-pins";
		pwm0_pin = "/pinctrl/pwm0/pwm0-pin";
		pwm1_pin = "/pinctrl/pwm1/pwm1-pin";
		pwm2_pin = "/pinctrl/pwm2/pwm2-pin";
		pwm3_pin = "/pinctrl/pwm3/pwm3-pin";
		pwm4_pin = "/pinctrl/pwm4/pwm4-pin";
		pwm5_pin = "/pinctrl/pwm5/pwm5-pin";
		pwm6_pin = "/pinctrl/pwm6/pwm6-pin";
		pwm7_pin = "/pinctrl/pwm7/pwm7-pin";
		rmii_pins = "/pinctrl/gmac/rmii-pins";
		mac_refclk_12ma = "/pinctrl/gmac/mac-refclk-12ma";
		mac_refclk = "/pinctrl/gmac/mac-refclk";
		cif_clkout_m0 = "/pinctrl/cif-m0/cif-clkout-m0";
		dvp_d2d9_m0 = "/pinctrl/cif-m0/dvp-d2d9-m0";
		dvp_d0d1_m0 = "/pinctrl/cif-m0/dvp-d0d1-m0";
		dvp_d10d11_m0 = "/pinctrl/cif-m0/d10-d11-m0";
		cif_clkout_m1 = "/pinctrl/cif-m1/cif-clkout-m1";
		dvp_d2d9_m1 = "/pinctrl/cif-m1/dvp-d2d9-m1";
		dvp_d0d1_m1 = "/pinctrl/cif-m1/dvp-d0d1-m1";
		dvp_d10d11_m1 = "/pinctrl/cif-m1/d10-d11-m1";
		isp_prelight = "/pinctrl/isp/isp-prelight";
		pmic_int = "/pinctrl/pmic/pmic_int";
		soc_slppin_gpio = "/pinctrl/pmic/soc_slppin_gpio";
		soc_slppin_slp = "/pinctrl/pmic/soc_slppin_slp";
		soc_slppin_rst = "/pinctrl/pmic/soc_slppin_rst";
		host_vbus_drv = "/pinctrl/usb2/host-vbus-drv";
		pcfg_pull_none_n_4ma = "/pcfg-for-s/pcfg-pull-none-n-4ma";
		pcfg_pull_up_n_4ma = "/pcfg-for-s/pcfg-pull-up-n-4ma";
		pcfg_pull_down_n_4ma = "/pcfg-for-s/pcfg-pull-down-n-4ma";
		pcfg_pull_none_0_6ma = "/pcfg-for-s/pcfg-pull-none-0-6ma";
		pcfg_pull_up_0_6ma = "/pcfg-for-s/pcfg-pull-up-0-6ma";
		pcfg_pull_down_0_6ma = "/pcfg-for-s/pcfg-pull-down-0-6ma";
		pcfg_pull_none_4_6ma = "/pcfg-for-s/pcfg-pull-none-4-6ma";
		pcfg_pull_up_4_6ma = "/pcfg-for-s/pcfg-pull-up-4-6ma";
		pcfg_pull_down_4_6ma = "/pcfg-for-s/pcfg-pull-down-4-6ma";
		pcfg_pull_none_8_6ma = "/pcfg-for-s/pcfg-pull-none-8-6ma";
		pcfg_pull_up_8_6ma = "/pcfg-for-s/pcfg-pull-up-8-6ma";
		pcfg_pull_down_8_6ma = "/pcfg-for-s/pcfg-pull-down-8-6ma";
		pcfg_pull_none_8_4ma = "/pcfg-for-s/pcfg-pull-none-8-4ma";
		pcfg_pull_up_8_4ma = "/pcfg-for-s/pcfg-pull-up-8-4ma";
		pcfg_pull_down_8_4ma = "/pcfg-for-s/pcfg-pull-down-8-4ma";
		pcfg_pull_none_12_4ma = "/pcfg-for-s/pcfg-pull-none-12-4ma";
		pcfg_pull_up_12_4ma = "/pcfg-for-s/pcfg-pull-up-12-4ma";
		pcfg_pull_down_12_4ma = "/pcfg-for-s/pcfg-pull-down-12-4ma";
		pcfg_pull_none_12_6ma = "/pcfg-for-s/pcfg-pull-none-12-6ma";
		pcfg_pull_up_12_6ma = "/pcfg-for-s/pcfg-pull-up-12-6ma";
		pcfg_pull_down_12_6ma = "/pcfg-for-s/pcfg-pull-down-12-6ma";
		drm_logo = "/reserved-memory/drm-logo@00000000";
		backlight = "/backlight";
		vcc_phy = "/vcc-phy-regulator";
		vcc5v0_sys = "/vccsys";
		vcc5v0_host = "/vcc5v0-host-regulator";
		vcc5v_usb = "/vcc5v0-usb-regulator";
		vcc3v3_wifi_rst = "/vcc3v3_wifi-rst";
		vcc3v3_wifi_en = "/vcc3v3_wifi-en";
	};
};