/*
 * Copyright (C) 2023 walter, Inc.
 * arch/arm64/boot/dts/lcd-mipi6.86-TXW.dtsi
 * Single Chip Driver: ST7703
 * resolution: 480*1280
 * mipi channel: 4 
 */



&dsi {
	status = "okay";
	//status = "disabled";
	//rockchip,lane-rate = <800>;
	panel@0 {
		compatible = "simple-panel-dsi";
		reg = <0>;		
		backlight = <&backlight>;
		prepare-delay-ms = <2>;
		reset-delay-ms = <20>;
		init-delay-ms = <20>;
		enable-delay-ms = <120>;
		disable-delay-ms = <50>;
		unprepare-delay-ms = <20>;

		width-mm = <66>;
		height-mm = <160>;

		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
		dsi,format = <MIPI_DSI_FMT_RGB888>;
		dsi,lanes = <4>;

		panel-init-sequence = [
			15 0A 02 FF 30
			15 00 02 FF 52
			15 00 02 FF 01

			15 00 02 E3 00
			15 00 02 08 0E
			15 00 02 25 0A                  
			15 00 02 28 77//77
			15 00 02 29 04                
			15 00 02 37 9C
			15 00 02 38 A7
			15 00 02 30 58//58//78//38
			15 00 02 45 91//91			 
			15 00 02 A3 58
			15 00 02 2C 03
			15 00 02 C3 0F 
			15 00 02 D6 00    
			15 00 02 39 55//VCOM 
			15 00 02 49 3C
			15 00 02 59 FE   
			15 00 02 80 20//2POWER
			15 00 02 91 67
			15 00 02 92 67
			15 00 02 99 56
			15 00 02 9B 5C                   
			15 00 02 A0 55
			15 00 02 A1 50
			15 00 02 A4 9C
			15 00 02 A7 02
			15 00 02 A8 01
			15 00 02 A9 21
			15 00 02 AA A8
			15 00 02 AB 28
			15 00 02 AC E0
			15 00 02 AD E2
			15 00 02 AE E2
			15 00 02 AF 02
			15 00 02 B0 E2
			15 00 02 B1 26
			15 00 02 B2 28
			15 00 02 B3 28
			15 00 02 B4 22
			15 00 02 B5 E2
			15 00 02 B6 26
			15 00 02 B7 E2
			15 00 02 B8 26
			15 00 02 F6 C0
			15 00 02 F0 00               
			15 00 02 FF 30
			15 00 02 FF 52
			15 00 02 FF 02
			15 00 02 B5 3E
			15 00 02 D5 3C
			15 00 02 B0 08
			15 00 02 D0 0A
			15 00 02 B4 2F
			15 00 02 D4 2C
			15 00 02 B1 0B
			15 00 02 D1 08

			15 00 02 B3 2F
			15 00 02 D3 2D
			15 00 02 B2 05 
			15 00 02 D2 05

			15 00 02 B7 26
			15 00 02 D7 25
			15 00 02 B6 02
			15 00 02 D6 01

			15 00 02 C0 17
			15 00 02 E0 19
			15 00 02 C1 04
			15 00 02 E1 04

			15 00 02 BF 11
			15 00 02 DF 11
			15 00 02 B8 0A
			15 00 02 D8 0A

			15 00 02 BE 19
			15 00 02 DE 19
			15 00 02 B9 00
			15 00 02 D9 01

			15 00 02 BD 0F
			15 00 02 DD 0F
			15 00 02 BA 0E
			15 00 02 DA 0D

			15 00 02 BC 0D
			15 00 02 DC 0B
			15 00 02 BB 0B
			15 00 02 DB 0B          
			15 00 02 FF 30
			15 00 02 FF 52
			15 00 02 FF 03                                
			15 00 02 08 8a
			15 00 02 09 89
			15 00 02 27 06 
			15 00 02 2A 00             
			15 00 02 34 01
			15 00 02 35 00
			15 00 02 36 00
			15 00 02 37 03                 
			15 00 02 40 8a
			15 00 02 41 89
			15 00 02 42 88
			15 00 02 43 87   
			15 00 02 44 44 
			15 00 02 45 fc
			15 00 02 46 fd
			15 00 02 47 54
			15 00 02 48 fe
			15 00 02 49 ff                 
			15 00 02 50 86
			15 00 02 51 85
			15 00 02 52 84
			15 00 02 53 83    
			15 00 02 55 00 
			15 00 02 56 01 
			15 00 02 58 02 
			15 00 02 59 03  
			15 00 02 7E 78 
			15 00 02 80 02
			15 00 02 81 0F
			15 00 02 82 00
			15 00 02 83 0F
			15 00 02 84 0E
			15 00 02 85 0C
			15 00 02 86 0D
			15 00 02 87 07
			15 00 02 88 06  
			15 00 02 89 05  
			15 00 02 8A 04  
			15 00 02 96 02  
			15 00 02 97 0F  
			15 00 02 98 00  
			15 00 02 99 0F  
			15 00 02 9A 0E  
			15 00 02 9B 0C 
			15 00 02 9C 0D //0D
			15 00 02 9D 07  
			15 00 02 9E 06   
			15 00 02 9F 05   
			15 00 02 A0 04    
			15 00 02 FF 30
			15 00 02 FF 52
			15 00 02 FF 00
			15 00 02 36 02			
			//15 00 02 11 00
			//15 00 02 11 00
			//15 78 02 29 00
			//15 05 02 35 00
			
			05 C8 01 11
			05 14 01 29

		];

		display-timings {
			native-mode = <&timing1>;

			timing1: timing1 {
				clock-frequency = <72000000>;
				hactive = <600>;
				vactive = <1280>;
				hfront-porch = <24>;
				hsync-len = <2>;
				hback-porch = <30>;
				vfront-porch = <16>;
				vsync-len = <6>;
				vback-porch = <8>;
				hsync-active = <0>;
				vsync-active = <2>;
				de-active = <0>;
				pixelclk-active = <0>;
				swap-rb=<0>;
				swap-rg=<0>;
				swap-gb=<0>;
			};
		};
		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				panel_in_dsi: endpoint {
					remote-endpoint = <&dsi_out_panel>;
				};
			};
		};
	};
	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@1 {
			reg = <1>;
			dsi_out_panel: endpoint {
				remote-endpoint = <&panel_in_dsi>;
			};
		};
	};
};

&dsi_in_vopb {
	status = "okay";
};

&dsi_in_vopl {
	status = "disabled";
};

&route_dsi {
	connect = <&vopb_out_dsi>;
	status = "okay";
	//status = "disabled";
};