linuxOS_AP05/kernel/arch/arm64/boot/dts/rockchip/lcd-mipi10.1-MX101BA1340.dtsi
2025-06-02 13:59:07 +08:00

296 lines
5.5 KiB
Plaintext
Executable File

/*
* Copyright (C) 2023 walter, Inc.
* arch/arm64/boot/dts/lcd-mipi-MX101BA1340.dtsi
* Single Chip Driver: JD9365
* resolution: 1280*800
* mipi channel: single
*/
&dsi {
status = "okay";
//status = "disabled";
panel@0 {
compatible = "sitronix,st7703", "simple-panel-dsi";
reg = <0>;
power-supply = <&vcc3v3_lcd>;
backlight = <&backlight>;
prepare-delay-ms = <2>;
reset-delay-ms = <1>;
init-delay-ms = <20>;
enable-delay-ms = <120>;
disable-delay-ms = <50>;
unprepare-delay-ms = <20>;
width-mm = <68>;
height-mm = <121>;
dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
dsi,format = <MIPI_DSI_FMT_RGB888>;
dsi,lanes = <4>;
panel-init-sequence = [
15 0A 02 E0 00
15 00 02 E1 93
15 00 02 E2 65
15 00 02 E3 F8
15 00 02 80 03
15 00 02 E0 01
15 00 02 00 00
15 00 02 01 38
15 00 02 0C 74
15 00 02 17 00
15 00 02 18 AF
15 00 02 19 00
15 00 02 1A 00
15 00 02 1B AF
15 00 02 1C 00
15 00 02 35 26
15 00 02 37 09
15 00 02 38 04
15 00 02 39 00
15 00 02 3A 01
15 00 02 3C 78
15 00 02 3D FF
15 00 02 3E FF
15 00 02 3F 7F
15 00 02 40 06
15 00 02 41 A0
15 00 02 42 81
15 00 02 43 14
15 00 02 44 23
15 00 02 45 28
15 00 02 55 02
15 00 02 57 69
15 00 02 59 0A
15 00 02 5A 2A
15 00 02 5B 17
15 00 02 5D 7F
15 00 02 5E 6A
15 00 02 5F 5B
15 00 02 60 4F
15 00 02 61 4A
15 00 02 62 3D
15 00 02 63 41
15 00 02 64 2A
15 00 02 65 44
15 00 02 66 43
15 00 02 67 44
15 00 02 68 62
15 00 02 69 52
15 00 02 6A 59
15 00 02 6B 4C
15 00 02 6C 48
15 00 02 6D 3A
15 00 02 6E 26
15 00 02 6F 00
15 00 02 70 7F
15 00 02 71 6A
15 00 02 72 5B
15 00 02 73 4F
15 00 02 74 4A
15 00 02 75 3D
15 00 02 76 41
15 00 02 77 2A
15 00 02 78 44
15 00 02 79 43
15 00 02 7A 44
15 00 02 7B 62
15 00 02 7C 52
15 00 02 7D 59
15 00 02 7E 4C
15 00 02 7F 48
15 00 02 80 3A
15 00 02 81 26
15 00 02 82 00
15 00 02 E0 02
15 00 02 00 02
15 00 02 01 02
15 00 02 02 00
15 00 02 03 00
15 00 02 04 1E
15 00 02 05 1E
15 00 02 06 1F
15 00 02 07 1F
15 00 02 08 1F
15 00 02 09 17
15 00 02 0A 17
15 00 02 0B 37
15 00 02 0C 37
15 00 02 0D 47
15 00 02 0E 47
15 00 02 0F 45
15 00 02 10 45
15 00 02 11 4B
15 00 02 12 4B
15 00 02 13 49
15 00 02 14 49
15 00 02 15 1F
15 00 02 16 01
15 00 02 17 01
15 00 02 18 00
15 00 02 19 00
15 00 02 1A 1E
15 00 02 1B 1E
15 00 02 1C 1F
15 00 02 1D 1F
15 00 02 1E 1F
15 00 02 1F 17
15 00 02 20 17
15 00 02 21 37
15 00 02 22 37
15 00 02 23 46
15 00 02 24 46
15 00 02 25 44
15 00 02 26 44
15 00 02 27 4A
15 00 02 28 4A
15 00 02 29 48
15 00 02 2A 48
15 00 02 2B 1F
15 00 02 2C 01
15 00 02 2D 01
15 00 02 2E 00
15 00 02 2F 00
15 00 02 30 1F
15 00 02 31 1F
15 00 02 32 1E
15 00 02 33 1E
15 00 02 34 1F
15 00 02 35 17
15 00 02 36 17
15 00 02 37 37
15 00 02 38 37
15 00 02 39 08
15 00 02 3A 08
15 00 02 3B 0A
15 00 02 3C 0A
15 00 02 3D 04
15 00 02 3E 04
15 00 02 3F 06
15 00 02 40 06
15 00 02 41 1F
15 00 02 42 02
15 00 02 43 02
15 00 02 44 00
15 00 02 45 00
15 00 02 46 1F
15 00 02 47 1F
15 00 02 48 1E
15 00 02 49 1E
15 00 02 4A 1F
15 00 02 4B 17
15 00 02 4C 17
15 00 02 4D 37
15 00 02 4E 37
15 00 02 4F 09
15 00 02 50 09
15 00 02 51 0B
15 00 02 52 0B
15 00 02 53 05
15 00 02 54 05
15 00 02 55 07
15 00 02 56 07
15 00 02 57 1F
15 00 02 58 40
15 00 02 5B 30
15 00 02 5C 16
15 00 02 5D 34
15 00 02 5E 05
15 00 02 5F 02
15 00 02 63 00
15 00 02 64 6A
15 00 02 67 73
15 00 02 68 1D
15 00 02 69 08
15 00 02 6A 6A
15 00 02 6B 08
15 00 02 6C 00
15 00 02 6D 00
15 00 02 6E 00
15 00 02 6F 88
15 00 02 75 FF
15 00 02 77 DD
15 00 02 78 3F
15 00 02 79 15
15 00 02 7A 17
15 00 02 7D 14
15 00 02 7E 82
15 00 02 E0 04
15 00 02 00 0E
15 00 02 02 B3
15 00 02 09 61
15 00 02 0E 48
15 00 02 E0 00
15 00 02 E6 02
15 00 02 E7 0C
15 00 02 11 00
//15 78 02 E0 00
15 78 02 29 00
15 05 02 35 00
];
display-timings {
native-mode = <&timing1>;
timing1: timing1 {
clock-frequency = <71000000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <48>;
hsync-len = <8>;
hback-porch = <42>;
vfront-porch = <15>;
vsync-len = <6>;
vback-porch = <16>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
swap-rb=<0>;
swap-rg=<1>;
swap-gb=<1>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in_dsi: endpoint {
remote-endpoint = <&dsi_out_panel>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
dsi_out_panel: endpoint {
remote-endpoint = <&panel_in_dsi>;
};
};
};
};
&dsi_in_vopb {
status = "okay";
};
&dsi_in_vopl {
status = "disabled";
};
&route_dsi {
connect = <&vopb_out_dsi>;
status = "okay";
//status = "disabled";
};