255 lines
4.8 KiB
Plaintext
Executable File
255 lines
4.8 KiB
Plaintext
Executable File
/*
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* Copyright (C) 2023 walter, Inc.
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* arch/arm64/boot/dts/lcd-mipi6.86-TXW.dtsi
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* Single Chip Driver: ST7703
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* resolution: 480*1280
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* mipi channel: 4
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*/
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&dsi {
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status = "okay";
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//status = "disabled";
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//rockchip,lane-rate = <800>;
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panel@0 {
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compatible = "simple-panel-dsi";
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reg = <0>;
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backlight = <&backlight>;
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prepare-delay-ms = <2>;
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reset-delay-ms = <20>;
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init-delay-ms = <20>;
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enable-delay-ms = <120>;
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disable-delay-ms = <50>;
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unprepare-delay-ms = <20>;
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width-mm = <66>;
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height-mm = <160>;
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dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
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dsi,format = <MIPI_DSI_FMT_RGB888>;
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dsi,lanes = <4>;
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panel-init-sequence = [
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15 0A 02 FF 30
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15 00 02 FF 52
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15 00 02 FF 01
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15 00 02 E3 00
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15 00 02 08 0E
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15 00 02 25 0A
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15 00 02 28 77//77
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15 00 02 29 04
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15 00 02 37 9C
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15 00 02 38 A7
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15 00 02 30 58//58//78//38
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15 00 02 45 91//91
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15 00 02 A3 58
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15 00 02 2C 03
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15 00 02 C3 0F
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15 00 02 D6 00
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15 00 02 39 55//VCOM
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15 00 02 49 3C
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15 00 02 59 FE
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15 00 02 80 20//2POWER
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15 00 02 91 67
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15 00 02 92 67
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15 00 02 99 56
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15 00 02 9B 5C
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15 00 02 A0 55
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15 00 02 A1 50
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15 00 02 A4 9C
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15 00 02 A7 02
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15 00 02 A8 01
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15 00 02 A9 21
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15 00 02 AA A8
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15 00 02 AB 28
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15 00 02 AC E0
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15 00 02 AD E2
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15 00 02 AE E2
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15 00 02 AF 02
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15 00 02 B0 E2
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15 00 02 B1 26
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15 00 02 B2 28
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15 00 02 B3 28
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15 00 02 B4 22
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15 00 02 B5 E2
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15 00 02 B6 26
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15 00 02 B7 E2
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15 00 02 B8 26
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15 00 02 F6 C0
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15 00 02 F0 00
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15 00 02 FF 30
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15 00 02 FF 52
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15 00 02 FF 02
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15 00 02 B5 3E
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15 00 02 D5 3C
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15 00 02 B0 08
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15 00 02 D0 0A
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15 00 02 B4 2F
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15 00 02 D4 2C
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15 00 02 B1 0B
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15 00 02 D1 08
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15 00 02 B3 2F
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15 00 02 D3 2D
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15 00 02 B2 05
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15 00 02 D2 05
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15 00 02 B7 26
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15 00 02 D7 25
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15 00 02 B6 02
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15 00 02 D6 01
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15 00 02 C0 17
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15 00 02 E0 19
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15 00 02 C1 04
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15 00 02 E1 04
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15 00 02 BF 11
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15 00 02 DF 11
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15 00 02 B8 0A
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15 00 02 D8 0A
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15 00 02 BE 19
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15 00 02 DE 19
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15 00 02 B9 00
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15 00 02 D9 01
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15 00 02 BD 0F
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15 00 02 DD 0F
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15 00 02 BA 0E
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15 00 02 DA 0D
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15 00 02 BC 0D
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15 00 02 DC 0B
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15 00 02 BB 0B
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15 00 02 DB 0B
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15 00 02 FF 30
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15 00 02 FF 52
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15 00 02 FF 03
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15 00 02 08 8a
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15 00 02 09 89
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15 00 02 27 06
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15 00 02 2A 00
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15 00 02 34 01
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15 00 02 35 00
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15 00 02 36 00
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15 00 02 37 03
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15 00 02 40 8a
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15 00 02 41 89
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15 00 02 42 88
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15 00 02 43 87
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15 00 02 44 44
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15 00 02 45 fc
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15 00 02 46 fd
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15 00 02 47 54
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15 00 02 48 fe
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15 00 02 49 ff
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15 00 02 50 86
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15 00 02 51 85
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15 00 02 52 84
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15 00 02 53 83
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15 00 02 55 00
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15 00 02 56 01
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15 00 02 58 02
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15 00 02 59 03
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15 00 02 7E 78
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15 00 02 80 02
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15 00 02 81 0F
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15 00 02 82 00
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15 00 02 83 0F
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15 00 02 84 0E
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15 00 02 85 0C
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15 00 02 86 0D
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15 00 02 87 07
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15 00 02 88 06
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15 00 02 89 05
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15 00 02 8A 04
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15 00 02 96 02
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15 00 02 97 0F
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15 00 02 98 00
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15 00 02 99 0F
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15 00 02 9A 0E
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15 00 02 9B 0C
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15 00 02 9C 0D //0D
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15 00 02 9D 07
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15 00 02 9E 06
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15 00 02 9F 05
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15 00 02 A0 04
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15 00 02 FF 30
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15 00 02 FF 52
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15 00 02 FF 00
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15 00 02 36 02
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//15 00 02 11 00
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//15 00 02 11 00
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//15 78 02 29 00
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//15 05 02 35 00
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05 C8 01 11
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05 14 01 29
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];
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display-timings {
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native-mode = <&timing1>;
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timing1: timing1 {
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clock-frequency = <72000000>;
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hactive = <600>;
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vactive = <1280>;
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hfront-porch = <24>;
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hsync-len = <2>;
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hback-porch = <30>;
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vfront-porch = <16>;
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vsync-len = <6>;
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vback-porch = <8>;
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hsync-active = <0>;
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vsync-active = <2>;
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de-active = <0>;
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pixelclk-active = <0>;
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swap-rb=<0>;
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swap-rg=<0>;
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swap-gb=<0>;
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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panel_in_dsi: endpoint {
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remote-endpoint = <&dsi_out_panel>;
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};
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};
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};
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};
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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dsi_out_panel: endpoint {
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remote-endpoint = <&panel_in_dsi>;
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};
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};
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};
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};
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&dsi_in_vopb {
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status = "okay";
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};
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&dsi_in_vopl {
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status = "disabled";
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};
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&route_dsi {
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connect = <&vopb_out_dsi>;
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status = "okay";
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//status = "disabled";
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};
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