155 lines
3.1 KiB
Plaintext
Executable File
155 lines
3.1 KiB
Plaintext
Executable File
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
|
|
*/
|
|
|
|
|
|
#include <dt-bindings/display/drm_mipi_dsi.h>
|
|
#include <dt-bindings/display/media-bus-format.h>
|
|
#include <dt-bindings/clock/rk618-cru.h>
|
|
|
|
/ {
|
|
panel {
|
|
//compatible = "lg,lm215wf3", "simple-panel";
|
|
compatible = "simple-panel";
|
|
backlight = <&backlight>;
|
|
//power-supply = <&vcc3v3_lcd>;
|
|
//enable-gpios = <&gpio1 RK_PD7 GPIO_ACTIVE_LOW>;
|
|
prepare-delay-ms = <120>;
|
|
enable-delay-ms = <120>;
|
|
disable-delay-ms = <120>;
|
|
unprepare-delay-ms = <120>;
|
|
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
|
|
//bus-format = <MEDIA_BUS_FMT_RGB666_1X24_CPADHI>;
|
|
width-mm = <476>;
|
|
height-mm = <90>;
|
|
display-timings {
|
|
native-mode = <&timing0>;
|
|
|
|
timing0: timing0 {
|
|
clock-frequency = <148000000>;
|
|
hactive = <1920>;
|
|
vactive = <1080>;
|
|
hback-porch = <120>;
|
|
hfront-porch = <220>;
|
|
vback-porch = <40>;
|
|
vfront-porch = <10>;
|
|
hsync-len = <8>;
|
|
vsync-len = <4>;
|
|
hsync-active = <0>;
|
|
vsync-active = <0>;
|
|
de-active = <0>;
|
|
pixelclk-active = <0>;
|
|
};
|
|
};
|
|
|
|
port {
|
|
panel_in_lvds: endpoint {
|
|
remote-endpoint = <&lvds_out_panel>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&dmc {
|
|
auto-freq-en = <0>;
|
|
};
|
|
|
|
&i2c1 {
|
|
status = "okay";
|
|
//status = "disabled";
|
|
rk618@50 {
|
|
compatible = "rockchip,rk618";
|
|
reg = <0x50>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s1_2ch_mclk>;
|
|
clocks = <&cru SCLK_I2S1_OUT>;
|
|
clock-names = "clkin";
|
|
assigned-clocks = <&cru SCLK_I2S1_OUT>;
|
|
assigned-clock-rates = <11289600>;
|
|
//assigned-clock-rates = <12000000>;
|
|
reset-gpios = <&gpio1 RK_PD6 GPIO_ACTIVE_LOW>;
|
|
status = "okay";
|
|
|
|
clock: cru {
|
|
compatible = "rockchip,rk618-cru";
|
|
clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPB>;
|
|
//clocks = <&cru SCLK_I2S1_OUT>, <&cru DCLK_VOPL>;
|
|
clock-names = "clkin", "lcdc0_dclkp";
|
|
assigned-clocks = <&clock SCALER_PLLIN_CLK>,
|
|
<&clock VIF_PLLIN_CLK>,
|
|
<&clock SCALER_CLK>,
|
|
<&clock VIF0_PRE_CLK>,
|
|
<&clock CODEC_CLK>,
|
|
<&clock DITHER_CLK>;
|
|
assigned-clock-parents = <&cru SCLK_I2S1_OUT>,
|
|
<&clock LCDC0_CLK>,
|
|
<&clock SCALER_PLL_CLK>,
|
|
<&clock VIF_PLL_CLK>,
|
|
<&cru SCLK_I2S1_OUT>,
|
|
<&clock VIF0_CLK>;
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
lvds {
|
|
compatible = "rockchip,rk618-lvds";
|
|
clocks = <&cru LVDS_CLK>;
|
|
clock-names = "lvds";
|
|
dual-channel;
|
|
status = "okay";
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
|
|
lvds_in_rgb: endpoint {
|
|
remote-endpoint = <&rgb_out_lvds>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
lvds_out_panel: endpoint {
|
|
remote-endpoint = <&panel_in_lvds>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rgb {
|
|
status = "okay";
|
|
|
|
ports {
|
|
port@1 {
|
|
reg = <1>;
|
|
|
|
rgb_out_lvds: endpoint {
|
|
remote-endpoint = <&lvds_in_rgb>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&rgb_in_vopb {
|
|
//status = "disabled";
|
|
status = "okay";
|
|
};
|
|
|
|
&rgb_in_vopl {
|
|
//status = "okay";
|
|
status = "disabled";
|
|
};
|
|
|
|
&route_rgb {
|
|
connect = <&vopb_out_rgb>;
|
|
//connect = <&vopl_out_rgb>;
|
|
status = "okay";
|
|
//status = "disabled";
|
|
};
|