456 lines
13 KiB
C
456 lines
13 KiB
C
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <boot_rkimg.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <misc.h>
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#include <mmc.h>
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#include <scsi.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/boot_mode.h>
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#include <asm/arch/ioc_rk3576.h>
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#include <asm/arch/rockchip_smccc.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define SYS_GRF_BASE 0x2600A000
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#define SYS_GRF_SOC_CON2 0x0008
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#define SYS_GRF_SOC_CON7 0x001c
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#define SYS_GRF_SOC_CON11 0x002c
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#define SYS_GRF_SOC_CON12 0x0030
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#define GPIO0_IOC_BASE 0x26040000
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#define GPIO0B_PULL_L 0x0024
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#define GPIO0B_IE_L 0x002C
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#define TOP_IOC_BASE 0x26044000
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#define GPIO1A_IOMUX_SEL_L 0x0020
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#define GPIO1A_IOMUX_SEL_H 0x0024
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#define GPIO1B_IOMUX_SEL_L 0x0028
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#define GPIO1B_IOMUX_SEL_H 0x002c
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#define GPIO1C_IOMUX_SEL_L 0x0030
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#define GPIO1C_IOMUX_SEL_H 0x0034
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#define GPIO1D_IOMUX_SEL_L 0x0038
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#define GPIO1D_IOMUX_SEL_H 0x003c
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#define GPIO2A_IOMUX_SEL_L 0x0040
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#define GPIO2A_IOMUX_SEL_H 0x0044
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#define VCCIO_IOC_BASE 0x26046000
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#define VCCIO_IOC_GPIO1C_PUL 0x118
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#define VCCIO_IOC_GPIO1D_PUL 0x11C
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#define VCCIO_IOC_GPIO2A_PUL 0x120
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#define VCCIO6_IOC_BASE 0x2604a000
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#define VCCIO7_IOC_BASE 0x2604b000
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#define VCCIO7_IOC_GPIO4D_IOMUX_SEL_L 0x0398
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#define VCCIO7_IOC_XIN_UFS_CON 0x0400
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#define PMU1_SGRF_BASE 0x26002000
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#define PMU1_SGRF_SOC_CON10 0x0028
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#define PMU1_SGRF_SOC_CON11 0x002C
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#define SYS_SGRF_BASE 0x26004000
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#define SYS_SGRF_SOC_CON14 0x0058
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#define SYS_SGRF_SOC_CON15 0x005C
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#define SYS_SGRF_SOC_CON20 0x0070
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#define FW_SYS_SGRF_BASE 0x26005000
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#define SGRF_DOMAIN_CON1 0x4
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#define SGRF_DOMAIN_CON2 0x8
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#define SGRF_DOMAIN_CON3 0xc
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#define SGRF_DOMAIN_CON4 0x10
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#define SGRF_DOMAIN_CON5 0x14
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#define USBGRF_BASE 0x2601e000
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#define USB_GRF_USB3OTG0_CON1 0x0030
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#define PMU1_GRF_BASE 0x26026000
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#define OS_REG0 0x200
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#define USB2PHY0_GRF_BASE 0x2602e000
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#define USB2PHY1_GRF_BASE 0x26030000
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#define USB2PHY_GRF_CON4 0x0010
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#define USB2PHY_GRF_DBG_CON 0x0040
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#define USB2PHY_GRF_LS_TIMEOUT 0x0044
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#define USB2PHY_GRF_LS_DEB 0x0048
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#define USB2PHY_GRF_RX_TIMEOUT 0x004c
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#define USB2PHY_GRF_SEQ_LIMT 0x0050
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#define TOP_CRU_BASE 0x27200000
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#define TOP_CRU_GATE_CON19 0x084C
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#define TOP_CRU_SOFTRST_CON19 0x0a4C
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#define PHPPHYSOFTRST_CON01 0x8a04
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#define PMU1_CRU_BASE 0x27220000
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#define PMU1_CRU_CLKSEL_CON03 0x030c
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#define PMU1_CRU_GATE_CON03 0x080C
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#define PMU1_CRU_SOFTRST_CON03 0x0a0C
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region rk3576_mem_map[] = {
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{
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.virt = 0x20000000UL,
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.phys = 0x20000000UL,
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.size = 0xb080000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x3fe70000UL,
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.phys = 0x3fe70000UL,
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.size = 0x190000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x100000000UL - 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x100000000UL,
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.phys = 0x100000000UL,
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.size = 0x300000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x900000000UL,
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.phys = 0x900000000UL,
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.size = 0x100800000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = rk3576_mem_map;
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#endif
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void board_debug_uart_init(void)
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{
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}
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const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
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[BROM_BOOTSOURCE_EMMC] = "/mmc@2a330000",
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[BROM_BOOTSOURCE_SD] = "/mmc@2a310000",
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[BROM_BOOTSOURCE_UFS] = "/ufs@2a2d0000",
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};
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#ifdef CONFIG_SPL_BUILD
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void rockchip_stimer_init(void)
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{
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u32 reg;
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/* If Timer already enabled, don't re-init it */
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reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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if (reg & 0x1)
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return;
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#ifdef COUNTER_FREQUENCY
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asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
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#endif
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
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writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x04);
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}
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#endif
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void reset_misc(void)
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{
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#ifdef CONFIG_SPL_BUILD
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/* For RK3576 SPL, should extraly write os_reg0 and reset to maskrom. */
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if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) == BOOT_BROM_DOWNLOAD)
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writel(BOOT_BROM_DOWNLOAD, PMU1_GRF_BASE + OS_REG0);
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#elif CONFIG_SUPPORT_USBPLUG
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/*
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* For RK3576 USBPLUG, should clear maskrom flag both in os_reg0 and os_reg16.
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* It already clear os_reg16 under ./drivers/usb/gadget/f_rockusb.c
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*/
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if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != BOOT_BROM_DOWNLOAD)
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writel(0, (void *)PMU1_GRF_BASE + OS_REG0);
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#endif
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}
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void board_set_iomux(enum if_type if_type, int devnum, int routing)
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{
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switch (if_type) {
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case IF_TYPE_MMC:
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if (devnum == 0) {
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writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);
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writel(0xffff1111, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_H);
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writel(0xffff1111, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);
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} else if (devnum == 1) {
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writel(0xffff1111, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
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writel(0x00ff0011, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);
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/* Pull up */
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writel(0x0FFF0FFF, VCCIO_IOC_BASE + VCCIO_IOC_GPIO2A_PUL);
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}
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break;
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case IF_TYPE_MTD:
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if (routing == 0) {
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/* FSPI0 M0 */
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writel(0xffff2222, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);
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writel(0xffff2020, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);
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} else if (routing == 1) {
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/* FSPI1 M0 */
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writel(0xffff2222, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
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writel(0x00ff0022, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);
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/* Pull up */
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writel(0x03ff03ff, VCCIO_IOC_BASE + VCCIO_IOC_GPIO2A_PUL);
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} else if (routing == 2) {
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/* FSPI1 M1 */
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writel(0xf0003000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L);
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writel(0xffff3333, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H);
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writel(0x00f00030, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H);
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/* Pull up */
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writel(0xffc0ffc0, VCCIO_IOC_BASE + VCCIO_IOC_GPIO1C_PUL);
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}
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break;
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default:
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printf("Bootdev 0x%x is not support\n", if_type);
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}
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}
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void board_unset_iomux(enum if_type if_type, int devnum, int routing)
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{
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switch (if_type) {
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case IF_TYPE_MTD:
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if (routing == 0) {
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/* FSPI0 M0 -> GPIO */
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writel(0xffff0000, TOP_IOC_BASE + GPIO1A_IOMUX_SEL_L);
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writel(0xffff0000, TOP_IOC_BASE + GPIO1B_IOMUX_SEL_L);
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} else if (routing == 1) {
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/* FSPI1 M0 -> GPIO */
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writel(0xffff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
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writel(0x00ff0000, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_H);
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} else if (routing == 2) {
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/* FSPI1 M1 -> GPIO */
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writel(0xf0000000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_L);
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writel(0xffff0000, TOP_IOC_BASE + GPIO1C_IOMUX_SEL_H);
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writel(0x00f00000, TOP_IOC_BASE + GPIO1D_IOMUX_SEL_H);
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}
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break;
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default:
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break;
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}
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}
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/* @brief: release reset for MCU
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* @param id: id of MCU, like: bus_mcu, pmu_mcu
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* @param entry_point: entry of firmware, use for address map
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* */
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int fit_standalone_release(char *id, uintptr_t entry_point)
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{
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if (!strcmp(id, "bus_mcu")) {
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/* address map: map 0 to entry_point */
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sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
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ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
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entry_point);
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/*
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* bus m0 configuration:
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* open bus m0 rtc / core / biu / root
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*/
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writel(0x5c000000, TOP_CRU_BASE + TOP_CRU_GATE_CON19);
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/* select bus m0 jtag GPIO2A2 GPIO2A3 */
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//writel(0x003f0010, SYS_GRF_BASE + SYS_GRF_SOC_CON7);
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//writel(0xff009900, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L);
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/* release bus m0 jtag / core / biu */
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writel(0x38000000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON19);
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}
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else if (!strcmp(id, "pmu_mcu")) {
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/* pmu m0 configuration: */
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/* open pmu m0 rtc / core / biu / root */
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/* writel(0x59020000, PMU1_CRU_BASE + PMU1_CRU_GATE_CON03); */
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/* select pmu m0 jtag */
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/* writel(0x003f0008, SYS_GRF_BASE + SYS_GRF_SOC_CON7); */
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/* writel(0xff009900, TOP_IOC_BASE + GPIO2A_IOMUX_SEL_L); */
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/* release pmu m0 jtag / core / biu */
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/* writel(0x38000000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON03); */
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}
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return 0;
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}
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#ifndef CONFIG_TPL_BUILD
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int arch_cpu_init(void)
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{
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
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u32 val;
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/* Set the emmc to access ddr memory */
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
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writel(val | 0x7, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON2);
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/* Set the sdmmc0 to access ddr memory */
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
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writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON5);
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/* Set the UFS to access ddr memory */
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
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writel(val | 0x70000, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON3);
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/* Set the fspi0 and fspi1 to access ddr memory */
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
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writel(val | 0x7700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON4);
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/* Set the decom to access ddr memory */
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val = readl(FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
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writel(val | 0x700, FW_SYS_SGRF_BASE + SGRF_DOMAIN_CON1);
|
||
|
|
|
||
|
|
/* UFS PHY select 26M from ppll */
|
||
|
|
writel(0x00030002, PMU1_CRU_BASE + PMU1_CRU_CLKSEL_CON03);
|
||
|
|
|
||
|
|
/* set iomux UFS_REFCLK, UFS_RSTN */
|
||
|
|
writel(0x00FF0011, VCCIO7_IOC_BASE + VCCIO7_IOC_GPIO4D_IOMUX_SEL_L);
|
||
|
|
/* set UFS_RSTN to high */
|
||
|
|
udelay(20);
|
||
|
|
writel(0x00100010, VCCIO7_IOC_BASE + VCCIO7_IOC_XIN_UFS_CON);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set the GPIO0B0~B3 pull up and input enable.
|
||
|
|
* Keep consistent with other IO.
|
||
|
|
*/
|
||
|
|
writel(0x00ff00ff, GPIO0_IOC_BASE + GPIO0B_PULL_L);
|
||
|
|
writel(0x000f000f, GPIO0_IOC_BASE + GPIO0B_IE_L);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* bus mcu_cache_peripheral_addr
|
||
|
|
* The uncache area ranges from 0x20000000 to 0x48200000
|
||
|
|
* and contains rpmsg shared memory
|
||
|
|
*/
|
||
|
|
writel(0x20000000, SYS_SGRF_BASE + SYS_SGRF_SOC_CON14);
|
||
|
|
writel(0x48200000, SYS_SGRF_BASE + SYS_SGRF_SOC_CON15);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* pmu mcu_cache_peripheral_addr
|
||
|
|
* The uncache area ranges from 0x20000000 to 0x48200000
|
||
|
|
* and contains rpmsg shared memory
|
||
|
|
*/
|
||
|
|
/* writel(0x20000000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10); */
|
||
|
|
/* writel(0x48200000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON11); */
|
||
|
|
|
||
|
|
/* TODO: pmu mcu code addr need bl31 support */
|
||
|
|
/* writel(0x48200000, 0x26002030); */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set SYS_GRF_SOC_CON2[12](input of pwm2_ch0) as 0,
|
||
|
|
* keep consistent with other pwm.
|
||
|
|
*/
|
||
|
|
writel(0x10000000, SYS_GRF_BASE + SYS_GRF_SOC_CON2);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Assert reset the combophy0 and combophy1,
|
||
|
|
* de-assert reset in Kernel combophy driver.
|
||
|
|
*/
|
||
|
|
writel(0x01200120, TOP_CRU_BASE + PHPPHYSOFTRST_CON01);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Assert SIDDQ for USB 2.0 PHY1 to power down
|
||
|
|
* PHY1 analog block to save power. And let the
|
||
|
|
* PHY0 for OTG0 interface still in normal mode.
|
||
|
|
*/
|
||
|
|
writel(0x20002000, USB2PHY1_GRF_BASE + USB2PHY_GRF_CON4);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable USB to DEBUG
|
||
|
|
* 1. Set linestate timeout 8ms
|
||
|
|
* 2. Set linestate fiter time 500us
|
||
|
|
* 3. Set Rx timeout counter for RX pulldown 2s
|
||
|
|
* 4. Set handshake counter number for SE0 and
|
||
|
|
* SE1 sequence at least 5.
|
||
|
|
*/
|
||
|
|
writel(0xff, USB2PHY0_GRF_BASE + USB2PHY_GRF_LS_TIMEOUT);
|
||
|
|
writel(0x10, USB2PHY0_GRF_BASE + USB2PHY_GRF_LS_DEB);
|
||
|
|
writel(0xffff, USB2PHY0_GRF_BASE + USB2PHY_GRF_RX_TIMEOUT);
|
||
|
|
writel(0x05, USB2PHY0_GRF_BASE + USB2PHY_GRF_SEQ_LIMT);
|
||
|
|
writel(0x00010001, USB2PHY0_GRF_BASE + USB2PHY_GRF_DBG_CON);
|
||
|
|
|
||
|
|
/* Enable noc slave response timeout */
|
||
|
|
writel(0x80008000, SYS_GRF_BASE + SYS_GRF_SOC_CON11);
|
||
|
|
writel(0xffffffe0, SYS_GRF_BASE + SYS_GRF_SOC_CON12);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Select usb otg0 pipe phy status to 0 that
|
||
|
|
* ensure rockusb can work at high-speed even
|
||
|
|
* if usb3 phy isn't ready.
|
||
|
|
*/
|
||
|
|
writel(0x000c0008, USBGRF_BASE + USB_GRF_USB3OTG0_CON1);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Enable cci channels for below module AXI R/W
|
||
|
|
* Module: GMAC0/1, MMU0/1(PCIe, SATA, USB3)
|
||
|
|
*/
|
||
|
|
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
|
||
|
|
board_set_iomux(IF_TYPE_MMC, 0, 0);
|
||
|
|
#elif defined(CONFIG_ROCKCHIP_SFC_IOMUX)
|
||
|
|
/*
|
||
|
|
* (IF_TYPE_MTD, 0, 0) FSPI0
|
||
|
|
* (IF_TYPE_MTD, 1, 0) FSPI1 M0
|
||
|
|
* (IF_TYPE_MTD, 2, 0) FSPI1 M1
|
||
|
|
*/
|
||
|
|
board_set_iomux(IF_TYPE_MTD, 0, 0);
|
||
|
|
#endif /* #if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) */
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if defined(CONFIG_SCSI) && defined(CONFIG_CMD_SCSI) && defined(CONFIG_UFS)
|
||
|
|
int rk_board_dm_fdt_fixup(const void *blob)
|
||
|
|
{
|
||
|
|
struct blk_desc *desc = rockchip_get_bootdev();
|
||
|
|
const char *status = NULL;
|
||
|
|
int node = -1;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* 1. Kernel DTS will enable UFS by default.
|
||
|
|
*
|
||
|
|
* 2. It hangs if Kernel UFS driver tries to access UFS registers when there
|
||
|
|
* is no power supply for UFS.
|
||
|
|
*
|
||
|
|
* So generally, disable UFS when detect fail.
|
||
|
|
*
|
||
|
|
* To save time spent on detecting UFS, you can disable UFS in kernel dts or
|
||
|
|
* U-Boot defconfig.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
if (desc->if_type != IF_TYPE_SCSI) {
|
||
|
|
node = fdt_path_offset(blob, "/ufs@2a2d0000");
|
||
|
|
if (node >= 0) {
|
||
|
|
status = fdt_getprop(blob, node, "status", NULL);
|
||
|
|
if (status && strcmp(status, "disabled")) {
|
||
|
|
if (scsi_scan(true)) {
|
||
|
|
fdt_setprop((void *)blob, node, "status", "disabled", 9);
|
||
|
|
printf("FDT: UFS was not detected, disabling UFS.\n");
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|