72 lines
1.6 KiB
C
72 lines
1.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip UFS Host Controller driver
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*
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* Copyright (C) 2024 Rockchip Electronics Co.Ltd.
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*/
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#ifndef _UFS_ROCKCHIP_H_
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#define _UFS_ROCKCHIP_H_
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#define UFS_MAX_CLKS 3
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#define SEL_TX_LANE0 0x0
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#define SEL_TX_LANE1 0x1
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#define SEL_TX_LANE2 0x2
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#define SEL_TX_LANE3 0x3
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#define SEL_RX_LANE0 0x4
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#define SEL_RX_LANE1 0x5
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#define SEL_RX_LANE2 0x6
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#define SEL_RX_LANE3 0x7
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#define MIB_T_DBG_CPORT_TX_ENDIAN 0xc022
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#define MIB_T_DBG_CPORT_RX_ENDIAN 0xc023
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/* Vendor specific attributes */
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enum dwc_specific_registers {
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DWC_UFS_REG_HCLKDIV = 0xFC,
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};
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/* Clock Divider Values: Hex equivalent of frequency in MHz */
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enum clk_div_values {
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DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
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DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
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DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
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};
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/* Selector Index */
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enum selector_index {
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SELIND_LN0_TX = 0x00,
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SELIND_LN1_TX = 0x01,
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SELIND_LN0_RX = 0x04,
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SELIND_LN1_RX = 0x05,
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};
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struct ufshcd_dme_attr_val {
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u32 attr_sel;
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u32 mib_val;
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u8 peer;
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};
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struct ufs_rockchip_host {
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struct ufs_hba *hba;
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void __iomem *ufs_phy_ctrl;
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void __iomem *ufs_sys_ctrl;
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void __iomem *mphy_base;
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struct reset_ctl_bulk rsts;
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struct clk ref_out_clk;
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uint64_t caps;
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uint32_t phy_config_mode;
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bool in_suspend;
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};
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#define ufs_sys_writel(base, val, reg) \
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writel((val), (base) + (reg))
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#define ufs_sys_readl(base, reg) readl((base) + (reg))
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#define ufs_sys_set_bits(base, mask, reg) \
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ufs_sys_writel((base), ((mask) | (ufs_sys_readl((base), (reg)))), (reg))
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#define ufs_sys_ctrl_clr_bits(base, mask, reg) \
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ufs_sys_writel((base), ((~(mask)) & (ufs_sys_readl((base), (reg)))), (reg))
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#endif /* _UFS_ROCKCHIP_H_ */
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