// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
 */

#include <dt-bindings/pinctrl/rockchip.h>
#include "rockchip-pinconf.dtsi"

/*
 * This file is auto generated by pin2dts tool, please keep these code
 * by adding changes at end of this file.
 */
&pinctrl {
	cam_clk0 {
		cam_clk0_pins: cam-clk0-pins {
			rockchip,pins =
				/* cam_clk0_out */
				<1 RK_PB5 1 &pcfg_pull_none>;
		};
	};

	cam_clk1 {
		cam_clk1_pins: cam-clk1-pins {
			rockchip,pins =
				/* cam_clk1_out */
				<1 RK_PB6 1 &pcfg_pull_none>;
		};
	};

	cam_spi {
		cam_spi_bus4_pins: cam-spi-bus4-pins {
			rockchip,pins =
				/* cam_spi_d0 */
				<0 RK_PB5 4 &pcfg_pull_up_drv_level_2>,
				/* cam_spi_d1 */
				<0 RK_PB2 4 &pcfg_pull_up_drv_level_2>,
				/* cam_spi_d2 */
				<0 RK_PB1 4 &pcfg_pull_up_drv_level_2>,
				/* cam_spi_d3 */
				<0 RK_PB0 4 &pcfg_pull_up_drv_level_2>;
		};

		cam_spi_clk_pins: cam-spi-clk-pins {
			rockchip,pins =
				/* cam_spi_clk */
				<0 RK_PB4 4 &pcfg_pull_none>;
		};
		cam_spi_cs0n_pins: cam-spi-cs0n-pins {
			rockchip,pins =
				/* cam_spi_cs0n */
				<0 RK_PB3 4 &pcfg_pull_none>;
		};
	};

	clk {
		clk_32k_pins: clk-32k-pins {
			rockchip,pins =
				/* clk_32k */
				<0 RK_PA0 2 &pcfg_pull_none>;
		};
	};

	clk_24m {
		clk_24m_out_pins: clk-24m-out-pins {
			rockchip,pins =
				/* clk_24m_out */
				<0 RK_PA0 3 &pcfg_pull_none>;
		};
	};

	cpu {
		cpu_pins: cpu-pins {
			rockchip,pins =
				/* cpu_avs */
				<0 RK_PA1 2 &pcfg_pull_none>;
		};
	};

	emmc {
		emmc_bus4_pins: emmc-bus4-pins {
			rockchip,pins =
				/* emmc_d0 */
				<1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d1 */
				<1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d2 */
				<1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
				/* emmc_d3 */
				<1 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
		};

		emmc_clk_pins: emmc-clk-pins {
			rockchip,pins =
				/* emmc_clk */
				<1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
		};

		emmc_cmd_pins: emmc-cmd-pins {
			rockchip,pins =
				/* emmc_cmd */
				<1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
		};
	};

	emmc_testclk {
		emmc_testclk_clk_pins: emmc-testclk-clk-pins {
			rockchip,pins =
				/* emmc_testclk_out */
				<1 RK_PA7 3 &pcfg_pull_up_drv_level_2>;
		};
	};

	emmc_testdata {
		emmc_testdata_out_pins: emmc-testdata-out-pins {
			rockchip,pins =
				/* emmc_testdata_out */
				<1 RK_PB0 3 &pcfg_pull_none>;
		};
	};

	eth_led {
		eth_led_pins: eth-led-pins {
			rockchip,pins =
				/* eth_led_dpx */
				<2 RK_PA4 6 &pcfg_pull_none>,
				/* eth_led_link */
				<2 RK_PA6 6 &pcfg_pull_none>,
				/* eth_led_spd */
				<2 RK_PA7 6 &pcfg_pull_none>;
		};
	};

	flash_trig {
		flash_trig_pins: flash-trig-pins {
			rockchip,pins =
				/* flash_trig_out */
				<2 RK_PB0 6 &pcfg_pull_none>;
		};
	};

	fspi {
		fspi_bus4_pins: fspi-bus4-pins {
			rockchip,pins =
				/* fspi_d0 */
				<1 RK_PA1 2 &pcfg_pull_none>,
				/* fspi_d1 */
				<1 RK_PA2 2 &pcfg_pull_none>,
				/* fspi_d2 */
				<1 RK_PA3 2 &pcfg_pull_none>,
				/* fspi_d3 */
				<1 RK_PA0 2 &pcfg_pull_none>;
		};

		fspi_cs0_pins: fspi-cs0-pins {
			rockchip,pins =
				/* fspi_cs0n */
				<1 RK_PA5 2 &pcfg_pull_up>;
		};

		fspi_clk_pins: fspi-clk-pins {
			rockchip,pins =
				/* fspi_clk */
				<1 RK_PA4 2 &pcfg_pull_none>;
		};
	};

	fspi_testclk {
		fspi_testclk_out_pins: fspi-testclk-out-pins {
			rockchip,pins =
				/* fspi_testclk_out */
				<1 RK_PA7 5 &pcfg_pull_none>;
		};
	};

	fspi_testdata {
		fspi_testdata_out_pins: fspi-testdata-out-pins {
			rockchip,pins =
				/* fspi_testdata_out */
				<1 RK_PB0 5 &pcfg_pull_none>;
		};
	};

	i2c0 {
		i2c0m0_xfer_pins: i2c0m0-xfer-pins {
			rockchip,pins =
				/* i2c0_scl_m0 */
				<0 RK_PA5 3 &pcfg_pull_none_smt>,
				/* i2c0_sda_m0 */
				<0 RK_PA6 3 &pcfg_pull_none_smt>;
		};

		i2c0m1_xfer_pins: i2c0m1-xfer-pins {
			rockchip,pins =
				/* i2c0_scl_m1 */
				<1 RK_PB4 5 &pcfg_pull_none_smt>,
				/* i2c0_sda_m1 */
				<1 RK_PB3 5 &pcfg_pull_none_smt>;
		};

		i2c0m2_xfer_pins: i2c0m2-xfer-pins {
			rockchip,pins =
				/* i2c0_scl_m2 */
				<1 RK_PB5 2 &pcfg_pull_none_smt>,
				/* i2c0_sda_m2 */
				<1 RK_PB6 2 &pcfg_pull_none_smt>;
		};
	};

	i2c1 {
		i2c1m0_xfer_pins: i2c1m0-xfer-pins {
			rockchip,pins =
				/* i2c1_scl_m0 */
				<0 RK_PB0 1 &pcfg_pull_none_smt>,
				/* i2c1_sda_m0 */
				<0 RK_PB1 1 &pcfg_pull_none_smt>;
		};

		i2c1m1_xfer_pins: i2c1m1-xfer-pins {
			rockchip,pins =
				/* i2c1_scl_m1 */
				<2 RK_PA4 4 &pcfg_pull_none_smt>,
				/* i2c1_sda_m1 */
				<2 RK_PA5 4 &pcfg_pull_none_smt>;
		};
	};

	i2c2 {
		i2c2m0_xfer_pins: i2c2m0-xfer-pins {
			rockchip,pins =
				/* i2c2_scl_m0 */
				<0 RK_PB2 1 &pcfg_pull_none_smt>,
				/* i2c2_sda_m0 */
				<0 RK_PB3 1 &pcfg_pull_none_smt>;
		};

		i2c2m1_xfer_pins: i2c2m1-xfer-pins {
			rockchip,pins =
				/* i2c2_scl_m1 */
				<2 RK_PA6 4 &pcfg_pull_none_smt>,
				/* i2c2_sda_m1 */
				<2 RK_PA7 4 &pcfg_pull_none_smt>;
		};
	};

	i2c3 {
		i2c3m0_xfer_pins: i2c3m0-xfer-pins {
			rockchip,pins =
				/* i2c3_scl_m0 */
				<0 RK_PB4 1 &pcfg_pull_none_smt>,
				/* i2c3_sda_m0 */
				<0 RK_PB5 1 &pcfg_pull_none_smt>;
		};

		i2c3m1_xfer_pins: i2c3m1-xfer-pins {
			rockchip,pins =
				/* i2c3_scl_m1 */
				<2 RK_PB3 4 &pcfg_pull_none_smt>,
				/* i2c3_sda_m1 */
				<2 RK_PB2 4 &pcfg_pull_none_smt>;
		};
	};

	i2c4 {
		i2c4m0_xfer_pins: i2c4m0-xfer-pins {
			rockchip,pins =
				/* i2c4_scl_m0 */
				<2 RK_PB0 4 &pcfg_pull_none_smt>,
				/* i2c4_sda_m0 */
				<2 RK_PB1 4 &pcfg_pull_none_smt>;
		};

		i2c4m1_xfer_pins: i2c4m1-xfer-pins {
			rockchip,pins =
				/* i2c4_scl_m1 */
				<1 RK_PB7 2 &pcfg_pull_none_smt>,
				/* i2c4_sda_m1 */
				<1 RK_PC0 2 &pcfg_pull_none_smt>;
		};
	};

	jtag {
		jtagm0_pins: jtagm0-pins {
			rockchip,pins =
				/* jtag_tck_m0 */
				<0 RK_PA5 5 &pcfg_pull_none>,
				/* jtag_tms_m0 */
				<0 RK_PA6 5 &pcfg_pull_none>;
		};

		jtagm1_pins: jtagm1-pins {
			rockchip,pins =
				/* jtag_tck_m1 */
				<0 RK_PB4 3 &pcfg_pull_none>,
				/* jtag_tms_m1 */
				<0 RK_PB5 3 &pcfg_pull_none>;
		};

		jtagm2_pins: jtagm2-pins {
			rockchip,pins =
				/* jtag_tck_m2 */
				<1 RK_PB4 3 &pcfg_pull_none>,
				/* jtag_tms_m2 */
				<1 RK_PB3 3 &pcfg_pull_none>;
		};
	};

	pmu_debug_test {
		pmu_debug_test_pins: pmu-debug-test-pins {
			rockchip,pins =
				/* pmu_debug_test_out */
				<0 RK_PB1 5 &pcfg_pull_none>;
		};
	};

	prelight_trig {
		prelight_trig_pins: prelight-trig-pins {
			rockchip,pins =
				/* prelight_trig_out */
				<2 RK_PB1 6 &pcfg_pull_none>;
		};
	};

	psram_spi {
		psram_spi_bus4_pins: psram-spi-bus4-pins {
			rockchip,pins =
				/* psram_spi_d0 */
				<0 RK_PA2 4 &pcfg_pull_none>,
				/* psram_spi_d1 */
				<0 RK_PA1 4 &pcfg_pull_none>,
				/* psram_spi_d2 */
				<0 RK_PA5 4 &pcfg_pull_none>,
				/* psram_spi_d3 */
				<0 RK_PA6 4 &pcfg_pull_none>;
		};

		psram_spi_clk_pins: psram-spi-clk-pins {
			rockchip,pins =
				/* psram_spi_clk */
				<0 RK_PA0 4 &pcfg_pull_none>;
		};
		psram_spi_cs0n_pins: psram-spi-cs0n-pins {
			rockchip,pins =
				/* psram_spi_cs0n */
				<0 RK_PA4 4 &pcfg_pull_none>;
		};
	};

	pwm0 {
		pwm0m0_ch0_pins: pwm0m0-ch0-pins {
			rockchip,pins =
				/* pwm0m0_ch0 */
				<0 RK_PA1 1 &pcfg_pull_none>;
		};
		pwm0m0_ch1_pins: pwm0m0-ch1-pins {
			rockchip,pins =
				/* pwm0m0_ch1 */
				<0 RK_PA5 2 &pcfg_pull_none>;
		};
		pwm0m0_ch2_pins: pwm0m0-ch2-pins {
			rockchip,pins =
				/* pwm0m0_ch2 */
				<0 RK_PA6 2 &pcfg_pull_none>;
		};
		pwm0m0_ch3_pins: pwm0m0-ch3-pins {
			rockchip,pins =
				/* pwm0m0_ch3 */
				<0 RK_PA2 1 &pcfg_pull_none>;
		};

		pwm0m1_ch0_pins: pwm0m1-ch0-pins {
			rockchip,pins =
				/* pwm0m1_ch0 */
				<2 RK_PA0 3 &pcfg_pull_none>;
		};
		pwm0m1_ch1_pins: pwm0m1-ch1-pins {
			rockchip,pins =
				/* pwm0m1_ch1 */
				<2 RK_PA1 3 &pcfg_pull_none>;
		};
		pwm0m1_ch2_pins: pwm0m1-ch2-pins {
			rockchip,pins =
				/* pwm0m1_ch2 */
				<2 RK_PA2 3 &pcfg_pull_none>;
		};
		pwm0m1_ch3_pins: pwm0m1-ch3-pins {
			rockchip,pins =
				/* pwm0m1_ch3 */
				<2 RK_PB0 3 &pcfg_pull_none>;
		};

		pwm0m2_ch1_pins: pwm0m2-ch1-pins {
			rockchip,pins =
				/* pwm0m2_ch1 */
				<1 RK_PB7 1 &pcfg_pull_none>;
		};
		pwm0m2_ch2_pins: pwm0m2-ch2-pins {
			rockchip,pins =
				/* pwm0m2_ch2 */
				<1 RK_PC0 1 &pcfg_pull_none>;
		};
	};

	pwm1 {
		pwm1m0_ch0_pins: pwm1m0-ch0-pins {
			rockchip,pins =
				/* pwm1m0_ch0 */
				<0 RK_PB0 3 &pcfg_pull_none>;
		};
		pwm1m0_ch1_pins: pwm1m0-ch1-pins {
			rockchip,pins =
				/* pwm1m0_ch1 */
				<0 RK_PB1 3 &pcfg_pull_none>;
		};
		pwm1m0_ch2_pins: pwm1m0-ch2-pins {
			rockchip,pins =
				/* pwm1m0_ch2 */
				<0 RK_PB2 3 &pcfg_pull_none>;
		};
		pwm1m0_ch3_pins: pwm1m0-ch3-pins {
			rockchip,pins =
				/* pwm1m0_ch3 */
				<0 RK_PB3 3 &pcfg_pull_none>;
		};

		pwm1m1_ch0_pins: pwm1m1-ch0-pins {
			rockchip,pins =
				/* pwm1m1_ch0 */
				<2 RK_PA3 3 &pcfg_pull_none>;
		};
		pwm1m1_ch1_pins: pwm1m1-ch1-pins {
			rockchip,pins =
				/* pwm1m1_ch1 */
				<2 RK_PA4 3 &pcfg_pull_none>;
		};
		pwm1m1_ch2_pins: pwm1m1-ch2-pins {
			rockchip,pins =
				/* pwm1m1_ch2 */
				<2 RK_PA5 3 &pcfg_pull_none>;
		};
		pwm1m1_ch3_pins: pwm1m1-ch3-pins {
			rockchip,pins =
				/* pwm1m1_ch3 */
				<2 RK_PB1 3 &pcfg_pull_none>;
		};
	};

	pwm2 {
		pwm2m0_ch0_pins: pwm2m0-ch0-pins {
			rockchip,pins =
				/* pwm2m0_ch0 */
				<1 RK_PB0 4 &pcfg_pull_none>;
		};
		pwm2m0_ch1_pins: pwm2m0-ch1-pins {
			rockchip,pins =
				/* pwm2m0_ch1 */
				<1 RK_PA7 4 &pcfg_pull_none>;
		};
		pwm2m0_ch2_pins: pwm2m0-ch2-pins {
			rockchip,pins =
				/* pwm2m0_ch2 */
				<1 RK_PB4 4 &pcfg_pull_none>;
		};
		pwm2m0_ch3_pins: pwm2m0-ch3-pins {
			rockchip,pins =
				/* pwm2m0_ch3 */
				<1 RK_PB3 4 &pcfg_pull_none>;
		};

		pwm2m1_ch0_pins: pwm2m1-ch0-pins {
			rockchip,pins =
				/* pwm2m1_ch0 */
				<2 RK_PA6 3 &pcfg_pull_none>;
		};
		pwm2m1_ch1_pins: pwm2m1-ch1-pins {
			rockchip,pins =
				/* pwm2m1_ch1 */
				<2 RK_PA7 3 &pcfg_pull_none>;
		};
		pwm2m1_ch2_pins: pwm2m1-ch2-pins {
			rockchip,pins =
				/* pwm2m1_ch2 */
				<2 RK_PB2 3 &pcfg_pull_none>;
		};
		pwm2m1_ch3_pins: pwm2m1-ch3-pins {
			rockchip,pins =
				/* pwm2m1_ch3 */
				<2 RK_PB3 3 &pcfg_pull_none>;
		};
	};

	pwr {
		pwr_pins: pwr-pins {
			rockchip,pins =
				/* pwr_ctrl0 */
				<0 RK_PA3 1 &pcfg_pull_none>,
				/* pwr_ctrl1 */
				<0 RK_PA4 1 &pcfg_pull_none>;
		};
	};

	rtc_32k {
		rtc_32k_pins: rtc-32k-pins {
			rockchip,pins =
				/* rtc_32k_out */
				<0 RK_PA0 1 &pcfg_pull_none>;
		};
	};

	sai {
		sai_pins: sai-pins {
			rockchip,pins =
				/* sai_lrck */
				<2 RK_PB1 5 &pcfg_pull_none>,
				/* sai_mclk */
				<2 RK_PB0 5 &pcfg_pull_none>,
				/* sai_sclk */
				<2 RK_PA7 5 &pcfg_pull_none>,
				/* sai_sdi */
				<2 RK_PA6 5 &pcfg_pull_none>,
				/* sai_sdo */
				<2 RK_PB2 5 &pcfg_pull_none>;
		};
	};

	sdmmc0_pins: sdmmc0_pins {
		sdmmc0_bus4_pins: sdmmc0-bus4-pins {
			rockchip,pins =
				/* sdmmc0_d0 */
				<1 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d1 */
				<1 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d2 */
				<1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc0_d3 */
				<1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc0_clk_pins: sdmmc0-clk-pins {
			rockchip,pins =
				/* sdmmc0_clk */
				<1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc0_cmd_pins: sdmmc0-cmd-pins {
			rockchip,pins =
				/* sdmmc0_cmd */
				<1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc0_det_pins: sdmmc0-det-pins {
			rockchip,pins =
				/* sdmmc0_det */
				<1 RK_PA6 1 &pcfg_pull_up>;
		};
	};

	sdmmc1 {
		sdmmc1_bus4_pins: sdmmc1-bus4-pins {
			rockchip,pins =
				/* sdmmc1_d0 */
				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d1 */
				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d2 */
				<2 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
				/* sdmmc1_d3 */
				<2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1_clk_pins: sdmmc1-clk-pins {
			rockchip,pins =
				/* sdmmc1_clk */
				<2 RK_PA2 1 &pcfg_pull_up_drv_level_2>;
		};

		sdmmc1_cmd_pins: sdmmc1-cmd-pins {
			rockchip,pins =
				/* sdmmc1_cmd */
				<2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
		};
	};

	sdmmc0_testclk {
		sdmmc0_testclk_clk_pins: sdmmc0-testclk-clk-pins {
			rockchip,pins =
				/* sdmmc0_testclk_out */
				<1 RK_PA0 3 &pcfg_pull_up_drv_level_2>;
		};
	};

	sdmmc0_testdata {
		sdmmc0_testdata_out_pins: sdmmc0-testdata-out-pins {
			rockchip,pins =
				/* sdmmc0_testdata_out */
				<1 RK_PA3 3 &pcfg_pull_none>;
		};
	};

	sdmmc1_testclk {
		sdmmc1_testclk_clk_pins: sdmmc1-testclk-clk-pins {
			rockchip,pins =
				/* sdmmc1_testclk_out */
				<2 RK_PA6 7 &pcfg_pull_up_drv_level_2>;
		};
	};

	sdmmc1_testdata {
		sdmmc1_testdata_out_pins: sdmmc1-testdata-out-pins {
			rockchip,pins =
				/* sdmmc1_testdata_out */
				<2 RK_PA7 7 &pcfg_pull_none>;
		};
	};

	spi0 {
		spi0m0_clk_pins: spi0m0-clk-pins {
			rockchip,pins =
				/* spi0_clk_m0 */
				<2 RK_PB0 2 &pcfg_pull_none>,
				/* spi0_miso_m0 */
				<2 RK_PB3 2 &pcfg_pull_none>,
				/* spi0_mosi_m0 */
				<2 RK_PB1 2 &pcfg_pull_none>;
		};

		spi0m0_cs0_pins: spi0m0-cs0-pins {
			rockchip,pins =
				/* spi0_cs0n_m0 */
				<2 RK_PB2 2 &pcfg_pull_none>;
		};

		spi0m0_cs1_pins: spi0m0-cs1-pins {
			rockchip,pins =
				/* spi0_cs1n_m0 */
				<2 RK_PA7 2 &pcfg_pull_none>;
		};

		spi0m1_clk_pins: spi0m1-clk-pins {
			rockchip,pins =
				/* spi0_clk_m1 */
				<2 RK_PA2 5 &pcfg_pull_none>,
				/* spi0_miso_m1 */
				<2 RK_PA4 5 &pcfg_pull_none>,
				/* spi0_mosi_m1 */
				<2 RK_PA1 5 &pcfg_pull_none>;
		};

		spi0m1_cs0_pins: spi0m1-cs0-pins {
			rockchip,pins =
				/* spi0_cs0n_m1 */
				<2 RK_PA3 5 &pcfg_pull_none>;
		};

		spi0m1_cs1_pins: spi0m1-cs1-pins {
			rockchip,pins =
				/* spi0_cs1n_m1 */
				<2 RK_PA0 5 &pcfg_pull_none>;
		};
	};

	uart0 {
		uart0m0_xfer_pins: uart0m0-xfer-pins {
			rockchip,pins =
				/* uart0_rx_m0 */
				<0 RK_PA6 1 &pcfg_pull_up>,
				/* uart0_tx_m0 */
				<0 RK_PA5 1 &pcfg_pull_up>;
		};

		uart0m1_xfer_pins: uart0m1-xfer-pins {
			rockchip,pins =
				/* uart0_rx_m1 */
				<0 RK_PB5 2 &pcfg_pull_up>,
				/* uart0_tx_m1 */
				<0 RK_PB4 2 &pcfg_pull_up>;
		};

		uart0m2_xfer_pins: uart0m2-xfer-pins {
			rockchip,pins =
				/* uart0_rx_m2 */
				<1 RK_PB3 2 &pcfg_pull_up>,
				/* uart0_tx_m2 */
				<1 RK_PB4 2 &pcfg_pull_up>;
		};
	};

	uart1 {
		uart1m0_xfer_pins: uart1m0-xfer-pins {
			rockchip,pins =
				/* uart1_rx_m0 */
				<0 RK_PB2 2 &pcfg_pull_up>,
				/* uart1_tx_m0 */
				<0 RK_PB3 2 &pcfg_pull_up>;
		};

		uart1m0_ctsn_pins: uart1m0-ctsn-pins {
			rockchip,pins =
				/* uart1m0_ctsn */
				<0 RK_PB5 5 &pcfg_pull_none>;
		};
		uart1m0_rtsn_pins: uart1m0-rtsn-pins {
			rockchip,pins =
				/* uart1m0_rtsn */
				<0 RK_PB4 5 &pcfg_pull_none>;
		};

		uart1m1_xfer_pins: uart1m1-xfer-pins {
			rockchip,pins =
				/* uart1_rx_m1 */
				<1 RK_PA7 2 &pcfg_pull_up>,
				/* uart1_tx_m1 */
				<1 RK_PB0 2 &pcfg_pull_up>;
		};

		uart1m1_ctsn_pins: uart1m1-ctsn-pins {
			rockchip,pins =
				/* uart1m1_ctsn */
				<1 RK_PB2 2 &pcfg_pull_none>;
		};
		uart1m1_rtsn_pins: uart1m1-rtsn-pins {
			rockchip,pins =
				/* uart1m1_rtsn */
				<1 RK_PB1 2 &pcfg_pull_none>;
		};

		uart1m2_xfer_pins: uart1m2-xfer-pins {
			rockchip,pins =
				/* uart1_rx_m2 */
				<2 RK_PA7 1 &pcfg_pull_up>,
				/* uart1_tx_m2 */
				<2 RK_PA6 1 &pcfg_pull_up>;
		};

		uart1m2_ctsn_pins: uart1m2-ctsn-pins {
			rockchip,pins =
				/* uart1m2_ctsn */
				<2 RK_PA5 2 &pcfg_pull_none>;
		};
		uart1m2_rtsn_pins: uart1m2-rtsn-pins {
			rockchip,pins =
				/* uart1m2_rtsn */
				<2 RK_PA4 2 &pcfg_pull_none>;
		};

		uart1m3_xfer_pins: uart1m3-xfer-pins {
			rockchip,pins =
				/* uart1_rx_m3 */
				<2 RK_PA3 2 &pcfg_pull_up>,
				/* uart1_tx_m3 */
				<2 RK_PA2 2 &pcfg_pull_up>;
		};

		uart1m3_ctsn_pins: uart1m3-ctsn-pins {
			rockchip,pins =
				/* uart1m3_ctsn */
				<2 RK_PA1 2 &pcfg_pull_none>;
		};
		uart1m3_rtsn_pins: uart1m3-rtsn-pins {
			rockchip,pins =
				/* uart1m3_rtsn */
				<2 RK_PA0 2 &pcfg_pull_none>;
		};
	};

	uart2 {
		uart2m0_xfer_pins: uart2m0-xfer-pins {
			rockchip,pins =
				/* uart2_rx_m0 */
				<0 RK_PB1 2 &pcfg_pull_up>,
				/* uart2_tx_m0 */
				<0 RK_PB0 2 &pcfg_pull_up>;
		};

		uart2m0_ctsn_pins: uart2m0-ctsn-pins {
			rockchip,pins =
				/* uart2m0_ctsn */
				<0 RK_PB3 5 &pcfg_pull_none>;
		};
		uart2m0_rtsn_pins: uart2m0-rtsn-pins {
			rockchip,pins =
				/* uart2m0_rtsn */
				<0 RK_PB2 5 &pcfg_pull_none>;
		};

		uart2m1_xfer_pins: uart2m1-xfer-pins {
			rockchip,pins =
				/* uart2_rx_m1 */
				<2 RK_PB1 1 &pcfg_pull_up>,
				/* uart2_tx_m1 */
				<2 RK_PB0 1 &pcfg_pull_up>;
		};

		uart2m1_ctsn_pins: uart2m1-ctsn-pins {
			rockchip,pins =
				/* uart2m1_ctsn */
				<2 RK_PB3 1 &pcfg_pull_none>;
		};
		uart2m1_rtsn_pins: uart2m1-rtsn-pins {
			rockchip,pins =
				/* uart2m1_rtsn */
				<2 RK_PB2 1 &pcfg_pull_none>;
		};

		uart2m2_xfer_pins: uart2m2-xfer-pins {
			rockchip,pins =
				/* uart2_rx_m2 */
				<1 RK_PB6 3 &pcfg_pull_up>,
				/* uart2_tx_m2 */
				<1 RK_PB5 3 &pcfg_pull_up>;
		};

		uart2m2_ctsn_pins: uart2m2-ctsn-pins {
			rockchip,pins =
				/* uart2m2_ctsn */
				<1 RK_PC0 3 &pcfg_pull_none>;
		};
		uart2m2_rtsn_pins: uart2m2-rtsn-pins {
			rockchip,pins =
				/* uart2m2_rtsn */
				<1 RK_PB7 3 &pcfg_pull_none>;
		};
	};
};

/*
 * This part is edited handly.
 */
&pinctrl {
	sdmmc0_pins: sdmmc0_pins {
		sdmmc0_idle_pins: sdmmc0-idle-pins {
			rockchip,pins =
				<1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_down>,
				<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>,
				<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>,
				<1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>,
				<1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_down>,
				<1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
		};
	};
};