268 lines
7.2 KiB
C
268 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _ASM_ARCH_CRU_RV1103B_H
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#define _ASM_ARCH_CRU_RV1103B_H
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#include <common.h>
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define RC_OSC_HZ (125 * MHz)
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#define GPLL_HZ (1188 * MHz)
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/* RV1103B pll id */
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enum rv1103b_pll_id {
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GPLL,
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PLL_COUNT,
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};
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struct rv1103b_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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struct rv1103b_clk_priv {
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struct rv1103b_cru *cru;
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struct rv1103b_grf *grf;
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ulong gpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rv1103b_grf_clk_priv {
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struct rv1103b_grf *grf;
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};
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struct rv1103b_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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struct rv1103b_cru {
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unsigned int reserved0[192];
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unsigned int peri_clksel_con[4];
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unsigned int reserved1[316];
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unsigned int peri_clkgate_con[12];
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unsigned int reserved2[116];
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unsigned int peri_softrst_con[12];
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unsigned int reserved3[15924];
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unsigned int vepu_clksel_con[3];
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unsigned int reserved4[317];
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unsigned int vepu_clkgate_con[1];
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unsigned int reserved5[127];
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unsigned int vepu_softrst_con[1];
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unsigned int reserved6[15935];
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unsigned int npu_clksel_con[3];
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unsigned int reserved7[317];
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unsigned int npu_clkgate_con[1];
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unsigned int reserved8[127];
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unsigned int npu_softrst_con[1];
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unsigned int reserved9[15935];
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unsigned int vi_clksel_con[1];
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unsigned int reserved10[319];
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unsigned int vi_clkgate_con[3];
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unsigned int reserved11[125];
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unsigned int vi_softrst_con[3];
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unsigned int reserved12[15933];
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unsigned int core_clksel_con[3];
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unsigned int reserved13[16381];
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unsigned int ddr_clksel_con[1];
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unsigned int reserved14[16207];
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struct rv1103b_pll pll[2];
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unsigned int reserved15[128];
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unsigned int mode;
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unsigned int reserved16[31];
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unsigned int clksel_con[42];
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unsigned int reserved17[278];
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unsigned int clkgate_con[7];
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unsigned int reserved18[121];
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unsigned int softrst_con[1];
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unsigned int reserved19[127];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int reserved20[15803];
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unsigned int pmu_clksel_con[3];
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unsigned int reserved21[317];
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unsigned int pmu_clkgate_con[3];
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unsigned int reserved22[125];
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unsigned int pmu_softrst_con[3];
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unsigned int reserved23[15933];
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unsigned int pmu1_clksel_con[1];
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unsigned int reserved24[319];
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unsigned int pmu1_clkgate_con[2];
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unsigned int reserved25[126];
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unsigned int pmu1_softrst_con[2];
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};
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check_member(rv1103b_cru, pmu1_softrst_con[1], 0x80a04);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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#define RV1103B_TOPCRU_BASE 0x60000
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#define RV1103B_PERICRU_BASE 0x0
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#define RV1103B_VICRU_BASE 0x30000
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#define RV1103B_NPUCRU_BASE 0x20000
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#define RV1103B_CORECRU_BASE 0x40000
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#define RV1103B_VEPUCRU_BASE 0x10000
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#define RV1103B_DDRCRU_BASE 0x50000
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#define RV1103B_SUBDDRCRU_BASE 0x58000
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#define RV1103B_PMUCRU_BASE 0x70000
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#define RV1103B_PMU1CRU_BASE 0x80000
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#define RV1103B_CRU_BASE 0x20000000
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#define RV1103B_PLL_CON(x) ((x) * 0x4 + RV1103B_TOPCRU_BASE)
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#define RV1103B_MODE_CON (0x280 + RV1103B_TOPCRU_BASE)
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#define RV1103B_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RV1103B_TOPCRU_BASE)
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#define RV1103B_SUBDDRMODE_CON (0x280 + RV1103B_SUBDDRCRU_BASE)
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enum {
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/* CORECRU_CLK_SEL0_CON */
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CLK_CORE_SRC_SEL_SHIFT = 1,
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CLK_CORE_SRC_SEL_MASK = 0x1 << CLK_CORE_SRC_SEL_SHIFT,
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CLK_CORE_SRC_SEL_GPLL = 0,
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CLK_CORE_SRC_SEL_PVTPLL,
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/* CRU_PERI_CLK_SEL0_CON */
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CLK_TSADC_TSEN_DIV_SHIFT = 10,
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CLK_TSADC_TSEN_DIV_MASK = 0x1f << CLK_TSADC_TSEN_DIV_SHIFT,
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CLK_TSADC_DIV_SHIFT = 4,
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CLK_TSADC_DIV_MASK = 0x1f << CLK_TSADC_DIV_SHIFT,
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PCLK_PERI_DIV_SHIFT = 0,
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PCLK_PERI_DIV_MASK = 0x3 << PCLK_PERI_DIV_SHIFT,
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/* CRU_PERI_CLK_SEL1_CON */
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CLK_SARADC_DIV_SHIFT = 0,
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CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
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/* CRU_CLK_SEL5_CON */
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CLK_UART2_SRC_DIV_SHIFT = 10,
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CLK_UART2_SRC_DIV_MASK = 0x1f << CLK_UART2_SRC_DIV_SHIFT,
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CLK_UART1_SRC_DIV_SHIFT = 5,
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CLK_UART1_SRC_DIV_MASK = 0x1f << CLK_UART1_SRC_DIV_SHIFT,
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CLK_UART0_SRC_DIV_SHIFT = 0,
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CLK_UART0_SRC_DIV_MASK = 0x1f << CLK_UART0_SRC_DIV_SHIFT,
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/* CRU_CLK_SEL10_CON */
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CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
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CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
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CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
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CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
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/* CRU_CLK_SEL31_CON */
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CLK_EMMC_SEL_SHIFT = 15,
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CLK_EMMC_SEL_MASK = 0x1 << CLK_EMMC_SEL_SHIFT,
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ACLK_PERI_SEL_SHIFT = 10,
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ACLK_PERI_SEL_MASK = 0x3 << ACLK_PERI_SEL_SHIFT,
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ACLK_PERI_SEL_600M = 0,
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ACLK_PERI_SEL_480M,
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ACLK_PERI_SEL_400M,
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LSCLK_PERI_SEL_SHIFT = 9,
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LSCLK_PERI_SEL_MASK = 0x1 << LSCLK_PERI_SEL_SHIFT,
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LSCLK_PERI_SEL_300M = 0,
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LSCLK_PERI_SEL_200M,
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CLK_EMMC_DIV_SHIFT = 0,
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CLK_EMMC_DIV_MASK = 0xff << CLK_EMMC_DIV_SHIFT,
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/* CRU_CLK_SEL32_CON */
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CLK_SDMMC_SEL_SHIFT = 15,
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CLK_SDMMC_SEL_MASK = 0x1 << CLK_SDMMC_SEL_SHIFT,
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CLK_MMC_SEL_GPLL = 0,
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CLK_MMC_SEL_OSC,
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CLK_UART2_SEL_SHIFT = 12,
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CLK_UART2_SEL_MASK = 3 << CLK_UART2_SEL_SHIFT,
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CLK_UART1_SEL_SHIFT = 10,
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CLK_UART1_SEL_MASK = 3 << CLK_UART1_SEL_SHIFT,
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CLK_UART0_SEL_SHIFT = 8,
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CLK_UART0_SEL_MASK = 3 << CLK_UART0_SEL_SHIFT,
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CLK_UART_SEL_SRC = 0,
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CLK_UART_SEL_FRAC,
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CLK_UART_SEL_OSC,
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CLK_SDMMC_DIV_SHIFT = 0,
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CLK_SDMMC_DIV_MASK = 0xff << CLK_SDMMC_DIV_SHIFT,
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/* CRU_CLK_SEL33_CON */
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CLK_SFC_SEL_SHIFT = 15,
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CLK_SFC_SEL_MASK = 0x1 << CLK_SFC_SEL_SHIFT,
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CLK_SFC_DIV_SHIFT = 0,
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CLK_SFC_DIV_MASK = 0xff << CLK_SFC_DIV_SHIFT,
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/* CRU_CLK_SEL34_CON */
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CLK_PWM2_SEL_SHIFT = 14,
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CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT,
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CLK_PWM1_SEL_SHIFT = 13,
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CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT,
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CLK_PWM0_SEL_SHIFT = 12,
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CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT,
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CLK_PWM_SEL_100M = 0,
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CLK_PWM_SEL_24M,
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CLK_SPI0_SEL_SHIFT = 2,
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CLK_SPI0_SEL_MASK = 3 << CLK_SPI0_SEL_SHIFT,
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CLK_SPI0_SEL_200M = 0,
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CLK_SPI0_SEL_100M,
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CLK_SPI0_SEL_50M,
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CLK_SPI0_SEL_24M,
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CLK_I2C1_SEL_SHIFT = 1,
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CLK_I2C1_SEL_MASK = 0x1 << CLK_I2C1_SEL_SHIFT,
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CLK_I2C0_SEL_SHIFT = 0,
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CLK_I2C0_SEL_MASK = 0x1 << CLK_I2C0_SEL_SHIFT,
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CLK_I2C_SEL_100M = 0,
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CLK_I2C_SEL_24M,
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/* CRU_CLK_SEL35_CON */
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CLK_PKA_CRYPTO_SEL_SHIFT = 4,
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CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
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CLK_CORE_CRYPTO_SEL_SHIFT = 2,
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CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
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CLK_CORE_CRYPTO_SEL_300M = 0,
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CLK_CORE_CRYPTO_SEL_200M,
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CLK_CORE_CRYPTO_SEL_100M,
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DCLK_DECOM_SEL_SHIFT = 0,
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DCLK_DECOM_SEL_MASK = 0x3 << DCLK_DECOM_SEL_SHIFT,
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DCLK_DECOM_SEL_480M = 0,
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DCLK_DECOM_SEL_400M,
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DCLK_DECOM_SEL_300M,
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/* CRU_CLK_SEL37_CON */
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CLK_CORE_GPLL_DIV_SHIFT = 13,
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CLK_CORE_GPLL_DIV_MASK = 0x7 << CLK_CORE_GPLL_DIV_SHIFT,
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CLK_CORE_GPLL_SEL_SHIFT = 12,
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CLK_CORE_GPLL_SEL_MASK = 0x1 << CLK_CORE_GPLL_SEL_SHIFT,
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CLK_CORE_GPLL_SEL_GPLL = 0,
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CLK_CORE_GPLL_SEL_OSC,
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/* CRU_PMU_CLK_SEL2_CON */
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LSCLK_PMU_SEL_SHIFT = 4,
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LSCLK_PMU_SEL_MASK = 0x1 << LSCLK_PMU_SEL_SHIFT,
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LSCLK_PMU_SEL_24M = 0,
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LSCLK_PMU_SEL_RC_OSC,
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LSCLK_PMU_DIV_SHIFT = 0,
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LSCLK_PMU_DIV_MASK = 0x3 << LSCLK_PMU_DIV_SHIFT,
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};
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#endif
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