208 lines
14 KiB
C
208 lines
14 KiB
C
/*
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* (C) Copyright 2023 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_RK3506_H
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#define _ASM_ARCH_GRF_RK3506_H
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#include <common.h>
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/* grf register structure define */
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struct rk3506_grf_reg {
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uint32_t soc_con0; /* address offset: 0x0000 */
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uint32_t soc_con1; /* address offset: 0x0004 */
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uint32_t soc_con2; /* address offset: 0x0008 */
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uint32_t soc_con3; /* address offset: 0x000c */
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uint32_t soc_con4; /* address offset: 0x0010 */
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uint32_t soc_con5; /* address offset: 0x0014 */
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uint32_t soc_con6; /* address offset: 0x0018 */
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uint32_t soc_con7; /* address offset: 0x001c */
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uint32_t soc_con8; /* address offset: 0x0020 */
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uint32_t soc_con9; /* address offset: 0x0024 */
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uint32_t soc_con10; /* address offset: 0x0028 */
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uint32_t soc_con11; /* address offset: 0x002c */
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uint32_t reserved0030; /* address offset: 0x0030 */
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uint32_t soc_con13; /* address offset: 0x0034 */
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uint32_t soc_con14; /* address offset: 0x0038 */
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uint32_t soc_con15; /* address offset: 0x003c */
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uint32_t soc_con16; /* address offset: 0x0040 */
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uint32_t soc_con17; /* address offset: 0x0044 */
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uint32_t soc_con18; /* address offset: 0x0048 */
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uint32_t soc_con19; /* address offset: 0x004c */
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uint32_t soc_con20; /* address offset: 0x0050 */
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uint32_t soc_con21; /* address offset: 0x0054 */
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uint32_t soc_con22; /* address offset: 0x0058 */
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uint32_t soc_con23; /* address offset: 0x005c */
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uint32_t soc_con24; /* address offset: 0x0060 */
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uint32_t soc_con25; /* address offset: 0x0064 */
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uint32_t soc_con26; /* address offset: 0x0068 */
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uint32_t soc_con27; /* address offset: 0x006c */
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uint32_t soc_con28; /* address offset: 0x0070 */
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uint32_t soc_con29; /* address offset: 0x0074 */
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uint32_t soc_con30; /* address offset: 0x0078 */
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uint32_t soc_con31; /* address offset: 0x007c */
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uint32_t soc_con32; /* address offset: 0x0080 */
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uint32_t soc_con33; /* address offset: 0x0084 */
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uint32_t reserved0088; /* address offset: 0x0088 */
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uint32_t soc_con35; /* address offset: 0x008c */
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uint32_t soc_con36; /* address offset: 0x0090 */
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uint32_t soc_con37; /* address offset: 0x0094 */
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uint32_t soc_con38; /* address offset: 0x0098 */
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uint32_t soc_con39; /* address offset: 0x009c */
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uint32_t soc_con40; /* address offset: 0x00a0 */
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uint32_t soc_con41; /* address offset: 0x00a4 */
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uint32_t soc_con42; /* address offset: 0x00a8 */
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uint32_t soc_con43; /* address offset: 0x00ac */
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uint32_t reserved00b0[20]; /* address offset: 0x00b0 */
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uint32_t soc_status0; /* address offset: 0x0100 */
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uint32_t soc_status1; /* address offset: 0x0104 */
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uint32_t soc_status2; /* address offset: 0x0108 */
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uint32_t reserved010c; /* address offset: 0x010c */
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uint32_t ddr_status0; /* address offset: 0x0110 */
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uint32_t ddr_status1; /* address offset: 0x0114 */
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uint32_t usbphy_status; /* address offset: 0x0118 */
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uint32_t reserved011c[13]; /* address offset: 0x011c */
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uint32_t usbotg0_sig_detect_con; /* address offset: 0x0150 */
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uint32_t usbotg0_sig_detect_status; /* address offset: 0x0154 */
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uint32_t usbotg0_sig_detect_clr; /* address offset: 0x0158 */
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uint32_t usbotg0_vbusvalid_detect_con; /* address offset: 0x015c */
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uint32_t usbotg0_linestate_detect_con; /* address offset: 0x0160 */
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uint32_t usbotg0_disconnect_detect_con; /* address offset: 0x0164 */
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uint32_t usbotg0_bvalid_detect_con; /* address offset: 0x0168 */
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uint32_t usbotg0_id_detect_con; /* address offset: 0x016c */
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uint32_t usbotg1_sig_detect_con; /* address offset: 0x0170 */
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uint32_t usbotg1_sig_detect_status; /* address offset: 0x0174 */
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uint32_t usbotg1_sig_detect_clr; /* address offset: 0x0178 */
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uint32_t usbotg1_vbusvalid_detect_con; /* address offset: 0x017c */
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uint32_t usbotg1_linestate_detect_con; /* address offset: 0x0180 */
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uint32_t usbotg1_disconnect_detect_con; /* address offset: 0x0184 */
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uint32_t usbotg1_bvalid_detect_con; /* address offset: 0x0188 */
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uint32_t usbotg1_id_detect_con; /* address offset: 0x018c */
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uint32_t reserved0190[4]; /* address offset: 0x0190 */
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uint32_t mac0_mcgr_ack; /* address offset: 0x01a0 */
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uint32_t mac1_mcgr_ack; /* address offset: 0x01a4 */
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uint32_t reserved01a8[22]; /* address offset: 0x01a8 */
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uint32_t os_reg0; /* address offset: 0x0200 */
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uint32_t os_reg1; /* address offset: 0x0204 */
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uint32_t os_reg2; /* address offset: 0x0208 */
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uint32_t os_reg3; /* address offset: 0x020c */
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uint32_t os_reg4; /* address offset: 0x0210 */
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uint32_t os_reg5; /* address offset: 0x0214 */
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uint32_t os_reg6; /* address offset: 0x0218 */
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uint32_t os_reg7; /* address offset: 0x021c */
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uint32_t os_reg8; /* address offset: 0x0220 */
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uint32_t os_reg9; /* address offset: 0x0224 */
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uint32_t os_reg10; /* address offset: 0x0228 */
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uint32_t os_reg11; /* address offset: 0x022c */
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uint32_t reserved0230[52]; /* address offset: 0x0230 */
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uint32_t soc_version; /* address offset: 0x0300 */
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};
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check_member(rk3506_grf_reg, soc_version, 0x0300);
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/* grf_core register structure define */
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struct rk3506_grf_core_reg {
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uint32_t pvtpll_con0_l; /* address offset: 0x0000 */
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uint32_t pvtpll_con0_h; /* address offset: 0x0004 */
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uint32_t pvtpll_con1; /* address offset: 0x0008 */
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uint32_t pvtpll_con2; /* address offset: 0x000c */
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uint32_t pvtpll_con3; /* address offset: 0x0010 */
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uint32_t pvtpll_osc_cnt; /* address offset: 0x0014 */
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uint32_t pvtpll_osc_cnt_avg; /* address offset: 0x0018 */
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uint32_t reserved001c[17]; /* address offset: 0x001c */
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uint32_t cpu_status; /* address offset: 0x0060 */
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uint32_t cpu_con0; /* address offset: 0x0064 */
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uint32_t cpu_con1; /* address offset: 0x0068 */
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uint32_t cpu_mem_con0; /* address offset: 0x006c */
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uint32_t reserved0070[5]; /* address offset: 0x0070 */
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uint32_t soc_con0; /* address offset: 0x0084 */
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uint32_t soc_con1; /* address offset: 0x0088 */
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uint32_t soc_con2; /* address offset: 0x008c */
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uint32_t soc_con3; /* address offset: 0x0090 */
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uint32_t soc_con4; /* address offset: 0x0094 */
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uint32_t soc_con5; /* address offset: 0x0098 */
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};
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check_member(rk3506_grf_core_reg, soc_con5, 0x0098);
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/* grf_pmu register structure define */
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struct rk3506_grf_pmu_reg {
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uint32_t soc_con0; /* address offset: 0x0000 */
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uint32_t soc_con1; /* address offset: 0x0004 */
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uint32_t soc_con2; /* address offset: 0x0008 */
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uint32_t soc_con3; /* address offset: 0x000c */
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uint32_t soc_con4; /* address offset: 0x0010 */
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uint32_t soc_con5; /* address offset: 0x0014 */
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uint32_t soc_con6; /* address offset: 0x0018 */
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uint32_t soc_con7; /* address offset: 0x001c */
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uint32_t soc_con8; /* address offset: 0x0020 */
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uint32_t soc_con9; /* address offset: 0x0024 */
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uint32_t soc_con10; /* address offset: 0x0028 */
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uint32_t soc_con11; /* address offset: 0x002c */
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uint32_t soc_con12; /* address offset: 0x0030 */
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uint32_t soc_con13; /* address offset: 0x0034 */
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uint32_t soc_con14; /* address offset: 0x0038 */
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uint32_t soc_con15; /* address offset: 0x003c */
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uint32_t soc_con16; /* address offset: 0x0040 */
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uint32_t soc_con17; /* address offset: 0x0044 */
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uint32_t soc_con18; /* address offset: 0x0048 */
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uint32_t reserved004c[45]; /* address offset: 0x004c */
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uint32_t soc_status; /* address offset: 0x0100 */
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uint32_t reserved0104[63]; /* address offset: 0x0104 */
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uint32_t os_reg0; /* address offset: 0x0200 */
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uint32_t os_reg1; /* address offset: 0x0204 */
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uint32_t os_reg2; /* address offset: 0x0208 */
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uint32_t os_reg3; /* address offset: 0x020c */
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uint32_t os_reg4; /* address offset: 0x0210 */
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uint32_t os_reg5; /* address offset: 0x0214 */
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uint32_t os_reg6; /* address offset: 0x0218 */
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uint32_t os_reg7; /* address offset: 0x021c */
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uint32_t os_reg8; /* address offset: 0x0220 */
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uint32_t os_reg9; /* address offset: 0x0224 */
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uint32_t os_reg10; /* address offset: 0x0228 */
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uint32_t os_reg11; /* address offset: 0x022c */
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uint32_t rstfunc_status; /* address offset: 0x0230 */
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uint32_t rstfunc_clr; /* address offset: 0x0234 */
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uint32_t reserved0238[882]; /* address offset: 0x0238 */
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uint32_t mcu_iso_con0; /* address offset: 0x1000 */
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uint32_t mcu_iso_con1; /* address offset: 0x1004 */
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uint32_t mcu_iso_con2; /* address offset: 0x1008 */
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uint32_t mcu_iso_con3; /* address offset: 0x100c */
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uint32_t mcu_iso_con4; /* address offset: 0x1010 */
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uint32_t mcu_iso_con5; /* address offset: 0x1014 */
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uint32_t mcu_iso_con6; /* address offset: 0x1018 */
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uint32_t mcu_iso_con7; /* address offset: 0x101c */
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uint32_t mcu_iso_con8; /* address offset: 0x1020 */
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uint32_t mcu_iso_con9; /* address offset: 0x1024 */
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uint32_t mcu_iso_con10; /* address offset: 0x1028 */
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uint32_t mcu_iso_con11; /* address offset: 0x102c */
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uint32_t reserved1030[244]; /* address offset: 0x1030 */
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uint32_t mcu_iso_ddr_con0; /* address offset: 0x1400 */
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uint32_t mcu_iso_ddr_con1; /* address offset: 0x1404 */
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uint32_t reserved1408[62]; /* address offset: 0x1408 */
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uint32_t mcu_iso_lock; /* address offset: 0x1500 */
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uint32_t reserved1504[703]; /* address offset: 0x1504 */
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uint32_t cpu_iso_con0; /* address offset: 0x2000 */
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uint32_t cpu_iso_con1; /* address offset: 0x2004 */
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uint32_t cpu_iso_con2; /* address offset: 0x2008 */
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uint32_t cpu_iso_con3; /* address offset: 0x200c */
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uint32_t cpu_iso_con4; /* address offset: 0x2010 */
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uint32_t cpu_iso_con5; /* address offset: 0x2014 */
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uint32_t cpu_iso_con6; /* address offset: 0x2018 */
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uint32_t cpu_iso_con7; /* address offset: 0x201c */
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uint32_t cpu_iso_con8; /* address offset: 0x2020 */
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uint32_t cpu_iso_con9; /* address offset: 0x2024 */
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uint32_t cpu_iso_con10; /* address offset: 0x2028 */
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uint32_t cpu_iso_con11; /* address offset: 0x202c */
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uint32_t reserved2030[244]; /* address offset: 0x2030 */
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uint32_t cpu_iso_ddr_con0; /* address offset: 0x2400 */
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uint32_t cpu_iso_ddr_con1; /* address offset: 0x2404 */
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uint32_t reserved2408[62]; /* address offset: 0x2408 */
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uint32_t cpu_iso_lock; /* address offset: 0x2500 */
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};
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check_member(rk3506_grf_pmu_reg, cpu_iso_lock, 0x2500);
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#endif /* _ASM_ARCH_GRF_RK3506_H */
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