222 lines
15 KiB
C
222 lines
15 KiB
C
/*
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* (C) Copyright 2024 Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_GRF_RK3506_H
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#define _ASM_ARCH_GRF_RK3506_H
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#include <common.h>
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/* gpio0_ioc register structure define */
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struct rk3506_gpio0_ioc_reg {
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uint32_t gpio0a_iomux_sel_0; /* address offset: 0x0000 */
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uint32_t gpio0a_iomux_sel_1; /* address offset: 0x0004 */
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uint32_t gpio0b_iomux_sel_0; /* address offset: 0x0008 */
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uint32_t gpio0b_iomux_sel_1; /* address offset: 0x000c */
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uint32_t gpio0c_iomux_sel_0; /* address offset: 0x0010 */
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uint32_t gpio0c_iomux_sel_1; /* address offset: 0x0014 */
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uint32_t reserved0018[58]; /* address offset: 0x0018 */
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uint32_t gpio0a_ds_0; /* address offset: 0x0100 */
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uint32_t gpio0a_ds_1; /* address offset: 0x0104 */
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uint32_t gpio0a_ds_2; /* address offset: 0x0108 */
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uint32_t gpio0a_ds_3; /* address offset: 0x010c */
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uint32_t gpio0b_ds_0; /* address offset: 0x0110 */
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uint32_t gpio0b_ds_1; /* address offset: 0x0114 */
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uint32_t gpio0b_ds_2; /* address offset: 0x0118 */
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uint32_t gpio0b_ds_3; /* address offset: 0x011c */
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uint32_t gpio0c_ds_0; /* address offset: 0x0120 */
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uint32_t gpio0c_ds_1; /* address offset: 0x0124 */
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uint32_t gpio0c_ds_2; /* address offset: 0x0128 */
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uint32_t gpio0c_ds_3; /* address offset: 0x012c */
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uint32_t reserved0130[52]; /* address offset: 0x0130 */
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uint32_t gpio0a_pull; /* address offset: 0x0200 */
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uint32_t gpio0b_pull; /* address offset: 0x0204 */
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uint32_t gpio0c_pull; /* address offset: 0x0208 */
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uint32_t reserved020c[61]; /* address offset: 0x020c */
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uint32_t gpio0a_ie; /* address offset: 0x0300 */
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uint32_t gpio0b_ie; /* address offset: 0x0304 */
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uint32_t gpio0c_ie; /* address offset: 0x0308 */
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uint32_t reserved030c[61]; /* address offset: 0x030c */
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uint32_t gpio0a_smt; /* address offset: 0x0400 */
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uint32_t gpio0b_smt; /* address offset: 0x0404 */
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uint32_t gpio0c_smt; /* address offset: 0x0408 */
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uint32_t reserved040c[61]; /* address offset: 0x040c */
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uint32_t gpio0a_sus; /* address offset: 0x0500 */
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uint32_t gpio0b_sus; /* address offset: 0x0504 */
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uint32_t gpio0c_sus; /* address offset: 0x0508 */
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uint32_t reserved050c[61]; /* address offset: 0x050c */
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uint32_t gpio0a_sl; /* address offset: 0x0600 */
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uint32_t gpio0b_sl; /* address offset: 0x0604 */
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uint32_t gpio0c_sl; /* address offset: 0x0608 */
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uint32_t reserved060c[61]; /* address offset: 0x060c */
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uint32_t gpio0a_od; /* address offset: 0x0700 */
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uint32_t gpio0b_od; /* address offset: 0x0704 */
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uint32_t gpio0c_od; /* address offset: 0x0708 */
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uint32_t reserved070c[61]; /* address offset: 0x070c */
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uint32_t gpio0_iddq; /* address offset: 0x0800 */
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uint32_t reserved0804[11]; /* address offset: 0x0804 */
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uint32_t gpio0d_con; /* address offset: 0x0830 */
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};
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check_member(rk3506_gpio0_ioc_reg, gpio0d_con, 0x0830);
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/* gpio1_ioc register structure define */
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struct rk3506_gpio1_ioc_reg {
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uint32_t reserved0000[8]; /* address offset: 0x0000 */
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uint32_t gpio1a_iomux_sel_0; /* address offset: 0x0020 */
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uint32_t gpio1a_iomux_sel_1; /* address offset: 0x0024 */
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uint32_t gpio1b_iomux_sel_0; /* address offset: 0x0028 */
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uint32_t gpio1b_iomux_sel_1; /* address offset: 0x002c */
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uint32_t gpio1c_iomux_sel_0; /* address offset: 0x0030 */
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uint32_t gpio1c_iomux_sel_1; /* address offset: 0x0034 */
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uint32_t gpio1d_iomux_sel_0; /* address offset: 0x0038 */
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uint32_t reserved003c[65]; /* address offset: 0x003c */
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uint32_t gpio1a_ds_0; /* address offset: 0x0140 */
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uint32_t gpio1a_ds_1; /* address offset: 0x0144 */
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uint32_t gpio1a_ds_2; /* address offset: 0x0148 */
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uint32_t gpio1a_ds_3; /* address offset: 0x014c */
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uint32_t gpio1b_ds_0; /* address offset: 0x0150 */
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uint32_t gpio1b_ds_1; /* address offset: 0x0154 */
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uint32_t gpio1b_ds_2; /* address offset: 0x0158 */
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uint32_t gpio1b_ds_3; /* address offset: 0x015c */
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uint32_t gpio1c_ds_0; /* address offset: 0x0160 */
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uint32_t gpio1c_ds_1; /* address offset: 0x0164 */
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uint32_t gpio1c_ds_2; /* address offset: 0x0168 */
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uint32_t gpio1c_ds_3; /* address offset: 0x016c */
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uint32_t gpio1d_ds_0; /* address offset: 0x0170 */
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uint32_t gpio1d_ds_1; /* address offset: 0x0174 */
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uint32_t reserved0178[38]; /* address offset: 0x0178 */
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uint32_t gpio1a_pull; /* address offset: 0x0210 */
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uint32_t gpio1b_pull; /* address offset: 0x0214 */
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uint32_t gpio1c_pull; /* address offset: 0x0218 */
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uint32_t gpio1d_pull; /* address offset: 0x021c */
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uint32_t reserved0220[60]; /* address offset: 0x0220 */
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uint32_t gpio1a_ie; /* address offset: 0x0310 */
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uint32_t gpio1b_ie; /* address offset: 0x0314 */
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uint32_t gpio1c_ie; /* address offset: 0x0318 */
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uint32_t gpio1d_ie; /* address offset: 0x031c */
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uint32_t reserved0320[60]; /* address offset: 0x0320 */
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uint32_t gpio1a_smt; /* address offset: 0x0410 */
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uint32_t gpio1b_smt; /* address offset: 0x0414 */
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uint32_t gpio1c_smt; /* address offset: 0x0418 */
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uint32_t gpio1d_smt; /* address offset: 0x041c */
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uint32_t reserved0420[60]; /* address offset: 0x0420 */
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uint32_t gpio1a_sus; /* address offset: 0x0510 */
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uint32_t gpio1b_sus; /* address offset: 0x0514 */
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uint32_t gpio1c_sus; /* address offset: 0x0518 */
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uint32_t gpio1d_sus; /* address offset: 0x051c */
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uint32_t reserved0520[60]; /* address offset: 0x0520 */
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uint32_t gpio1a_sl; /* address offset: 0x0610 */
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uint32_t gpio1b_sl; /* address offset: 0x0614 */
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uint32_t gpio1c_sl; /* address offset: 0x0618 */
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uint32_t gpio1d_sl; /* address offset: 0x061c */
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uint32_t reserved0620[60]; /* address offset: 0x0620 */
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uint32_t gpio1a_od; /* address offset: 0x0710 */
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uint32_t gpio1b_od; /* address offset: 0x0714 */
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uint32_t gpio1c_od; /* address offset: 0x0718 */
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uint32_t gpio1d_od; /* address offset: 0x071c */
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uint32_t reserved0720[60]; /* address offset: 0x0720 */
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uint32_t gpio1_iddq; /* address offset: 0x0810 */
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};
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check_member(rk3506_gpio1_ioc_reg, gpio1_iddq, 0x0810);
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/* gpio2_ioc register structure define */
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struct rk3506_gpio2_ioc_reg {
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uint32_t reserved0000[16]; /* address offset: 0x0000 */
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uint32_t gpio2a_iomux_sel_0; /* address offset: 0x0040 */
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uint32_t gpio2a_iomux_sel_1; /* address offset: 0x0044 */
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uint32_t gpio2b_iomux_sel_0; /* address offset: 0x0048 */
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uint32_t gpio2b_iomux_sel_1; /* address offset: 0x004c */
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uint32_t gpio2c_iomux_sel_0; /* address offset: 0x0050 */
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uint32_t reserved0054[75]; /* address offset: 0x0054 */
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uint32_t gpio2a_ds_0; /* address offset: 0x0180 */
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uint32_t gpio2a_ds_1; /* address offset: 0x0184 */
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uint32_t gpio2a_ds_2; /* address offset: 0x0188 */
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uint32_t reserved018c; /* address offset: 0x018c */
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uint32_t gpio2b_ds_0; /* address offset: 0x0190 */
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uint32_t gpio2b_ds_1; /* address offset: 0x0194 */
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uint32_t gpio2b_ds_2; /* address offset: 0x0198 */
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uint32_t gpio2b_ds_3; /* address offset: 0x019c */
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uint32_t gpio2c_ds_0; /* address offset: 0x01a0 */
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uint32_t reserved01a4[31]; /* address offset: 0x01a4 */
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uint32_t gpio2a_pull; /* address offset: 0x0220 */
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uint32_t gpio2b_pull; /* address offset: 0x0224 */
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uint32_t gpio2c_pull; /* address offset: 0x0228 */
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uint32_t reserved022c[61]; /* address offset: 0x022c */
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uint32_t gpio2a_ie; /* address offset: 0x0320 */
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uint32_t gpio2b_ie; /* address offset: 0x0324 */
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uint32_t gpio2c_ie; /* address offset: 0x0328 */
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uint32_t reserved032c[61]; /* address offset: 0x032c */
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uint32_t gpio2a_smt; /* address offset: 0x0420 */
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uint32_t gpio2b_smt; /* address offset: 0x0424 */
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uint32_t gpio2c_smt; /* address offset: 0x0428 */
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uint32_t reserved042c[61]; /* address offset: 0x042c */
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uint32_t gpio2a_sus; /* address offset: 0x0520 */
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uint32_t gpio2b_sus; /* address offset: 0x0524 */
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uint32_t gpio2c_sus; /* address offset: 0x0528 */
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uint32_t reserved052c[61]; /* address offset: 0x052c */
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uint32_t gpio2a_sl; /* address offset: 0x0620 */
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uint32_t gpio2b_sl; /* address offset: 0x0624 */
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uint32_t gpio2c_sl; /* address offset: 0x0628 */
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uint32_t reserved062c[61]; /* address offset: 0x062c */
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uint32_t gpio2a_od; /* address offset: 0x0720 */
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uint32_t gpio2b_od; /* address offset: 0x0724 */
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uint32_t gpio2c_od; /* address offset: 0x0728 */
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uint32_t reserved072c[61]; /* address offset: 0x072c */
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uint32_t gpio2_iddq; /* address offset: 0x0820 */
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};
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check_member(rk3506_gpio2_ioc_reg, gpio2_iddq, 0x0820);
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/* gpio3_ioc register structure define */
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struct rk3506_gpio3_ioc_reg {
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uint32_t reserved0000[24]; /* address offset: 0x0000 */
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uint32_t gpio3a_iomux_sel_0; /* address offset: 0x0060 */
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uint32_t gpio3a_iomux_sel_1; /* address offset: 0x0064 */
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uint32_t gpio3b_iomux_sel_0; /* address offset: 0x0068 */
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uint32_t gpio3b_iomux_sel_1; /* address offset: 0x006c */
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uint32_t reserved0070[84]; /* address offset: 0x0070 */
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uint32_t gpio3a_ds_0; /* address offset: 0x01c0 */
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uint32_t gpio3a_ds_1; /* address offset: 0x01c4 */
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uint32_t gpio3a_ds_2; /* address offset: 0x01c8 */
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uint32_t gpio3a_ds_3; /* address offset: 0x01cc */
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uint32_t gpio3b_ds_0; /* address offset: 0x01d0 */
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uint32_t gpio3b_ds_1; /* address offset: 0x01d4 */
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uint32_t gpio3b_ds_2; /* address offset: 0x01d8 */
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uint32_t gpio3b_ds_3; /* address offset: 0x01dc */
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uint32_t reserved01e0[20]; /* address offset: 0x01e0 */
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uint32_t gpio3a_pull; /* address offset: 0x0230 */
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uint32_t gpio3b_pull; /* address offset: 0x0234 */
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uint32_t reserved0238[62]; /* address offset: 0x0238 */
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uint32_t gpio3a_ie; /* address offset: 0x0330 */
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uint32_t gpio3b_ie; /* address offset: 0x0334 */
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uint32_t reserved0338[62]; /* address offset: 0x0338 */
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uint32_t gpio3a_smt; /* address offset: 0x0430 */
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uint32_t gpio3b_smt; /* address offset: 0x0434 */
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uint32_t reserved0438[62]; /* address offset: 0x0438 */
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uint32_t gpio3a_sus; /* address offset: 0x0530 */
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uint32_t gpio3b_sus; /* address offset: 0x0534 */
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uint32_t reserved0538[62]; /* address offset: 0x0538 */
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uint32_t gpio3a_sl; /* address offset: 0x0630 */
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uint32_t gpio3b_sl; /* address offset: 0x0634 */
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uint32_t reserved0638[62]; /* address offset: 0x0638 */
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uint32_t gpio3a_od; /* address offset: 0x0730 */
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uint32_t gpio3b_od; /* address offset: 0x0734 */
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uint32_t reserved0738[58]; /* address offset: 0x0738 */
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uint32_t gpio3_iddq; /* address offset: 0x0820 */
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};
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check_member(rk3506_gpio3_ioc_reg, gpio3_iddq, 0x0820);
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/* gpio4_ioc register structure define */
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struct rk3506_gpio4_ioc_reg {
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uint32_t reserved0000[528]; /* address offset: 0x0000 */
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uint32_t saradc_con; /* address offset: 0x0840 */
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};
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check_member(rk3506_gpio4_ioc_reg, saradc_con, 0x0840);
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#endif /* _ASM_ARCH_GRF_RK3506_H */
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