378 lines
12 KiB
C
378 lines
12 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd.
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*/
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#ifndef __MACH_ROCKCHIP_RV1103B_PM_H
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#define __MACH_ROCKCHIP_RV1103B_PM_H
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#define RV1103B_WAKEUP_TO_SYSTEM_RESET 0
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#define RV1103B_PERICRU_OFFSET 0x0
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#define RV1103B_VENCCRU_OFFSET 0x10000
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#define RV1103B_NPUCRU_OFFSET 0x20000
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#define RV1103B_VICRU_OFFSET 0x30000
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#define RV1103B_CORECRU_OFFSET 0x40000
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#define RV1103B_DDRCRU_OFFSET 0x50000
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#define RV1103B_TOPCRU_OFFSET 0x60000
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#define RV1103B_PMU0CRU_OFFSET 0x70000
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#define RV1103B_PMU1CRU_OFFSET 0x80000
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#define RV1103B_VENCGRF_OFFSET 0x100000
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#define RV1103B_NPUGRF_OFFSET 0x110000
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#define RV1103B_VIGRF_OFFSET 0x120000
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#define RV1103B_COREGRF_OFFSET 0x130000
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#define RV1103B_DDRGRF_OFFSET 0x140000
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#define RV1103B_PERIGRF_OFFSET 0x150000
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#define RV1103B_PMUGRF_OFFSET 0x160000
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#define RV1103B_IOC3_OFFSET 0x170000
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#define RV1103B_IOC47_OFFSET 0x180000
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#define RV1103B_IOC6_OFFSET 0x1a0000
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#define RV1103B_IOC0_OFFSET 0x1b0000
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#define RV1103B_IOC1_OFFSET 0x1c0000
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#define RV1103B_PERISGRF_OFFSET 0x250000
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#define RV1103B_PMUSGRF_OFFSET 0x260000
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#define RV1103B_GIC_OFFSET 0x410000
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#define RV1103B_PVTPLL_CORE_OFFSET 0x460000
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#define RV1103B_HPTIMER_OFFSET 0x500000
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#define RV1103B_PMU_OFFSET 0x510000
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#define RV1103B_GPIO0_OFFSET 0x520000
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#define RV1103B_I2C0_OFFSET 0x530000
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#define RV1103B_UART0_OFFSET 0x540000
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#define RV1103B_PWM0_OFFSET 0x550000
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#define RV1103B_SPI2AHB_OFFSET 0x570000
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#define RV1103B_LPMCU_MBOX_OFFSET 0x580000
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#define RV1103B_FSPI1_CFG_OFFSET 0x5c0000
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#define RV1103B_WDTS_OFFSET 0x780000
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#define RV1103B_STIMER_OFFSET 0x7a0000
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#define RV1103B_NSTIMER_OFFSET 0x830000
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#define RV1103B_GPIO2_OFFSET 0x840000
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#define RV1103B_WDTNS_OFFSET 0x8d0000
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#define RV1103B_HPMCU_MBOX_OFFSET 0xa10000
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#define RV1103B_DDRC_OFFSET 0xc00000
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#define RV1103B_FW_DDR_OFFSET 0xc30000
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#define RV1103B_GPIO1_OFFSET 0xd80000
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#define RV1103B_PVTPLL_ISP_OFFSET 0xdc0000
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#define RV1103B_PVTPLL_VEPU_OFFSET 0xe00000
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#define RV1103B_PVTPLL_NPU_OFFSET 0xf80000
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#define RV1103B_SYSSRAM_OFFSET 0x10f6000
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#define RV1103B_PMUSRAM_OFFSET 0x10fe000
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#define RV1103B_DEV_REG_BASE 0x20000000
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#define RV1103B_DEV_REG_SIZE 0x1100000
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#define RV1103B_PMUSRAM_BASE \
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(RV1103B_DEV_REG_BASE + RV1103B_PMUSRAM_OFFSET)
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/* cru */
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#define RV1103B_CRU_PLL_CON(pll_id, i) (0x40 + (pll_id) * 0x20 + (i) * 4)
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#define RV1103B_CRU_MODE_CON00 0x280
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#define RV1103B_CRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_CRU_CLKSEL_CON_NUM 42
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#define RV1103B_CRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_CRU_GATE_CON_NUM 7
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#define RV1103B_CRU_SFTRST_CON(i) (0xa00 + (i) * 4)
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#define RV1103B_CRU_GLB_SRST_FST 0xc08
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#define RV1103B_CRU_GLB_RST_CON 0xc10
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#define CRU_PLLCON1_LOCK_STATUS BIT(10)
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#define CRU_PLLCON1_PWRDOWN BIT(13)
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#define RV1103B_PMU0CRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_PMU0CRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_PMU0CRU_GATE_CON_NUM 3
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#define RV1103B_PMU1CRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_PMU1CRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_PMU1CRU_GATE_CON_NUM 3
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#define RV1103B_PERICRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_PERICRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_PERICRU_GATE_CON_NUM 12
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#define RV1103B_NPUCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_NPUCRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_NPUCRU_GATE_CON_NUM 1
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#define RV1103B_VENCCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_VENCCRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_VENCCRU_GATE_CON_NUM 1
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#define RV1103B_VICRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_VICRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_VICRU_GATE_CON_NUM 3
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#define RV1103B_COERCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
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#define RV1103B_CORECRU_GATE_CON(i) (0x800 + (i) * 4)
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#define RV1103B_CORECRU_GATE_CON_NUM 2
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#define RV1103B_COERCRU_SFTRST_CON(i) (0xa00 + (i) * 4)
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/* grf */
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#define RV1103B_SYSGRF_PERI_CON(i) ((i) * 4)
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#define RV1103B_PMUGRF_SOC_CON(i) ((i) * 4)
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#define RV1103B_PMUGRF_OS_REG(i) (0x200 + (i) * 4)
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#define RV1103B_PMUSGRF_SOC_CON(i) ((i) * 4)
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#define RV1103B_DDRGRF_CON(i) ((i) * 0x4)
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/* pvtm */
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#define RV1103B_PVTM_CON(i) (0x4 + (i) * 4)
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#define RV1103B_PVTM_INTEN 0x70
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#define RV1103B_PVTM_INTSTS 0x74
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#define RV1103B_PVTM_STATUS(i) (0x80 + (i) * 4)
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#define RV1103B_PVTM_CALC_CNT 24000
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#define RV1103B_PVTM_TARGET_FREQ 32768
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/* gpio */
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#define RV1103B_GPIO_SWPORT_DR_L 0x0000
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#define RV1103B_GPIO_SWPORT_DR_H 0x0004
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#define RV1103B_GPIO_SWPORT_DDR_L 0x0008
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#define RV1103B_GPIO_SWPORT_DDR_H 0x000c
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#define RV1103B_GPIO_INT_EN_L 0x0010
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#define RV1103B_GPIO_INT_EN_H 0x0014
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#define RV1103B_GPIO_INT_MASK_L 0x0018
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#define RV1103B_GPIO_INT_MASK_H 0x001c
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#define RV1103B_GPIO_INT_TYPE_L 0x0020
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#define RV1103B_GPIO_INT_TYPE_H 0x0024
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#define RV1103B_GPIO_INT_POLARITY_L 0x0028
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#define RV1103B_GPIO_INT_POLARITY_H 0x002c
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#define RV1103B_GPIO_INT_BOTHEDGE_L 0x0030
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#define RV1103B_GPIO_INT_BOTHEDGE_H 0x0034
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#define RV1103B_GPIO_DEBOUNCE_L 0x0038
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#define RV1103B_GPIO_DEBOUNCE_H 0x003c
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#define RV1103B_GPIO_DBCLK_DIV_EN_L 0x0040
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#define RV1103B_GPIO_DBCLK_DIV_EN_H 0x0044
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#define RV1103B_GPIO_DBCLK_DIV_CON 0x0048
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#define RV1103B_GPIO_INT_STATUS 0x0050
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#define RV1103B_GPIO_INT_RAWSTATUS 0x0058
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/* pmu */
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#define RV1103B_PMU1_OFFSET 0x4000
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#define RV1103B_PMU2_OFFSET 0x8000
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#define RV1103B_PMU0_PWR_CON 0x0000
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#define RV1103B_PMU0_WAKEUP_INT_ST 0x000c
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#define RV1103B_PMU0_INFO_TX_CON 0x0030
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#define RV1103B_PMU1_VERSION_ID (RV1103B_PMU1_OFFSET + 0x000)
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#define RV1103B_PMU1_PWR_CON (RV1103B_PMU1_OFFSET + 0x004)
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#define RV1103B_PMU1_PWR_FSM (RV1103B_PMU1_OFFSET + 0x008)
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#define RV1103B_PMU1_INT_MASK_CON (RV1103B_PMU1_OFFSET + 0x00c)
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#define RV1103B_PMU1_WAKEUP_INT_CON (RV1103B_PMU1_OFFSET + 0x010)
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#define RV1103B_PMU1_WAKEUP_INT_ST (RV1103B_PMU1_OFFSET + 0x014)
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#define RV1103B_PMU1_WAKEUP_EDGE_CON (RV1103B_PMU1_OFFSET + 0x018)
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#define RV1103B_PMU1_WAKEUP_EDGE_ST (RV1103B_PMU1_OFFSET + 0x01c)
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#define RV1103B_PMU1_DDR_PWR_CON (RV1103B_PMU1_OFFSET + 0x020)
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#define RV1103B_PMU1_DDR_PWR_SFTCON (RV1103B_PMU1_OFFSET + 0x030)
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#define RV1103B_PMU1_DDR_PWR_FSM (RV1103B_PMU1_OFFSET + 0x040)
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#define RV1103B_PMU1_DDR_ST (RV1103B_PMU1_OFFSET + 0x044)
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#define RV1103B_PMU1_CRU_PWR_CON(i) (RV1103B_PMU1_OFFSET + 0x050 + (i) * 4)
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#define RV1103B_PMU1_CRU_PWR_SFTCON (RV1103B_PMU1_OFFSET + 0x058)
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#define RV1103B_PMU1_CRU_PWR_FSM (RV1103B_PMU1_OFFSET + 0x05c)
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#define RV1103B_PMU1_PLLPD_CON (RV1103B_PMU1_OFFSET + 0x060)
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#define RV1103B_PMU1_PLLPD_SFTCON (RV1103B_PMU1_OFFSET + 0x068)
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#define RV1103B_PMU1_PMIC_STABLE_CNT (RV1103B_PMU1_OFFSET + 0x080)
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#define RV1103B_PMU1_OSC_STABLE_CNT (RV1103B_PMU1_OFFSET + 0x084)
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#define RV1103B_PMU1_WAKEUP_RST_CLR_CNT (RV1103B_PMU1_OFFSET + 0x088)
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#define RV1103B_PMU1_PLL_LOCK_CNT (RV1103B_PMU1_OFFSET + 0x08c)
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#define RV1103B_PMU1_WAKEUP_TIMEOUT (RV1103B_PMU1_OFFSET + 0x094)
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#define RV1103B_PMU1_PWM_SWITCH_CNT (RV1103B_PMU1_OFFSET + 0x098)
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#define RV1103B_PMU1_SLEEP_CNT (RV1103B_PMU1_OFFSET + 0x09c)
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#define RV1103B_PMU2_SCU_PWR_CON (RV1103B_PMU2_OFFSET + 0x000)
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#define RV1103B_PMU2_SCU_PWR_SFTCON (RV1103B_PMU2_OFFSET + 0x004)
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#define RV1103B_PMU2_SCU_AUTO_PWR_CON (RV1103B_PMU2_OFFSET + 0x008)
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#define RV1103B_PMU2_SCU_PWR_FSM_STATUS (RV1103B_PMU2_OFFSET + 0x00c)
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#define RV1103B_PMU2_CPU_AUTO_PWR_CON (RV1103B_PMU2_OFFSET + 0x010)
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#define RV1103B_PMU2_CPU_PWR_SFTCON (RV1103B_PMU2_OFFSET + 0x014)
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#define RV1103B_PMU2_DBG_PWR_CON (RV1103B_PMU2_OFFSET + 0x018)
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#define RV1103B_PMU2_CLUSTER_PWR_ST (RV1103B_PMU2_OFFSET + 0x01c)
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#define RV1103B_PMU2_CLUSTER_IDLE_CON (RV1103B_PMU2_OFFSET + 0x020)
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#define RV1103B_PMU2_CLUSTER_IDLE_SFTCON (RV1103B_PMU2_OFFSET + 0x024)
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#define RV1103B_PMU2_SCU_STABLE_CNT (RV1103B_PMU2_OFFSET + 0x030)
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#define RV1103B_PMU2_SCU_PWRUP_CNT (RV1103B_PMU2_OFFSET + 0x034)
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#define RV1103B_PMU2_SCU_PWRDN_CNT (RV1103B_PMU2_OFFSET + 0x038)
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#define RV1103B_PMU2_SCU_VOLUP_CNT (RV1103B_PMU2_OFFSET + 0x03c)
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#define RV1103B_PMU2_SCU_VOLDN_CNT (RV1103B_PMU2_OFFSET + 0x040)
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#define RV1103B_PMU2_BUS_IDLE_CON (RV1103B_PMU2_OFFSET + 0x100)
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#define RV1103B_PMU2_BUS_IDLE_SFTCON (RV1103B_PMU2_OFFSET + 0x110)
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#define RV1103B_PMU2_BUS_IDLE_ACK (RV1103B_PMU2_OFFSET + 0x120)
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#define RV1103B_PMU2_BUS_IDLE_ST (RV1103B_PMU2_OFFSET + 0x128)
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#define RV1103B_PMU2_NOC_AUTO_CON (RV1103B_PMU2_OFFSET + 0x130)
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#define RV1103B_PMU2_NOC_AUTO_SFTCON (RV1103B_PMU2_OFFSET + 0x140)
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/* wdt */
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#define RV1103B_WDT_CR 0x0
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#define RV1103B_WDT_TORR 0x4
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#define RV1103B_WDT_CCVR 0x8
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#define RV1103B_WDT_CRR 0xc
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#define RV1103B_WDT_STAT 0x10
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#define RV1103B_WDT_EOI 0x14
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#define PMU_SUSPEND_MAGIC 0x02468ace
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#define PMU_RESUME_MAGIC 0x13579bdf
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/* mcu */
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#define RV1103B_MBOX_B2A_STATUS 0x2c
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#define RV1103B_MBOX_B2A_CMD_0 0x30
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#define RV1103B_HPMCU_MBOX_IRQ_AP 33
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#define RV1103B_HPMCU_BOOT_ADDR 0x40000
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#define RV1103B_MBOX_CMD_AP_SUSPEND 0x12345600
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#define RV1103B_MBOX_CMD_AP_RESUME 0x12345601
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#define RV1103B_SYS_IS_WKUP 0x87654300
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#ifndef __ASSEMBLER__
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extern unsigned long rkpm_bootdata_cpusp;
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extern unsigned long rkpm_bootdata_cpu_code;
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extern unsigned long rkpm_bootdata_l2ctlr_f;
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extern unsigned long rkpm_bootdata_l2ctlr;
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extern unsigned long rkpm_bootdata_ddr_code;
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extern unsigned long rkpm_bootdata_ddr_data;
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extern unsigned long rv1103b_bootram_sz;
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void rockchip_slp_cpu_resume(void);
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void rv1103b_rockchip_slp_cpu_resume(void);
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#ifdef CONFIG_PM_SLEEP
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void __init rockchip_suspend_init(void);
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#else
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static inline void rockchip_suspend_init(void)
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{
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}
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#endif
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enum rv1103b_pwr0_con {
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RV1103B_PMU_PWRMODE0_EN = 0,
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RV1103B_PMU1_PWR_BYPASS = 1,
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RV1103B_PMU1_BUS_BYPASS = 2,
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RV1103B_PMU1_PWRGT_EN = 8,
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RV1103B_PMU1_PWRGT_SFTEN = 9,
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RV1103B_PMU1_BUS_IDLE_EN = 11,
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RV1103B_PMU1_BUS_IDLE_SFTEN = 12,
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RV1103B_PMU1_BUS_AUTO = 13,
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};
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enum rv1103b_pwr1_con {
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RV1103B_PMU_PWRMODE1_EN = 0,
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RV1103B_PMU_SCU_BYPASS = 1,
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RV1103B_PMU_BUS_BYPASS = 4,
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RV1103B_PMU_DDR_BYPASS = 5,
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RV1103B_PMU_PWRGT_BYPASS = 6,
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RV1103B_PMU_CRU_BYPASS = 7,
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RV1103B_PMU_PDPMU1_BYPASS = 9,
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RV1103B_PMU_WFI_BYPASS = 12,
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RV1103B_PMU_SLP_CNT_EN = 13,
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};
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enum rv1103b_int_mask_con {
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RV1103B_PMU_GLB_INT_MASK = 0,
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};
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enum rv1103b_wakeup_init {
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RV1103B_PMU_WAKEUP_GPIO_INT = 0,
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RV1103B_PMU_WAKEUP_SDMMC0 = 1,
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RV1103B_PMU_WAKEUP_SDIO = 2,
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RV1103B_PMU_WAKEUP_USBDEV = 3,
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RV1103B_PMU_WAKEUP_UART0 = 4,
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RV1103B_PMU_WAKEUP_PWM0 = 5,
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RV1103B_PMU_WAKEUP_TIMER = 6,
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RV1103B_PMU_WAKEUP_HPTIMER = 7,
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RV1103B_PMU_WAKEUP_SYS_INT = 8,
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RV1103B_PMU_WAKEUP_AOV = 9,
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RV1103B_PMU_WAKEUP_TIMEOUT = 10,
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};
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enum rv1103b_ddr_pwr_con {
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RV1103B_PMU_DDR_SREF_C = 0,
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RV1103B_PMU_DDR_SREF_A = 1,
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RV1103B_PMU_DDRIO_RETON_ENTER = 2,
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RV1103B_PMU_DDRIO_RETON_EXIT = 5,
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RV1103B_PMU_DDRIO_RSTIOV_ENTER = 6,
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RV1103B_PMU_DDRIO_RSTIOV_EXIT = 7,
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RV1103B_PMU_DDRCTL_A_AUTO_GATING = 8,
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RV1103B_PMU_DDRCTL_C_AUTO_GATING = 9,
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RV1103B_PMU_DDRPHY_AUTO_GATING = 10,
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RV1103B_PMU_DDRIO_HZ_ENTER = 11,
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RV1103B_PMU_DDRIO_HZ_EXIT = 12,
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};
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enum rv1103b_cru_pwr_con0 {
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RV1103B_PMU_ALIVE_32K = 0,
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RV1103B_PMU_OSC_DIS = 1,
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RV1103B_PMU_WAKEUP_RST = 2,
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RV1103B_PMU_INPUT_CLAMP = 3,
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RV1103B_PMU_ALIVE_OSC_EN = 4,
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RV1103B_PMU_POWER_OFF = 5,
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RV1103B_PMU_PWM_SWITCH = 6,
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RV1103B_PMU_GPIO_IOE = 7,
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RV1103B_PMU_PWM_SWITCH_IOUT = 8,
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RV1103B_PMU_OFF_IO = 9,
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RV1103B_PWM_CLK_GT_PLL = 11,
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RV1103B_PWM_CLK_GT_OSC = 12,
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};
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enum rv1103b_cru_pwr_con1 {
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RV1103B_PMU_PERI_CLK_SRC_GT,
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RV1103B_PMU_VENC_CLK_SRC_GT,
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RV1103B_PMU_VI_CLK_SRC_GT = 0,
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RV1103B_PMU_NPU_CLK_SRC_GT,
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RV1103B_PMU_CORE_CLK_SRC_GT,
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RV1103B_PMU_DDR_CLK_SRC_GT,
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};
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enum rv1103b_scu_pwr_con {
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RV1103B_PMU_SCU_L2_FLUSH = 0,
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RV1103B_PMU_SCU_L2_IDLE = 1,
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RV1103B_PMU_SCU_PWRDN = 2,
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RV1103B_PMU_SCU_PWROFF = 3,
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RV1103B_PMU_CLST_CPU_PD = 5,
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RV1103B_PMU_SCU_VOL_GT = 6,
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RV1103B_PMU_CLST_CLK_SRC_GT = 7,
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};
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enum rv1103b_biu_idle_con {
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RV1103B_PMU_IDLE_REQ_MSCH = 0,
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RV1103B_PMU_IDLE_REQ_DDRC = 1,
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RV1103B_PMU_IDLE_REQ_PERI = 2,
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RV1103B_PMU_IDLE_REQ_VEPU = 3,
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RV1103B_PMU_IDLE_REQ_VI = 4,
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RV1103B_PMU_IDLE_REQ_CRU = 5,
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};
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enum rv1103b_scu_auto_pwr_con {
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RV1103B_SCU_AUTO_LP_EN = 0,
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RV1103B_SCU_AUTO_WKUP_EN = 1,
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RV1103B_SCU_AUTO_INT_MSK = 2,
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RV1103B_SCU_AUTO_SFT_WKUP = 3,
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};
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enum rv1103b_cpu_auto_pwr_con {
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RV1103B_CPU_AUTO_LP_EN = 0,
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RV1103B_CPU_AUTO_WKUP_EN = 1,
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RV1103B_CPU_AUTO_INT_MSK = 2,
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RV1103B_CPU_AUTO_SFT_WKUP = 3,
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};
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enum rv1103b_pllpd_con {
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RV1103B_PMU_GPLL_PD = 0,
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RV1103B_PMU_DPLL_PD = 1,
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};
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enum rv1103b_pllid {
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RV1103B_DPLL_ID = 0,
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RV1103B_GPLL_ID = 1,
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};
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#endif
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#endif /* __MACH_ROCKCHIP_RV1103B_PM_H */
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