92 lines
1.9 KiB
C
92 lines
1.9 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* (C) Copyright 2020 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dwc3-uboot.h>
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#include <usb.h>
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#include <linux/usb/phy-rockchip-naneng-combphy.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/cpu.h>
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#include <rockusb.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_USB_DWC3
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#define CRU_BASE 0xfdd20000
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#define CRU_SOFTRST_CON09 0x0424
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#define U3PHY_BASE 0xfe820000
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static struct dwc3_device dwc3_device_data = {
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.maximum_speed = USB_SPEED_SUPER,
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.base = 0xfcc00000,
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.dr_mode = USB_DR_MODE_PERIPHERAL,
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.index = 0,
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.dis_u2_susphy_quirk = 1,
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.dis_u1u2_quirk = 1,
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.usb2_phyif_utmi_width = 16,
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};
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int usb_gadget_handle_interrupts(int index)
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{
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dwc3_uboot_handle_interrupt(0);
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return 0;
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}
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bool rkusb_usb3_capable(void)
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{
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return true;
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}
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static void usb_reset_otg_controller(void)
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{
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writel(0x00100010, CRU_BASE + CRU_SOFTRST_CON09);
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mdelay(1);
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writel(0x00100000, CRU_BASE + CRU_SOFTRST_CON09);
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mdelay(1);
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}
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int board_usb_init(int index, enum usb_init_type init)
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{
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u32 ret = 0;
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usb_reset_otg_controller();
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#if defined(CONFIG_SUPPORT_USBPLUG)
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dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
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if (rkusb_switch_usb3_enabled()) {
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dwc3_device_data.maximum_speed = USB_SPEED_SUPER;
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ret = rockchip_combphy_usb3_uboot_init(U3PHY_BASE);
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if (ret) {
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rkusb_force_to_usb2(true);
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dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
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}
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}
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#else
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if (soc_is_rk3566()) {
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rkusb_force_to_usb2(true);
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dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
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} else {
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ret = rockchip_combphy_usb3_uboot_init(U3PHY_BASE);
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if (ret) {
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rkusb_force_to_usb2(true);
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dwc3_device_data.maximum_speed = USB_SPEED_HIGH;
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}
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}
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#endif
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return dwc3_uboot_init(&dwc3_device_data);
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}
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#if defined(CONFIG_SUPPORT_USBPLUG)
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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dwc3_uboot_exit(index);
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return 0;
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}
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#endif
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#endif
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