412 lines
9.2 KiB
C
412 lines
9.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2024 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static int rv1103b_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int iomux_num = (pin / 8);
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struct regmap *regmap;
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int reg, ret, mask;
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u8 bit;
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u32 data;
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debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
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if (bank->bank_num == 2 && pin >= 12)
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return 0;
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regmap = priv->regmap_base;
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reg = bank->iomux[iomux_num].offset;
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if ((pin % 8) >= 4)
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reg += 0x4;
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bit = (pin % 4) * 4;
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mask = 0xf;
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if (bank->recalced_mask & BIT(pin))
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rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
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data = (mask << (bit + 16));
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data |= (mux & mask) << bit;
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debug("iomux write reg = %x data = %x\n", reg, data);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RV1103B_DRV_BITS_PER_PIN 8
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#define RV1103B_DRV_PINS_PER_REG 2
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#define RV1103B_DRV_GPIO0_A_OFFSET 0x40100
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#define RV1103B_DRV_GPIO0_B_OFFSET 0x50110
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#define RV1103B_DRV_GPIO1_A01_OFFSET 0x140
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#define RV1103B_DRV_GPIO1_A67_OFFSET 0x1014C
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#define RV1103B_DRV_GPIO2_OFFSET 0x30180
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#define RV1103B_DRV_GPIO2_SARADC_OFFSET 0x3080C
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static int rv1103b_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int ret = 0;
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*regmap = priv->regmap_base;
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switch (bank->bank_num) {
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case 0:
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if (pin_num < 7)
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*reg = RV1103B_DRV_GPIO0_A_OFFSET;
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else if (pin_num > 7 && pin_num < 14)
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*reg = RV1103B_DRV_GPIO0_B_OFFSET - 0x10;
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else
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ret = -EINVAL;
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break;
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case 1:
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if (pin_num < 6)
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*reg = RV1103B_DRV_GPIO1_A01_OFFSET;
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else if (pin_num >= 6 && pin_num < 23)
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*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
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else if (pin_num >= 24 && pin_num < 30)
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*reg = RV1103B_DRV_GPIO1_A67_OFFSET - 0xc;
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else
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ret = -EINVAL;
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break;
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case 2:
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if (pin_num < 12) {
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*reg = RV1103B_DRV_GPIO2_OFFSET;
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} else if (pin_num >= 16) {
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ret = -EINVAL;
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} else {
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*reg = RV1103B_DRV_GPIO2_SARADC_OFFSET;
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*bit = 10;
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return 0;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret) {
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dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
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return ret;
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}
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*reg += ((pin_num / RV1103B_DRV_PINS_PER_REG) * 4);
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*bit = pin_num % RV1103B_DRV_PINS_PER_REG;
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*bit *= RV1103B_DRV_BITS_PER_PIN;
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return 0;
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}
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static int rv1103b_set_drive(struct rockchip_pin_bank *bank,
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int pin_num, int strength)
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{
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struct regmap *regmap;
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int reg, ret, i;
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u32 data;
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u8 bit;
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int rmask_bits = RV1103B_DRV_BITS_PER_PIN;
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ret = rv1103b_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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if (ret)
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return ret;
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for (i = 0, ret = 1; i < strength; i++)
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ret = (ret << 1) | 1;
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if (bank->bank_num == 2 && pin_num >= 12) {
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rmask_bits = 2;
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ret = strength;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << rmask_bits) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RV1103B_PULL_BITS_PER_PIN 2
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#define RV1103B_PULL_PINS_PER_REG 8
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#define RV1103B_PULL_GPIO0_A_OFFSET 0x40200
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#define RV1103B_PULL_GPIO0_B_OFFSET 0x50204
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#define RV1103B_PULL_GPIO1_A01_OFFSET 0x210
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#define RV1103B_PULL_GPIO1_A67_OFFSET 0x10210
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#define RV1103B_PULL_GPIO2_OFFSET 0x30220
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#define RV1103B_PULL_GPIO2_SARADC_OFFSET 0x3080C
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static int rv1103b_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int ret = 0;
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*regmap = priv->regmap_base;
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switch (bank->bank_num) {
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case 0:
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if (pin_num < 7)
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*reg = RV1103B_PULL_GPIO0_A_OFFSET;
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else if (pin_num > 7 && pin_num < 14)
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*reg = RV1103B_PULL_GPIO0_B_OFFSET - 0x4;
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else
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ret = -EINVAL;
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break;
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case 1:
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if (pin_num < 6)
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*reg = RV1103B_PULL_GPIO1_A01_OFFSET;
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else if (pin_num >= 6 && pin_num < 23)
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*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
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else if (pin_num >= 24 && pin_num < 30)
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*reg = RV1103B_PULL_GPIO1_A67_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 2:
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if (pin_num < 12) {
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*reg = RV1103B_PULL_GPIO2_OFFSET;
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} else if (pin_num >= 16) {
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ret = -EINVAL;
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} else {
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*reg = RV1103B_PULL_GPIO2_SARADC_OFFSET;
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*bit = 13;
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return 0;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret) {
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dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
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return ret;
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}
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*reg += ((pin_num / RV1103B_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % RV1103B_PULL_PINS_PER_REG;
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*bit *= RV1103B_PULL_BITS_PER_PIN;
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return 0;
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}
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static int rv1103b_set_pull(struct rockchip_pin_bank *bank,
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int pin_num, int pull)
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{
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struct regmap *regmap;
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int reg, ret;
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u8 bit, type;
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u32 data;
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if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
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return -ENOTSUPP;
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ret = rv1103b_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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if (ret)
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return ret;
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type = bank->pull_type[pin_num / 8];
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if (bank->bank_num == 2 && pin_num >= 12)
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type = 1;
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ret = rockchip_translate_pull_value(type, pull);
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if (ret < 0) {
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debug("unsupported pull setting %d\n", pull);
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return ret;
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}
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/* enable the write to the equivalent lower bits */
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data = ((1 << RV1103B_PULL_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (ret << bit);
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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#define RV1103B_SMT_BITS_PER_PIN 1
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#define RV1103B_SMT_PINS_PER_REG 8
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#define RV1103B_SMT_GPIO0_A_OFFSET 0x40400
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#define RV1103B_SMT_GPIO0_B_OFFSET 0x50404
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#define RV1103B_SMT_GPIO1_A01_OFFSET 0x410
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#define RV1103B_SMT_GPIO1_A67_OFFSET 0x10410
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#define RV1103B_SMT_GPIO2_OFFSET 0x30420
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#define RV1103B_SMT_GPIO2_SARADC_OFFSET 0x3080C
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static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num,
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struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int ret = 0;
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*regmap = priv->regmap_base;
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switch (bank->bank_num) {
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case 0:
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if (pin_num < 7)
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*reg = RV1103B_SMT_GPIO0_A_OFFSET;
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else if (pin_num > 7 && pin_num < 14)
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*reg = RV1103B_SMT_GPIO0_B_OFFSET - 0x4;
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else
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ret = -EINVAL;
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break;
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case 1:
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if (pin_num < 6)
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*reg = RV1103B_SMT_GPIO1_A01_OFFSET;
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else if (pin_num >= 6 && pin_num < 23)
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*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
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else if (pin_num >= 24 && pin_num < 30)
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*reg = RV1103B_SMT_GPIO1_A67_OFFSET;
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else
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ret = -EINVAL;
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break;
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case 2:
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if (pin_num < 12) {
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*reg = RV1103B_SMT_GPIO2_OFFSET;
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} else if (pin_num >= 16) {
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ret = -EINVAL;
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} else {
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*reg = RV1103B_SMT_GPIO2_SARADC_OFFSET;
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*bit = 8;
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return 0;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (ret) {
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dev_err(info->dev, "unsupported bank_num %d pin_num %d\n", bank->bank_num, pin_num);
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return ret;
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}
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*reg += ((pin_num / RV1103B_SMT_PINS_PER_REG) * 4);
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*bit = pin_num % RV1103B_SMT_PINS_PER_REG;
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*bit *= RV1103B_SMT_BITS_PER_PIN;
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return 0;
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}
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static int rv1103b_set_schmitt(struct rockchip_pin_bank *bank,
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int pin_num, int enable)
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{
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struct regmap *regmap;
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int reg, ret;
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u32 data;
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u8 bit;
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ret = rv1103b_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
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if (ret)
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return ret;
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/* enable the write to the equivalent lower bits */
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data = ((1 << RV1103B_SMT_BITS_PER_PIN) - 1) << (bit + 16);
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data |= (enable << bit);
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if (bank->bank_num == 2 && pin_num >= 12) {
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data = 0x3 << (bit + 16);
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data |= ((enable ? 0x3 : 0) << bit);
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}
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ret = regmap_write(regmap, reg, data);
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return ret;
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}
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static struct rockchip_mux_recalced_data rv1103b_mux_recalced_data[] = {
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{
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.num = 1,
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.pin = 6,
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.reg = 0x10024,
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.bit = 8,
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.mask = 0xf
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}, {
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.num = 1,
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.pin = 7,
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.reg = 0x10024,
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.bit = 12,
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.mask = 0xf
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},
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};
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static struct rockchip_pin_bank rv1103b_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x40000, 0x50008, 0x50010, 0x50018),
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PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x20, 0x10028, 0x10030, 0x10038),
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PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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IOMUX_WIDTH_4BIT,
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0x30040, 0x30048, 0x30050, 0x30058),
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};
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static const struct rockchip_pin_ctrl rv1103b_pin_ctrl = {
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.pin_banks = rv1103b_pin_banks,
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.nr_banks = ARRAY_SIZE(rv1103b_pin_banks),
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.nr_pins = 96,
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.iomux_recalced = rv1103b_mux_recalced_data,
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.niomux_recalced = ARRAY_SIZE(rv1103b_mux_recalced_data),
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.set_mux = rv1103b_set_mux,
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.set_pull = rv1103b_set_pull,
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.set_drive = rv1103b_set_drive,
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.set_schmitt = rv1103b_set_schmitt,
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};
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static const struct udevice_id rv1103b_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rv1103b-pinctrl",
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.data = (ulong)&rv1103b_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rv1103b) = {
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.name = "rockchip_rv1103b_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rv1103b_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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