490 lines
16 KiB
C
490 lines
16 KiB
C
/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2024 Rockchip Electronics Co. Ltd.
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* Author: Elaine Zhang <zhangqing@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RV1103B_H
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/* pll clocks */
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#define PLL_GPLL 1
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#define ARMCLK 2
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/* clk (clocks) */
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#define XIN_OSC0_HALF 5
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#define CLK_GPLL_DIV24 6
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#define CLK_GPLL_DIV12 7
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#define CLK_GPLL_DIV6 8
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#define CLK_GPLL_DIV4 9
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#define CLK_GPLL_DIV3 10
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#define CLK_GPLL_DIV2P5 11
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#define CLK_GPLL_DIV2 12
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#define CLK_UART0_SRC 13
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#define CLK_UART1_SRC 14
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#define CLK_UART2_SRC 15
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#define CLK_UART0_FRAC 16
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#define CLK_UART1_FRAC 17
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#define CLK_UART2_FRAC 18
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#define CLK_SAI_SRC 19
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#define CLK_SAI_FRAC 20
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#define LSCLK_NPU_SRC 21
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#define CLK_NPU_SRC 22
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#define ACLK_VEPU_SRC 23
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#define CLK_VEPU_SRC 24
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#define ACLK_VI_SRC 25
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#define CLK_ISP_SRC 26
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#define DCLK_VICAP 27
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#define CCLK_EMMC 28
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#define CCLK_SDMMC0 29
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#define SCLK_SFC_2X 30
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#define LSCLK_PERI_SRC 31
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#define ACLK_PERI_SRC 32
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#define HCLK_HPMCU 33
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#define SCLK_UART0 34
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#define SCLK_UART1 35
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#define SCLK_UART2 36
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#define CLK_I2C_PMU 37
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#define CLK_I2C_PERI 38
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#define CLK_SPI0 39
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#define CLK_PWM0_SRC 40
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#define CLK_PWM1 41
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#define CLK_PWM2 42
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#define DCLK_DECOM_SRC 43
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#define CCLK_SDMMC1 44
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#define CLK_CORE_CRYPTO 45
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#define CLK_PKA_CRYPTO 46
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#define CLK_CORE_RGA 47
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#define MCLK_SAI_SRC 48
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#define CLK_FREQ_PWM0_SRC 49
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#define CLK_COUNTER_PWM0_SRC 50
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#define PCLK_TOP_ROOT 51
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#define CLK_REF_MIPI0 52
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#define CLK_MIPI0_OUT2IO 53
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#define CLK_REF_MIPI1 54
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#define CLK_MIPI1_OUT2IO 55
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#define MCLK_SAI_OUT2IO 56
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#define ACLK_NPU_ROOT 57
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#define HCLK_RKNN 58
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#define ACLK_RKNN 59
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#define LSCLK_VEPU_ROOT 60
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#define HCLK_VEPU 61
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#define ACLK_VEPU 62
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#define CLK_CORE_VEPU 63
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#define PCLK_IOC_VCCIO3 64
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#define PCLK_ACODEC 65
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#define PCLK_USBPHY 66
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#define LSCLK_VI_100M 67
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#define LSCLK_VI_ROOT 68
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#define HCLK_ISP 69
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#define ACLK_ISP 70
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#define CLK_CORE_ISP 71
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#define ACLK_VICAP 72
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#define HCLK_VICAP 73
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#define ISP0CLK_VICAP 74
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#define PCLK_CSI2HOST0 75
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#define PCLK_CSI2HOST1 76
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#define HCLK_EMMC 77
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#define HCLK_SFC 78
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#define HCLK_SFC_XIP 79
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#define HCLK_SDMMC0 80
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#define PCLK_CSIPHY 81
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#define PCLK_GPIO1 82
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#define DBCLK_GPIO1 83
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#define PCLK_IOC_VCCIO47 84
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#define LSCLK_DDR_ROOT 85
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#define CLK_TIMER_DDRMON 86
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#define LSCLK_PMU_ROOT 87
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#define PCLK_PMU 88
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#define XIN_RC_DIV 89
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#define CLK_32K 90
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#define PCLK_PMU_GPIO0 91
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#define DBCLK_PMU_GPIO0 92
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#define CLK_DDR_FAIL_SAFE 93
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#define PCLK_PMU_HP_TIMER 94
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#define CLK_PMU_32K_HP_TIMER 95
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#define PCLK_PWM0 96
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#define CLK_PWM0 97
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#define CLK_OSC_PWM0 98
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#define CLK_RC_PWM0 99
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#define CLK_FREQ_PWM0 100
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#define CLK_COUNTER_PWM0 101
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#define PCLK_I2C0 102
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#define CLK_I2C0 103
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#define PCLK_UART0 104
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#define PCLK_IOC_PMUIO0 105
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#define CLK_REFOUT 106
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#define CLK_PREROLL 107
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#define CLK_PREROLL_32K 108
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#define CLK_LPMCU_PMU 109
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#define PCLK_SPI2AHB 110
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#define HCLK_SPI2AHB 111
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#define SCLK_SPI2AHB 112
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#define PCLK_WDT_LPMCU 113
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#define TCLK_WDT_LPMCU 114
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#define HCLK_SFC_PMU1 115
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#define HCLK_SFC_XIP_PMU1 116
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#define SCLK_SFC_2X_PMU1 117
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#define CLK_LPMCU 118
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#define CLK_LPMCU_RTC 119
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#define PCLK_LPMCU_MAILBOX 120
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#define PCLK_IOC_PMUIO1 121
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#define PCLK_CRU_PMU1 122
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#define PCLK_PERI_ROOT 123
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#define PCLK_RTC_ROOT 124
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#define CLK_TIMER_ROOT 125
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#define PCLK_TIMER 126
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#define CLK_TIMER0 127
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#define CLK_TIMER1 128
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#define CLK_TIMER2 129
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#define CLK_TIMER3 130
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#define CLK_TIMER4 131
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#define CLK_TIMER5 132
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#define PCLK_STIMER 133
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#define CLK_STIMER0 134
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#define CLK_STIMER1 135
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#define PCLK_WDT_NS 136
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#define TCLK_WDT_NS 137
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#define PCLK_WDT_S 138
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#define TCLK_WDT_S 139
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#define PCLK_WDT_HPMCU 140
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#define TCLK_WDT_HPMCU 141
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#define PCLK_I2C1 142
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#define CLK_I2C1 143
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#define PCLK_I2C2 144
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#define CLK_I2C2 145
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#define PCLK_I2C3 146
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#define CLK_I2C3 147
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#define PCLK_I2C4 148
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#define CLK_I2C4 149
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#define PCLK_SPI0 150
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#define PCLK_PWM1 151
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#define CLK_OSC_PWM1 152
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#define PCLK_PWM2 153
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#define CLK_OSC_PWM2 154
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#define PCLK_UART2 155
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#define PCLK_UART1 156
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#define ACLK_RKDMA 157
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#define PCLK_TSADC 158
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#define CLK_TSADC 159
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#define CLK_TSADC_TSEN 160
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#define PCLK_SARADC 161
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#define CLK_SARADC 162
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#define PCLK_GPIO2 163
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#define DBCLK_GPIO2 164
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#define PCLK_IOC_VCCIO6 165
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#define ACLK_USBOTG 166
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#define CLK_REF_USBOTG 167
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#define HCLK_SDMMC1 168
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#define HCLK_SAI 169
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#define MCLK_SAI 170
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#define ACLK_CRYPTO 171
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#define HCLK_CRYPTO 172
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#define HCLK_RK_RNG_NS 173
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#define HCLK_RK_RNG_S 174
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#define PCLK_OTPC_NS 175
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#define CLK_OTPC_ROOT_NS 176
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#define CLK_SBPI_OTPC_NS 177
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#define CLK_USER_OTPC_NS 178
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#define PCLK_OTPC_S 179
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#define CLK_OTPC_ROOT_S 180
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#define CLK_SBPI_OTPC_S 181
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#define CLK_USER_OTPC_S 182
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#define CLK_OTPC_ARB 183
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#define PCLK_OTP_MASK 184
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#define HCLK_RGA 185
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#define ACLK_RGA 186
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#define ACLK_MAC 187
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#define PCLK_MAC 188
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#define CLK_MACPHY 189
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#define ACLK_SPINLOCK 190
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#define HCLK_CACHE 191
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#define PCLK_HPMCU_MAILBOX 192
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#define PCLK_HPMCU_INTMUX 193
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#define CLK_HPMCU 194
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#define CLK_HPMCU_RTC 195
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#define DCLK_DECOM 196
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#define ACLK_DECOM 197
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#define PCLK_DECOM 198
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#define ACLK_SYS_SRAM 199
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#define PCLK_DMA2DDR 200
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#define ACLK_DMA2DDR 201
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#define PCLK_DCF 202
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#define ACLK_DCF 203
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#define MCLK_ACODEC_TX 204
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#define SCLK_UART0_SRC 205
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#define SCLK_UART1_SRC 206
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#define SCLK_UART2_SRC 207
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#define XIN_RC_SRC 208
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#define CLK_UTMI_USBOTG 209
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#define CLK_REF_USBPHY 230
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#define CLK_NR_CLKS (CLK_REF_USBPHY + 1)
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// PERICRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_ARESETN_PERI_BIU 0x00000002
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#define SRST_HRESETN_HPMCU_BIU 0x00000003
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#define SRST_LSRESETN_PERI_BIU 0x00000004
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#define SRST_PRESETN_PERI_BIU 0x00000005
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#define SRST_PRESETN_RTC_BIU 0x00000006
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#define SRST_HRESETN_BOOTROM 0x00000007
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// PERICRU_SOFTRST_CON01(Offset:0xA04)
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#define SRST_PRESETN_TIMER 0x00000010
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#define SRST_RESETN_TIMER0 0x00000011
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#define SRST_RESETN_TIMER1 0x00000012
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#define SRST_RESETN_TIMER2 0x00000013
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#define SRST_RESETN_TIMER3 0x00000014
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#define SRST_RESETN_TIMER4 0x00000015
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#define SRST_RESETN_TIMER5 0x00000016
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#define SRST_PRESETN_STIMER 0x00000017
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#define SRST_RESETN_STIMER0 0x00000018
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#define SRST_RESETN_STIMER1 0x00000019
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// PERICRU_SOFTRST_CON02(Offset:0xA08)
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#define SRST_PRESETN_WDT_NS 0x00000020
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#define SRST_TRESETN_WDT_NS 0x00000021
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#define SRST_PRESETN_WDT_S 0x00000022
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#define SRST_TRESETN_WDT_S 0x00000023
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#define SRST_PRESETN_WDT_HPMCU 0x00000024
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#define SRST_TRESETN_WDT_HPMCU 0x00000025
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#define SRST_PRESETN_I2C1 0x00000026
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#define SRST_RESETN_I2C1 0x00000027
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#define SRST_PRESETN_I2C2 0x00000028
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#define SRST_RESETN_I2C2 0x00000029
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#define SRST_PRESETN_I2C3 0x0000002A
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#define SRST_RESETN_I2C3 0x0000002B
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#define SRST_PRESETN_I2C4 0x0000002C
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#define SRST_RESETN_I2C4 0x0000002D
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// PERICRU_SOFTRST_CON03(Offset:0xA0C)
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#define SRST_PRESETN_UART2 0x00000030
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#define SRST_SRESETN_UART2 0x00000031
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#define SRST_PRESETN_UART1 0x00000032
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#define SRST_SRESETN_UART1 0x00000033
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#define SRST_PRESETN_SPI0 0x0000003A
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#define SRST_RESETN_SPI0 0x0000003B
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// PERICRU_SOFTRST_CON04(Offset:0xA10)
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#define SRST_PRESETN_PWM1 0x00000046
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#define SRST_RESETN_PWM1 0x00000047
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#define SRST_PRESETN_PWM2 0x0000004C
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#define SRST_RESETN_PWM2 0x0000004D
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// PERICRU_SOFTRST_CON05(Offset:0xA14)
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#define SRST_ARESETN_RKDMA 0x00000058
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#define SRST_PRESETN_TSADC 0x00000059
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#define SRST_RESETN_TSADC 0x0000005A
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#define SRST_PRESETN_SARADC 0x0000005C
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#define SRST_RESETN_SARADC 0x0000005D
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// PERICRU_SOFTRST_CON06(Offset:0xA18)
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#define SRST_RESETN_SARADC_PHY 0x00000060
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#define SRST_PRESETN_RTC_TEST 0x00000061
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#define SRST_PRESETN_GPIO2 0x00000063
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#define SRST_DBRESETN_GPIO2 0x00000064
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#define SRST_PRESETN_IOC_VCCIO6 0x00000065
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#define SRST_PRESETN_PERI_SGRF 0x00000066
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#define SRST_PRESETN_PERI_GRF 0x00000067
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#define SRST_PRESETN_CRU_PERI 0x00000068
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#define SRST_ARESETN_USBOTG 0x00000069
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// PERICRU_SOFTRST_CON07(Offset:0xA1C)
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#define SRST_HRESETN_SDMMC1 0x00000070
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#define SRST_HRESETN_SAI 0x00000071
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#define SRST_MRESETN_SAI 0x00000072
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// PERICRU_SOFTRST_CON08(Offset:0xA20)
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#define SRST_RESETN_CORE_CRYPTO 0x00000080
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#define SRST_RESETN_PKA_CRYPTO 0x00000081
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#define SRST_ARESETN_CRYPTO 0x00000082
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#define SRST_HRESETN_CRYPTO 0x00000083
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#define SRST_HRESETN_RK_RNG_NS 0x00000084
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#define SRST_HRESETN_RK_RNG_S 0x00000085
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#define SRST_PRESETN_OTPC_NS 0x00000086
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#define SRST_RESETN_SBPI_OTPC_NS 0x00000088
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#define SRST_RESETN_USER_OTPC_NS 0x00000089
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#define SRST_PRESETN_OTPC_S 0x0000008A
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#define SRST_RESETN_SBPI_OTPC_S 0x0000008C
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#define SRST_RESETN_USER_OTPC_S 0x0000008D
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#define SRST_RESETN_OTPC_ARB 0x0000008E
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#define SRST_PRESETN_OTP_MASK 0x0000008F
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// PERICRU_SOFTRST_CON09(Offset:0xA24)
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#define SRST_HRESETN_RGA 0x00000090
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#define SRST_ARESETN_RGA 0x00000091
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#define SRST_RESETN_CORE_RGA 0x00000092
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#define SRST_ARESETN_MAC 0x00000093
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#define SRST_RESETN_MACPHY 0x0000009B
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// PERICRU_SOFTRST_CON10(Offset:0xA28)
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#define SRST_ARESETN_SPINLOCK 0x000000A0
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#define SRST_HRESETN_CACHE 0x000000A1
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#define SRST_PRESETN_HPMCU_MAILBOX 0x000000A2
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#define SRST_PRESETN_HPMCU_INTMUX 0x000000A3
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#define SRST_RESETN_HPMCU_FULL_CLUSTER 0x000000A4
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#define SRST_RESETN_HPMCU_PWUP 0x000000A5
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#define SRST_RESETN_HPMCU_ONLY_CORE 0x000000A6
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#define SRST_TRESETN_HPMCU_JTAG 0x000000A7
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// PERICRU_SOFTRST_CON11(Offset:0xA2C)
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#define SRST_DRESETN_DECOM 0x000000B0
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#define SRST_ARESETN_DECOM 0x000000B1
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#define SRST_PRESETN_DECOM 0x000000B2
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#define SRST_ARESETN_SYS_SRAM 0x000000B3
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#define SRST_PRESETN_DMA2DDR 0x000000B4
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#define SRST_ARESETN_DMA2DDR 0x000000B5
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#define SRST_PRESETN_DCF 0x000000B6
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#define SRST_ARESETN_DCF 0x000000B7
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#define SRST_RESETN_USBPHY_POR 0x000000BC
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#define SRST_RESETN_USBPHY_OTG 0x000000BD
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// ======================= VEPUCRU module definition bank=1 =======================
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// VEPUCRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_ARESETN_VEPU_BIU 0x00040001
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#define SRST_LSRESETN_VEPU_BIU 0x00040002
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#define SRST_RESETN_REF_PVTPLL_VEPU 0x00040003
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#define SRST_HRESETN_VEPU 0x00040004
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#define SRST_ARESETN_VEPU 0x00040005
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#define SRST_RESETN_CORE_VEPU 0x00040006
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#define SRST_PRESETN_VEPU_PVTPLL 0x00040007
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#define SRST_PRESETN_CRU_VEPU 0x00040008
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#define SRST_PRESETN_VEPU_GRF 0x0004000A
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#define SRST_PRESETN_IOC_VCCIO3 0x0004000B
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#define SRST_PRESETN_ACODEC 0x0004000D
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#define SRST_PRESETN_USBPHY 0x0004000E
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// ======================= NPUCRU module definition bank=2 ========================
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// NPUCRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_RESETN_REF_PVTPLL_NPU 0x00080000
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#define SRST_ARESETN_NPU_BIU 0x00080002
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#define SRST_LSRESETN_NPU_BIU 0x00080003
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#define SRST_HRESETN_RKNN 0x00080004
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#define SRST_ARESETN_RKNN 0x00080005
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#define SRST_PRESETN_NPU_PVTPLL 0x00080006
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#define SRST_PRESETN_CRU_NPU 0x00080007
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#define SRST_PRESETN_NPU_GRF 0x00080009
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// ======================== VICRU module definition bank=3 ========================
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// VICRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_LSRESETN_VI_BIU 0x000c0001
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#define SRST_ARESETN_VI_BIU 0x000c0002
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#define SRST_RESETN_REF_PVTPLL_ISP 0x000c0003
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#define SRST_RESETN_CORE_ISP 0x000c0006
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// VICRU_SOFTRST_CON01(Offset:0xA04)
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#define SRST_DRESETN_VICAP 0x000c0010
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#define SRST_ARESETN_VICAP 0x000c0012
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#define SRST_HRESETN_VICAP 0x000c0013
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#define SRST_ISP0RESETN_VICAP 0x000c0018
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#define SRST_PRESETN_CSI2HOST0 0x000c0019
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#define SRST_PRESETN_CSI2HOST1 0x000c001B
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#define SRST_SRESETN_SFC_2X 0x000c001C
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#define SRST_HRESETN_EMMC 0x000c001D
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#define SRST_HRESETN_SFC 0x000c001E
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#define SRST_HRESETN_SFC_XIP 0x000c001F
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// VICRU_SOFTRST_CON02(Offset:0xA08)
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#define SRST_HRESETN_SDMMC0 0x000c0020
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#define SRST_PRESETN_CSIPHY 0x000c0022
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#define SRST_PRESETN_GPIO1 0x000c0023
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#define SRST_DBRESETN_GPIO1 0x000c0024
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#define SRST_PRESETN_IOC_VCCIO47 0x000c0025
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#define SRST_PRESETN_VI_GRF 0x000c0026
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#define SRST_PRESETN_CRU_VI 0x000c0028
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#define SRST_PRESETN_VI_PVTPLL 0x000c0029
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// ======================= CORECRU module definition bank=4 =======================
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// CORECRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_RESETN_REF_PVTPLL_CORE 0x00100000
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#define SRST_NCOREPORESET 0x00100001
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#define SRST_NCORESET 0x00100002
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#define SRST_NDBGRESET 0x00100003
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#define SRST_NL2RESET 0x00100004
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#define SRST_ARESETN_CORE_BIU 0x00100005
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#define SRST_PRESETN_CORE_BIU 0x00100006
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#define SRST_HRESETN_CORE_BIU 0x00100007
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#define SRST_PRESETN_DBG 0x00100008
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#define SRST_POTRESETN_DBG 0x00100009
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#define SRST_NTRESETN_DBG 0x0010000A
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// ======================= DDRCRU module definition bank=5 ========================
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// DDRCRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_LSRESETN_DDR_BIU 0x00140001
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#define SRST_PRESETN_DDRC 0x00140002
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#define SRST_PRESETN_DDRMON 0x00140003
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#define SRST_RESETN_TIMER_DDRMON 0x00140004
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#define SRST_PRESETN_DFICTRL 0x00140005
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#define SRST_PRESETN_DDR_GRF 0x00140006
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#define SRST_PRESETN_CRU_DDR 0x00140007
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#define SRST_HRESETN_DDRPHY 0x00140008
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// ====================== SUBDDRCRU module definition bank=6 ======================
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// SUBDDRCRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_RESETN_DDR_BIU 0x00160001
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#define SRST_ARESETN_DDRSCH_CPU 0x00160002
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#define SRST_ARESETN_DDRSCH_VI 0x00160004
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#define SRST_ARESETN_DDRSCH_NPVD 0x00160005
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#define SRST_RESETN_CORE_DDRC 0x00160006
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#define SRST_RESETN_DDRMON 0x00160007
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#define SRST_RESETN_DFICTRL 0x00160008
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#define SRST_RESETN_DFI_SCRAMBLE 0x00160009
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// ======================= TOPCRU module definition bank=7 ========================
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// TOPCRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_PRESETN_CRU 0x00180000
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#define SRST_PRESETN_CRU_BIU 0x00180001
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#define SRST_RESETN_DDRPHY 0x0018000C
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//======================= PMUCRU module definition bank=8 ========================
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// PMUCRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_PRESETN_PMU_GPIO0 0x001c0004
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#define SRST_DBRESETN_PMU_GPIO0 0x001c0005
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#define SRST_RESETN_DDR_FAIL_SAFE 0x001c0008
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#define SRST_PRESETN_PMU_HP_TIMER 0x001c0009
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#define SRST_RESETN_PMU_HP_TIMER 0x001c000A
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#define SRST_RESETN_PMU_32K_HP_TIMER 0x001c000B
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#define SRST_PRESETN_I2C0 0x001c000C
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#define SRST_RESETN_I2C0 0x001c000D
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#define SRST_PRESETN_UART0 0x001c000E
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#define SRST_SRESETN_UART0 0x001c000F
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// PMUCRU_SOFTRST_CON01(Offset:0xA04)
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#define SRST_PRESETN_IOC_PMUIO0 0x001c0010
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#define SRST_PRESETN_CRU_PMU 0x001c0011
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#define SRST_PRESETN_PMU_GRF 0x001c0012
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#define SRST_PRESETN_PMU_SGRF 0x001c0013
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#define SRST_PRESETN_PMU_SGRF_REMAP 0x001c0014
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#define SRST_RESETN_PREROLL 0x001c0016
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#define SRST_RESETN_PREROLL_32K 0x001c0017
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#define SRST_HRESETN_PMU_SRAM 0x001c0018
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#define SRST_PRESETN_PWM0 0x001c0019
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#define SRST_RESETN_PWM0 0x001c001A
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// PMUCRU_SOFTRST_CON02(Offset:0xA08)
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#define SRST_RESETN_LPMCU 0x001c0020
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#define SRST_RESETN_LPMCU_PWRUP 0x001c0021
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#define SRST_RESETN_LPMCU_CPU 0x001c0022
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#define SRST_TRESETN_LPMCU_CPU 0x001c0023
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// ======================= PMU1CRU module definition bank=9 =======================
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// PMU1CRU_SOFTRST_CON00(Offset:0xA00)
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#define SRST_PRESETN_SPI2AHB 0x00200000
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#define SRST_HRESETN_SPI2AHB 0x00200001
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#define SRST_SRESETN_SPI2AHB 0x00200002
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#define SRST_LSRESETN_PMU_BIU 0x00200003
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#define SRST_PRESETN_WDT_LPMCU 0x00200009
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#define SRST_TRESETN_WDT_LPMCU 0x0020000A
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#define SRST_HRESETN_SFC_PMU1 0x0020000C
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#define SRST_HRESETN_SFC_XIP_PMU1 0x0020000D
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#define SRST_SRESETN_SFC_2X_PMU1 0x0020000E
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// PMU1CRU_SOFTRST_CON01(Offset:0xA04)
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#define SRST_PRESETN_LPMCU_MAILBOX 0x00200018
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#define SRST_PRESETN_IOC_PMUIO1 0x00200019
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#define SRST_PRESETN_CRU_PMU1 0x0020001A
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#define CLK_NR_SRST (SRST_PRESETN_CRU_PMU1 + 1)
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#endif
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