97 lines
3.3 KiB
Diff
97 lines
3.3 KiB
Diff
From 6f59188c0888a48d1dfb5144d4b9c07276e7711f Mon Sep 17 00:00:00 2001
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From: Jeffy Chen <jeffy.chen@rock-chips.com>
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Date: Thu, 9 Jan 2025 14:52:44 +0800
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Subject: [PATCH 50/50] HACK: kmssink: Fallback to RFBC for AFBC
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NOTE:
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Those formats only supported on a few planes of a few chips.
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Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
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---
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sys/kms/gstkmsallocator.c | 10 ++++++++++
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sys/kms/gstkmssink.c | 3 ++-
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sys/kms/gstkmsutils.h | 30 ++++++++++++++++++++++++++++++
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3 files changed, 42 insertions(+), 1 deletion(-)
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diff --git a/sys/kms/gstkmsallocator.c b/sys/kms/gstkmsallocator.c
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index 359646a..a834eef 100644
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--- a/sys/kms/gstkmsallocator.c
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+++ b/sys/kms/gstkmsallocator.c
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@@ -475,8 +475,18 @@ gst_kms_allocator_add_fb (GstKMSAllocator * alloc, GstKMSMemory * kmsmem,
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ret = drmModeAddFB2WithModifiers (alloc->priv->fd, w, h, _fmt, _handles,
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_pitches, _offsets, _modifiers, &kmsmem->fb_id,
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DRM_MODE_FB_MODIFIERS);
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+
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+ /* Fallback to RFBC */
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+ if (ret) {
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+ _modifiers[0] = DRM_RFBC_MODIFIER;
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+
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+ ret = drmModeAddFB2WithModifiers (alloc->priv->fd, w, h, _fmt, _handles,
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+ _pitches, _offsets, _modifiers, &kmsmem->fb_id,
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+ DRM_MODE_FB_MODIFIERS);
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+ }
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}
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+ /* Old kernel, e.g. 4.4 */
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if (ret)
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ret = drmModeAddFB2WithModifiers (alloc->priv->fd, w, h, fmt, bo_handles,
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pitches, offsets, modifiers, &kmsmem->fb_id, DRM_MODE_FB_MODIFIERS);
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diff --git a/sys/kms/gstkmssink.c b/sys/kms/gstkmssink.c
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index 9fd1746..3cb9093 100644
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--- a/sys/kms/gstkmssink.c
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+++ b/sys/kms/gstkmssink.c
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@@ -1162,7 +1162,8 @@ check_afbc (GstKMSSink * self, drmModePlane * plane, guint32 drmfmt,
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if (!(mod->formats & (1 << (i - mod->offset))))
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continue;
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- if (mod->modifier == DRM_AFBC_MODIFIER)
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+ if (mod->modifier == DRM_AFBC_MODIFIER ||
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+ mod->modifier == DRM_RFBC_MODIFIER)
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*afbc = TRUE;
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else if (mod->modifier == DRM_FORMAT_MOD_LINEAR)
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*linear = TRUE;
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diff --git a/sys/kms/gstkmsutils.h b/sys/kms/gstkmsutils.h
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index 500405a..dd575a4 100644
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--- a/sys/kms/gstkmsutils.h
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+++ b/sys/kms/gstkmsutils.h
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@@ -70,6 +70,36 @@ G_BEGIN_DECLS
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(DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_SPARSE) | \
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DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16))
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+#ifndef DRM_FORMAT_MOD_VENDOR_ROCKCHIP
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+#define DRM_FORMAT_MOD_VENDOR_ROCKCHIP 0x0b
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+#endif
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+
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+#ifndef DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT
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+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT 52
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+#endif
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+
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+#ifndef DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC
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+#define DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC 0x1
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+#endif
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+
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+#ifndef ROCKCHIP_RFBC_BLOCK_SIZE_64x4
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+#define ROCKCHIP_RFBC_BLOCK_SIZE_64x4 (1ULL)
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+#endif
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+
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+#ifndef DRM_FORMAT_MOD_ROCKCHIP_CODE
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+#define DRM_FORMAT_MOD_ROCKCHIP_CODE(__type, __val) \
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+ fourcc_mod_code(ROCKCHIP, ((__u64)(__type) << DRM_FORMAT_MOD_ROCKCHIP_TYPE_SHIFT) | \
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+ ((__val) & 0x000fffffffffffffULL))
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+#endif
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+
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+#ifndef DRM_FORMAT_MOD_ROCKCHIP_RFBC
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+#define DRM_FORMAT_MOD_ROCKCHIP_RFBC(mode) \
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+ DRM_FORMAT_MOD_ROCKCHIP_CODE(DRM_FORMAT_MOD_ROCKCHIP_TYPE_RFBC, mode)
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+#endif
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+
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+#define DRM_RFBC_MODIFIER \
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+ DRM_FORMAT_MOD_ROCKCHIP_RFBC(ROCKCHIP_RFBC_BLOCK_SIZE_64x4)
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+
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#ifndef GST_VIDEO_FLAG_ARM_AFBC
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#define GST_VIDEO_FLAG_ARM_AFBC (1UL << 31)
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#define GST_VIDEO_INFO_SET_AFBC(i) \
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--
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2.20.1
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