273 lines
7.8 KiB
C
273 lines
7.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co. Ltd.
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* Author:
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* Finley Xiao <finley.xiao@rock-chips.com>
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*/
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#ifndef _ASM_ARCH_CRU_RK3506_H
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#define _ASM_ARCH_CRU_RK3506_H
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define CPU_FREQ_HZ 589824000
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/* RK3506 pll id */
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enum rk3506_pll_id {
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GPLL,
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V0PLL,
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V1PLL,
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PLL_COUNT,
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};
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struct rk3506_clk_info {
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unsigned long id;
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char *name;
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};
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struct rk3506_clk_priv {
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struct rk3506_cru *cru;
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ulong gpll_hz;
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ulong gpll_div_hz;
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ulong gpll_div_100mhz;
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ulong v0pll_hz;
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ulong v0pll_div_hz;
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ulong v1pll_hz;
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ulong v1pll_div_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk3506_cru {
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/* cru */
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uint32_t reserved0000[160]; /* offset 0x0 */
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uint32_t mode_con; /* offset 0x280 */
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uint32_t reserved0284[31]; /* offset 0x284 */
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uint32_t clksel_con[62]; /* offset 0x300 */
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uint32_t reserved03f8[258]; /* offset 0x3F8 */
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uint32_t gate_con[23]; /* offset 0x800 */
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uint32_t reserved085c[105]; /* offset 0x85C */
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uint32_t softrst_con[23]; /* offset 0xA00 */
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uint32_t reserved0a5c[105]; /* offset 0xA5C */
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uint32_t glb_cnt_th; /* offset 0xC00 */
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uint32_t glb_rst_st; /* offset 0xC04 */
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uint32_t glb_srst_fst; /* offset 0xC08 */
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uint32_t glb_srst_snd; /* offset 0xC0C */
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uint32_t glb_rst_con; /* offset 0xC10 */
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uint32_t reserved0c14[6]; /* offset 0xC14 */
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uint32_t corewfi_con; /* offset 0xC2C */
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uint32_t reserved0c30[15604]; /* offset 0xC30 */
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/* pmu cru */
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uint32_t gpll_con[5]; /* offset 0x10000 */
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uint32_t reserved10014[3]; /* offset 0x10014 */
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uint32_t v0pll_con[5]; /* offset 0x10020 */
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uint32_t reserved10034[3]; /* offset 0x10034 */
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uint32_t v1pll_con[5]; /* offset 0x10040 */
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uint32_t reserved10074[171]; /* offset 0x10054 */
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uint32_t pmuclksel_con[7]; /* offset 0x10300 */
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uint32_t reserved1031c[313]; /* offset 0x1031C */
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uint32_t pmugate_con[3]; /* offset 0x10800 */
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uint32_t reserved1080c[125]; /* offset 0x1080C */
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uint32_t pmusoftrst_con[2]; /* offset 0x10A00 */
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uint32_t reserved10a08[7583]; /* offset 0x10A08 */
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};
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check_member(rk3506_cru, reserved0c30[0], 0x0c30);
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check_member(rk3506_cru, reserved10a08[0], 0x10a08);
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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#define RK3506_PMU_CRU_BASE 0x10000
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#define RK3506_PLL_CON(x) ((x) * 0x4 + RK3506_PMU_CRU_BASE)
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#define RK3506_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
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#define RK3506_CLKGATE_CON(x) ((x) * 0x4 + 0x800)
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#define RK3506_SOFTRST_CON(x) ((x) * 0x4 + 0xa00)
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#define RK3506_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3506_PMU_CRU_BASE)
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#define RK3506_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x800 + RK3506_PMU_CRU_BASE)
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#define RK3506_MODE_CON 0x280
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#define RK3506_GLB_CNT_TH 0xc00
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#define RK3506_GLB_SRST_FST 0xc08
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#define RK3506_GLB_SRST_SND 0xc0c
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enum {
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/* CRU_CLKSEL_CON00 */
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CLK_GPLL_DIV_SHIFT = 6,
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CLK_GPLL_DIV_MASK = 0xf << CLK_GPLL_DIV_SHIFT,
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CLK_GPLL_DIV_100M_SHIFT = 10,
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CLK_GPLL_DIV_100M_MASK = 0xf << CLK_GPLL_DIV_100M_SHIFT,
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/* CRU_CLKSEL_CON01 */
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CLK_V0PLL_DIV_SHIFT = 0,
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CLK_V0PLL_DIV_MASK = 0xf << CLK_V0PLL_DIV_SHIFT,
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CLK_V1PLL_DIV_SHIFT = 4,
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CLK_V1PLL_DIV_MASK = 0xf << CLK_V1PLL_DIV_SHIFT,
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/* CRU_CLKSEL_CON15 */
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CLK_CORE_SRC_DIV_SHIFT = 0,
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CLK_CORE_SRC_DIV_MASK = 0x1f << CLK_CORE_SRC_DIV_SHIFT,
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CLK_CORE_SRC_SEL_SHIFT = 5,
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CLK_CORE_SRC_SEL_MASK = 0x3 << CLK_CORE_SRC_SEL_SHIFT,
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CLK_CORE_SEL_GPLL = 0,
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CLK_CORE_SEL_V0PLL,
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CLK_CORE_SEL_V1PLL,
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CLK_CORE_SRC_PVTMUX_SEL_SHIFT = 8,
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CLK_CORE_SRC_PVTMUX_SEL_MASK = 0x1 << CLK_CORE_SRC_PVTMUX_SEL_SHIFT,
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CLK_CORE_SRC_PRE = 0,
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CLK_CORE_PVTPLL_SRC,
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ACLK_CORE_DIV_SHIFT = 9,
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ACLK_CORE_DIV_MASK = 0xf << ACLK_CORE_DIV_SHIFT,
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/* CRU_CLKSEL_CON16 */
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PCLK_CORE_DIV_SHIFT = 0,
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PCLK_CORE_DIV_MASK = 0xf << PCLK_CORE_DIV_SHIFT,
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/* CRU_CLKSEL_CON21 */
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ACLK_BUS_DIV_SHIFT = 0,
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ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT,
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ACLK_BUS_SEL_SHIFT = 5,
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ACLK_BUS_SEL_MASK = 0x3 << ACLK_BUS_SEL_SHIFT,
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ACLK_BUS_SEL_GPLL_DIV = 0,
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ACLK_BUS_SEL_V0PLL_DIV,
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ACLK_BUS_SEL_V1PLL_DIV,
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HCLK_BUS_DIV_SHIFT = 7,
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HCLK_BUS_DIV_MASK = 0x1f << HCLK_BUS_DIV_SHIFT,
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HCLK_BUS_SEL_SHIFT = 12,
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HCLK_BUS_SEL_MASK = 0x3 << HCLK_BUS_SEL_SHIFT,
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/* CRU_CLKSEL_CON22 */
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PCLK_BUS_DIV_SHIFT = 0,
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PCLK_BUS_DIV_MASK = 0x1f << PCLK_BUS_DIV_SHIFT,
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PCLK_BUS_SEL_SHIFT = 5,
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PCLK_BUS_SEL_MASK = 0x3 << PCLK_BUS_SEL_SHIFT,
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/* CRU_CLKSEL_CON29 */
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HCLK_LSPERI_DIV_SHIFT = 0,
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HCLK_LSPERI_DIV_MASK = 0x1f << HCLK_LSPERI_DIV_SHIFT,
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HCLK_LSPERI_SEL_SHIFT = 5,
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HCLK_LSPERI_SEL_MASK = 0x3 << HCLK_LSPERI_SEL_SHIFT,
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/* CRU_CLKSEL_CON32 */
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CLK_I2C0_DIV_SHIFT = 0,
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CLK_I2C0_DIV_MASK = 0xf << CLK_I2C0_DIV_SHIFT,
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CLK_I2C0_SEL_SHIFT = 4,
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CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
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CLK_I2C_SEL_GPLL = 0,
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CLK_I2C_SEL_V0PLL,
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CLK_I2C_SEL_V1PLL,
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CLK_I2C1_DIV_SHIFT = 6,
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CLK_I2C1_DIV_MASK = 0xf << CLK_I2C1_DIV_SHIFT,
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CLK_I2C1_SEL_SHIFT = 10,
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CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
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/* CRU_CLKSEL_CON33 */
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CLK_I2C2_DIV_SHIFT = 0,
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CLK_I2C2_DIV_MASK = 0xf << CLK_I2C2_DIV_SHIFT,
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CLK_I2C2_SEL_SHIFT = 4,
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CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
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CLK_PWM1_DIV_SHIFT = 6,
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CLK_PWM1_DIV_MASK = 0xf << CLK_PWM1_DIV_SHIFT,
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CLK_PWM1_SEL_SHIFT = 10,
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CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
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CLK_PWM1_SEL_GPLL_DIV = 0,
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CLK_PWM1_SEL_V0PLL_DIV,
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CLK_PWM1_SEL_V1PLL_DIV,
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/* CRU_CLKSEL_CON34 */
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CLK_SPI0_DIV_SHIFT = 4,
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CLK_SPI0_DIV_MASK = 0xf << CLK_SPI0_DIV_SHIFT,
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CLK_SPI0_SEL_SHIFT = 8,
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CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
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CLK_SPI_SEL_24M = 0,
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CLK_SPI_SEL_GPLL_DIV,
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CLK_SPI_SEL_V0PLL_DIV,
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CLK_SPI_SEL_V1PLL_DIV,
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CLK_SPI1_DIV_SHIFT = 10,
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CLK_SPI1_DIV_MASK = 0xf << CLK_SPI1_DIV_SHIFT,
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CLK_SPI1_SEL_SHIFT = 14,
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CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
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/* CRU_CLKSEL_CON49 */
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ACLK_HSPERI_DIV_SHIFT = 0,
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ACLK_HSPERI_DIV_MASK = 0x1f << ACLK_HSPERI_DIV_SHIFT,
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ACLK_HSPERI_SEL_SHIFT = 5,
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ACLK_HSPERI_SEL_MASK = 0x3 << ACLK_HSPERI_SEL_SHIFT,
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ACLK_HSPERI_SEL_GPLL_DIV = 0,
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ACLK_HSPERI_SEL_V0PLL_DIV = 1,
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ACLK_HSPERI_SEL_V1PLL_DIV = 2,
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CCLK_SDMMC_DIV_SHIFT = 7,
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CCLK_SDMMC_DIV_MASK = 0x3f << CCLK_SDMMC_DIV_SHIFT,
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CCLK_SDMMC_SEL_SHIFT = 13,
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CCLK_SDMMC_SEL_MASK = 0x3 << CCLK_SDMMC_SEL_SHIFT,
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CCLK_SDMMC_SEL_24M = 0,
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CCLK_SDMMC_SEL_GPLL,
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CCLK_SDMMC_SEL_V0PLL,
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CCLK_SDMMC_SEL_V1PLL,
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/* CRU_CLKSEL_CON50 */
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SCLK_FSPI_DIV_SHIFT = 0,
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SCLK_FSPI_DIV_MASK = 0x1f << SCLK_FSPI_DIV_SHIFT,
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SCLK_FSPI_SEL_SHIFT = 5,
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SCLK_FSPI_SEL_MASK = 0x3 << SCLK_FSPI_SEL_SHIFT,
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SCLK_FSPI_SEL_24M = 0,
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SCLK_FSPI_SEL_GPLL,
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SCLK_FSPI_SEL_V0PLL,
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SCLK_FSPI_SEL_V1PLL,
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CLK_MAC_DIV_SHIFT = 7,
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CLK_MAC_DIV_MASK = 0x1f << CLK_MAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON54 */
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CLK_SARADC_DIV_SHIFT = 0,
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CLK_SARADC_DIV_MASK = 0xf << CLK_SARADC_DIV_SHIFT,
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CLK_SARADC_SEL_SHIFT = 4,
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CLK_SARADC_SEL_MASK = 0x3 << CLK_SARADC_SEL_SHIFT,
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CLK_SARADC_SEL_24M = 0,
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CLK_SARADC_SEL_400K,
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CLK_SARADC_SEL_32K,
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/* CRU_CLKSEL_CON60 */
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DCLK_VOP_DIV_SHIFT = 0,
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DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT,
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DCLK_VOP_SEL_SHIFT = 8,
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DCLK_VOP_SEL_MASK = 0x7 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_24M = 0,
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DCLK_VOP_SEL_GPLL,
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DCLK_VOP_SEL_V0PLL,
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DCLK_VOP_SEL_V1PLL,
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DCLK_VOP_SEL_FRAC_VOIC1,
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DCLK_VOP_SEL_FRAC_COMMON0,
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DCLK_VOP_SEL_FRAC_COMMON1,
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DCLK_VOP_SEL_FRAC_COMMON2,
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/* CRU_CLKSEL_CON61 */
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CLK_TSADC_DIV_SHIFT = 0,
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CLK_TSADC_DIV_MASK = 0xff << CLK_TSADC_DIV_SHIFT,
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CLK_TSADC_TSEN_DIV_SHIFT = 8,
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CLK_TSADC_TSEN_DIV_MASK = 0x7 << CLK_TSADC_TSEN_DIV_SHIFT,
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/* PMUCRU_CLKSEL_CON00 */
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CLK_PWM0_DIV_SHIFT = 6,
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CLK_PWM0_DIV_MASK = 0xf << CLK_PWM0_DIV_SHIFT,
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CLK_MAC_OUT_DIV_SHIFT = 10,
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CLK_MAC_OUT_DIV_MASK = 0x3f << CLK_MAC_OUT_DIV_SHIFT,
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};
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#endif
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