246 lines
7.1 KiB
C
246 lines
7.1 KiB
C
/*
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* Copyright (c) 2024 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rv1103b.h>
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#include <asm/arch/ioc_rv1103b.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PERI_CRU_BASE 0x20000000
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#define PERICRU_PERISOFTRST_CON10 0x0a28
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#define PMU0_CRU_BASE 0x20070000
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#define PMUCRU_PMUSOFTRST_CON02 0x0a08
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#define GRF_SYS_BASE 0x20150000
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#define GRF_SYS_HPMCU_CACHE_MISC 0x0214
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#define GPIO0_IOC_BASE 0x201B0000
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#define GPIO0A_IOMUX_SEL_H 0x04
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#define GPIO0_BASE 0x20520000
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#define GPIO_SWPORT_DR_L 0x00
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#define GPIO_SWPORT_DDR_L 0x08
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#define GPIO1_IOC_BASE 0x20170000
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#define GPIO1A_IOMUX_SEL_0 0x20
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#define GPIO1A_IOMUX_SEL_1_0 0x24
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#define GPIO1A_IOMUX_SEL_1_1 0x10024
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#define GPIO1B_IOMUX_SEL_0 0x10028
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#define GPIO1B_IOMUX_SEL_1 0x1002c
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#define GPIO1_IOC_GPIO1A_PULL_0 0x210
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#define GPIO1_IOC_GPIO1A_PULL_1 0x10210
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#define GPIO1_IOC_GPIO1B_PULL 0x10214
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#define GPIO1_IOC_JTAG_M2_CON 0x10810
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#define GPIO2_IOC_BASE 0x20840000
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#define GPIO2A_IOMUX_SEL_1_1 0x44
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#define SGRF_SYS_BASE 0x20250000
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#define SGRF_SYS_SOC_CON2 0x0008
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#define SGRF_SYS_SOC_CON3 0x000c
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#define SGRF_SYS_OTP_CON 0x0018
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#define FIREWALL_CON0 0x0020
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#define FIREWALL_CON1 0x0024
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#define FIREWALL_CON2 0x0028
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#define FIREWALL_CON3 0x002c
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#define FIREWALL_CON4 0x0030
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#define FIREWALL_CON5 0x0034
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#define FIREWALL_CON7 0x003c
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#define SGRF_SYS_HPMCU_BOOT_DDR 0x0080
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#define SGRF_PMU_BASE 0x20260000
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#define SGRF_PMU_SOC_CON0 0x0000
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#define SGRF_PMU_PMUMCU_BOOT_ADDR 0x0020
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#define SYS_GRF_BASE 0x20150000
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#define GRF_SYS_PERI_CON2 0x08
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#define GRF_SYS_USBPHY_CON0 0x50
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#define TOP_CRU_BASE 0x20060000
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#define TOPCRU_CRU_GLB_RST_CON 0xc10
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#define USBPHY_APB_BASE 0x20e10000
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#define USBPHY_FSLS_DIFF_RECEIVER 0x0100
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void board_debug_uart_init(void)
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{
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/* No need to change uart */
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}
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void board_set_iomux(enum if_type if_type, int devnum, int routing)
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{
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switch (if_type) {
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case IF_TYPE_MMC:
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if (devnum == 0) {
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writel(0xffff1111, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_0);
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writel(0x00ff0011, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0);
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} else if (devnum == 1) {
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#if CONFIG_SPL_BUILD
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/* set SDMMC D0-3/CMD/CLK to gpio and pull down */
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writel(0xf0000000, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1);
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writel(0xffff0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0);
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writel(0x000f0000, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_1);
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writel(0xc0008000, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_PULL_1);
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writel(0x03ff02AA, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_PULL);
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/* SDMMC PWREN GPIO0A4 power down and power up */
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writel(0x00100010, GPIO0_BASE + GPIO_SWPORT_DR_L);
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writel(0x00100010, GPIO0_BASE + GPIO_SWPORT_DDR_L);
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mdelay(50);
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writel(0x00100000, GPIO0_BASE + GPIO_SWPORT_DR_L);
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#endif
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/* set SDMMC D0-3/CMD/CLK and pull up */
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writel(0xff001100, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_1);
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writel(0xffff1111, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_0);
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writel(0x000f0001, GPIO1_IOC_BASE + GPIO1B_IOMUX_SEL_1);
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writel(0xc0004000, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_PULL_1);
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writel(0x03ff0155, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_PULL);
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}
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break;
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case IF_TYPE_MTD:
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if (routing == 0) {
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/* FSPI0 M0 */
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writel(0xffff2222, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_0);
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writel(0x00ff0022, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0);
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}
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break;
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default:
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printf("Bootdev 0x%x is not support\n", if_type);
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}
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}
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#ifdef CONFIG_SPL_BUILD
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void rockchip_stimer_init(void)
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{
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/* If Timer already enabled, don't re-init it */
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u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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if (reg & 0x1)
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return;
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writel(0x00010000, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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asm volatile("mcr p15, 0, %0, c14, c0, 0"
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: : "r"(COUNTER_FREQUENCY));
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
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writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
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writel(0x00010001, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
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}
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int spl_fit_standalone_release(char *id, uintptr_t entry_point)
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{
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if (!strcmp(id, "mcu0")) {
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/* set the hpmcu boot address */
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writel(entry_point, SGRF_SYS_BASE + SGRF_SYS_HPMCU_BOOT_DDR);
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} else if (!strcmp(id, "mcu1")) {
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/* reset lpmcu */
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writel(0x000f000f, PMU0_CRU_BASE + PMUCRU_PMUSOFTRST_CON02);
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/* set the lpmcu boot address */
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writel(entry_point, SGRF_PMU_BASE + SGRF_PMU_PMUMCU_BOOT_ADDR);
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writel(0x00800000, SGRF_PMU_BASE + SGRF_PMU_SOC_CON0);
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/* release lpmcu */
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writel(0x000f0000, PMU0_CRU_BASE + PMUCRU_PMUSOFTRST_CON02);
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}
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return 0;
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}
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void rk_meta_process(void)
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{
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/* trigger software irq to hpmcu that means meta was ready */
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writel(0x00080008, GRF_SYS_BASE + GRF_SYS_HPMCU_CACHE_MISC);
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}
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#endif
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#ifndef CONFIG_TPL_BUILD
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int arch_cpu_init(void)
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{
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#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_SUPPORT_USBPLUG)
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/* Set all devices to Non-secure */
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writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON0);
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writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON1);
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writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON2);
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writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON3);
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writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON4);
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writel(0xffff0000, SGRF_SYS_BASE + FIREWALL_CON5);
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writel(0x01f00000, SGRF_SYS_BASE + FIREWALL_CON7);
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/* Set OTP to none secure mode */
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writel(0x00020000, SGRF_SYS_BASE + SGRF_SYS_OTP_CON);
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#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX)
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/* Set the emmc iomux */
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board_set_iomux(IF_TYPE_MMC, 0, 0);
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#elif defined(CONFIG_ROCKCHIP_SFC_IOMUX)
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/* Set the fspi iomux */
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board_set_iomux(IF_TYPE_MTD, 0, 0);
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#endif
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#if defined(CONFIG_MMC_DW_ROCKCHIP)
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/* Set the sdmmc iomux and power cycle */
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board_set_iomux(IF_TYPE_MMC, 1, 0);
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/* Enable force_jtag */
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writel(0x00010001, GPIO1_IOC_BASE + GPIO1_IOC_JTAG_M2_CON);
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#endif
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/* no-secure WDT reset output will reset SoC system. */
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writel(0x00010001, SYS_GRF_BASE + GRF_SYS_PERI_CON2);
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/* secure WDT reset output will reset SoC system. */
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writel(0x00010001, SGRF_SYS_BASE + SGRF_SYS_SOC_CON2);
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/*
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* enable tsadc trigger global reset and select first reset.
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* enable global reset and wdt trigger pmu reset.
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* select first reset trigger pmu reset.
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*/
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writel(0x0000ffdf, TOP_CRU_BASE + TOPCRU_CRU_GLB_RST_CON);
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/*
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* Set the USB2 PHY in suspend mode and turn off the
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* USB2 PHY FS/LS differential receiver to save power:
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* VCC1V8_USB : reduce 3.8 mA
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* VDD_0V9 : reduce 4.4 mA
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*/
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writel(0x01ff01d1, SYS_GRF_BASE + GRF_SYS_USBPHY_CON0);
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writel(0x00000000, USBPHY_APB_BASE + USBPHY_FSLS_DIFF_RECEIVER);
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#ifdef CONFIG_SPI_FLASH_AUTO_MERGE
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/* gpio1a5/gpio2a6 cs-gpio */
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writel(0x00F00000, GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_1_0);
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writel(0x0F000000, GPIO2_IOC_BASE + GPIO2A_IOMUX_SEL_1_1);
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#endif
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_ROCKCHIP_IMAGE_TINY
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int rk_board_scan_bootdev(void)
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{
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char *devtype, *devnum;
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if (!run_command("blk dev mmc 1", 0) &&
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!run_command("rkimgtest mmc 1", 0)) {
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devtype = "mmc";
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devnum = "1";
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} else {
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run_command("blk dev mtd 2", 0);
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devtype = "mtd";
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devnum = "2";
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}
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env_set("devtype", devtype);
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env_set("devnum", devnum);
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return 0;
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}
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#endif
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#if defined(CONFIG_ROCKCHIP_EMMC_IOMUX) && defined(CONFIG_ROCKCHIP_SFC_IOMUX)
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#error FSPI and eMMC iomux is incompatible for rv1103b Soc. You should close one of them.
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#endif
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