2024-11-29 08:13:19 +00:00
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#
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# Configure the GCC_TARGET_ARCH variable and append the
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# appropriate RISC-V ISA extensions.
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#
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ifeq ($(BR2_riscv),y)
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ifeq ($(BR2_RISCV_64),y)
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GCC_TARGET_ARCH := rv64i
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else
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GCC_TARGET_ARCH := rv32i
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endif
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ifeq ($(BR2_RISCV_ISA_RVM),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)m
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endif
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ifeq ($(BR2_RISCV_ISA_RVA),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)a
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endif
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ifeq ($(BR2_RISCV_ISA_RVF),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)f
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endif
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ifeq ($(BR2_RISCV_ISA_RVD),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)d
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endif
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ifeq ($(BR2_RISCV_ISA_RVM),y)
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ifeq ($(BR2_RISCV_ISA_RVA),y)
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ifeq ($(BR2_RISCV_ISA_RVF),y)
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ifeq ($(BR2_RISCV_ISA_RVD),y)
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ifeq ($(BR2_RISCV_64),y)
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GCC_TARGET_ARCH := rv64g
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endif
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ifeq ($(BR2_RISCV_32),y)
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GCC_TARGET_ARCH := rv32g
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endif
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endif
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endif
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endif
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endif
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ifeq ($(BR2_RISCV_ISA_RVC),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)c
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endif
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2024-11-29 08:23:11 +00:00
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ifeq ($(BR2_RISCV_ISA_RVV),y)
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)v
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endif
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2024-11-29 08:13:19 +00:00
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ifeq ($(BR2_RISCV_ISA_RVXTHEAD),y)
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2024-11-29 08:33:21 +00:00
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GCC_TARGET_ARCH := $(GCC_TARGET_ARCH)xtheadc
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2024-11-29 08:13:19 +00:00
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endif
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endif
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