12 lines
241 B
Plaintext
12 lines
241 B
Plaintext
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menu "i.MX8ULP DDR controllers"
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depends on ARCH_IMX8ULP
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config IMX8ULP_DRAM
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bool "imx8m dram"
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config IMX8ULP_DRAM_PHY_PLL_BYPASS
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bool "Enable the DDR PHY PLL bypass mode, so PHY clock is from DDR_CLK "
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depends on IMX8ULP_DRAM
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endmenu
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