diff --git a/clean.sh b/clean.sh index 94706d34f..696db2a4b 100755 --- a/clean.sh +++ b/clean.sh @@ -1,5 +1,6 @@ make distclean -rm source/uboot-2021.10/include/configs/image_cfg.json +#rm source/uboot-2021.10/include/configs/image_cfg.json +rm -fr output/* rm tools/scripts/Cryptodome/Cipher/AES.pyc rm tools/scripts/Cryptodome/Cipher/__init__.pyc rm tools/scripts/Cryptodome/Cipher/_mode_cbc.pyc diff --git a/source/linux-5.10/arch/riscv/configs/d211_demo128_nand_defconfig b/source/linux-5.10/arch/riscv/configs/d211_demo128_nand_defconfig index 2071f0ec9..45734a960 100644 --- a/source/linux-5.10/arch/riscv/configs/d211_demo128_nand_defconfig +++ b/source/linux-5.10/arch/riscv/configs/d211_demo128_nand_defconfig @@ -39,6 +39,7 @@ CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_H4=y CONFIG_BT_HCIUART_RTL=y CONFIG_CFG80211=y +# CONFIG_CFG80211_CRDA_SUPPORT is not set CONFIG_CFG80211_WEXT=y CONFIG_MAC80211=y CONFIG_RFKILL=y @@ -98,7 +99,6 @@ CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y CONFIG_INPUT_TOUCHSCREEN=y CONFIG_TOUCHSCREEN_ARTINCHIP=y -CONFIG_TOUCHSCREEN_GT9XX=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_8250=y # CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set @@ -127,11 +127,12 @@ CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_PWM=y CONFIG_BACKLIGHT_GPIO=y +CONFIG_LT8911EXB=y CONFIG_ARTINCHIP_GE=y CONFIG_ARTINCHIP_VE=y CONFIG_ARTINCHIP_FB=y -CONFIG_AIC_DISP_LVDS=y -CONFIG_AIC_PANEL_LVDS_GENERAL=y +CONFIG_AIC_DISP_MIPI_DSI=y +CONFIG_AIC_PANEL_DSI_SIMPLE=y CONFIG_SOUND=y CONFIG_SND=y CONFIG_SND_SOC=y diff --git a/source/linux-5.10/drivers/video/Kconfig b/source/linux-5.10/drivers/video/Kconfig index 99f95f610..2656de98d 100644 --- a/source/linux-5.10/drivers/video/Kconfig +++ b/source/linux-5.10/drivers/video/Kconfig @@ -24,6 +24,7 @@ source "drivers/video/fbdev/Kconfig" endmenu source "drivers/video/backlight/Kconfig" +source "drivers/video/lt8911exb/Kconfig" config VGASTATE tristate diff --git a/source/linux-5.10/drivers/video/Makefile b/source/linux-5.10/drivers/video/Makefile index 0f24a73ae..c1f8143ca 100644 --- a/source/linux-5.10/drivers/video/Makefile +++ b/source/linux-5.10/drivers/video/Makefile @@ -9,6 +9,7 @@ obj-y += backlight/ obj-y += fbdev/ obj-y += artinchip/ +obj-y += lt8911exb/ obj-$(CONFIG_VIDEOMODE_HELPERS) += display_timing.o videomode.o ifeq ($(CONFIG_OF),y) diff --git a/source/linux-5.10/drivers/video/artinchip/disp/panel/panel_dsi_simple.c b/source/linux-5.10/drivers/video/artinchip/disp/panel/panel_dsi_simple.c index 6b7c65fdf..911f3c039 100644 --- a/source/linux-5.10/drivers/video/artinchip/disp/panel/panel_dsi_simple.c +++ b/source/linux-5.10/drivers/video/artinchip/disp/panel/panel_dsi_simple.c @@ -71,15 +71,15 @@ static struct aic_panel_funcs panel_funcs = { /* Init the videomode parameter, dts will override the initial value. */ static struct videomode panel_vm = { - .pixelclock = 130000000, - .hactive = 1200, - .hfront_porch = 160, - .hback_porch = 160, - .hsync_len = 40, - .vactive = 1920, - .vfront_porch = 10, - .vback_porch = 20, - .vsync_len = 8, + .pixelclock = 150 * 1000 * 1000, + .hactive = 1920, + .hfront_porch = 188, + .hback_porch = 148, + .hsync_len = 44, + .vactive = 1080, + .vfront_porch = 4, + .vback_porch = 36, + .vsync_len = 5, .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE }; diff --git a/source/linux-5.10/drivers/video/lt8911exb/Kconfig b/source/linux-5.10/drivers/video/lt8911exb/Kconfig new file mode 100755 index 000000000..9dbd166fc --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/Kconfig @@ -0,0 +1,10 @@ + +config LT8911EXB + tristate "LT8911EXB Driver" + default n + help + Control LT8911EXB Chip + Select m:build as a separate module; + Select y:Build into the kernel + Select n:Not build + diff --git a/source/linux-5.10/drivers/video/lt8911exb/LT8911EXB_Main.c b/source/linux-5.10/drivers/video/lt8911exb/LT8911EXB_Main.c new file mode 100755 index 000000000..4d3ffa831 --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/LT8911EXB_Main.c @@ -0,0 +1,32 @@ +#include "include/include.h" + +bool g_irq_flag = 0; + + +int LT8911EXB_Main(void *data) +{ + + printk("LT8911EXB Init Start:"); + + LT8911_Reset(); + msleep(100); + LT8911_ChipID(); + LT8911_SetVideoTiming(&video); + LT8911_Init(&video); + LT8911_LinkTrain(); + + LT8911_LinkTrainResultCheck(); + LT8911_video_check() ; + LT8911_pcr_mk_printk(); + LT8911_htotal_stable_printk(); + + + while(!atomic_read(&thread_should_stop)) + { + LT8911_MainLoop(&video); + msleep(500); + + } + return 0; + +} diff --git a/source/linux-5.10/drivers/video/lt8911exb/LontiumDrv.c b/source/linux-5.10/drivers/video/lt8911exb/LontiumDrv.c new file mode 100755 index 000000000..09745928c --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/LontiumDrv.c @@ -0,0 +1,283 @@ +#include "include/include.h" + + +struct _lt8911exb *lt8911exb; +static struct task_struct *kthread_obj; +atomic_t thread_should_stop = ATOMIC_INIT(0); +char *ChipName = "lt8911exb"; //Define Lontium Chip Name +static int major = 0; +static struct cdev chip_cdev; +static struct class *chip_class; + + + +static int chip_open(struct inode *inode, struct file *filp) +{ + printk("chip open\n"); + return 0; +} + + +static int chip_close (struct inode *node, struct file *file) +{ + printk("chip close\n"); + return 0; +} + + +static ssize_t chip_read(struct file *filp, char __user *buf, size_t cnt, loff_t *offt) +{ + Chip_Control_Args parameter; + + if (copy_from_user(¶meter, buf, sizeof(parameter))) { + return -EFAULT; + } + + parameter.value = HDMI_ReadI2C_Byte(parameter.address); + + if (copy_to_user(buf, ¶meter, sizeof(parameter))) { + return -EFAULT; + } + + return sizeof(parameter); + +} + +static ssize_t chip_write(struct file *filp, const char __user *buf, size_t cnt, loff_t *offt) +{ + Chip_Control_Args parameter; + + if (copy_from_user(¶meter, buf, sizeof(parameter))) { + return -EFAULT; + } + + HDMI_WriteI2C_Byte(parameter.address, parameter.value); + + return sizeof(parameter); + +} + + + + +static struct file_operations chip_drv = { + .owner = THIS_MODULE, + .open = chip_open, + .release = chip_close, + .read = chip_read, + .write = chip_write, +}; + + + +static int chip_dev_init(void) +{ + int ret; + dev_t devid; + + ret = alloc_chrdev_region(&devid, 0, 1, ChipName); + if (ret < 0) { + return ret; + } + + major = MAJOR(devid); + cdev_init(&chip_cdev, &chip_drv); + cdev_add(&chip_cdev, devid, 1); + chip_class = class_create(THIS_MODULE, "chip_class"); + if (IS_ERR(chip_class)) { + unregister_chrdev(major, ChipName); + return -1; + } + + device_create(chip_class, NULL, MKDEV(major, 0), NULL, ChipName); /* /dev/ChipName */ + + return 0; +} + + +static void chip_dev_exit(void) +{ + device_destroy(chip_class, MKDEV(major, 0)); + class_destroy(chip_class); + cdev_del(&chip_cdev); + unregister_chrdev_region(MKDEV(major,0), 1); +} + + + +static const struct regmap_range chip_ranges[] = { + { .range_min = 0, .range_max = 0xffff }, +}; + +static const struct regmap_access_table chip_table = { + .yes_ranges = chip_ranges, + .n_yes_ranges = ARRAY_SIZE(chip_ranges), +}; + +static const struct regmap_config chip_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .volatile_table = &chip_table, + .cache_type = REGCACHE_NONE, +}; + + + +/* + * devm_gpiod_get_optional - If this fails, NULL is returned and no error pointer. + * + * devm_gpiod_get - If this fails, an error pointer is returned, usually ERR_PTR(-ENOENT). + * + * The devm_gpiod_get function is recommended for practical use. + */ +static int chip_parse_dts(struct device *dev) +{ + + //Gets the handle to power gpio in dts + + lt8911exb->power_gpio=devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW); + if (IS_ERR(lt8911exb->power_gpio)) { + dev_err(dev, "Failed to get power GPIO\n"); + return PTR_ERR(lt8911exb->power_gpio); + } + + + //Gets the handle to reset gpio in dts + + lt8911exb->reset_gpio=devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(lt8911exb->reset_gpio)) { + dev_err(dev, "Failed to get reset GPIO\n"); + return PTR_ERR(lt8911exb->reset_gpio); + } + + + // Additional GPIO pins can be added here if needed + + return 0; +} + + +static int chip_probe(struct i2c_client *client, const struct i2c_device_id *id) +{ + int ret; + + chip_dev_init(); + + lt8911exb = devm_kzalloc(&client->dev, sizeof(*lt8911exb), GFP_KERNEL); + if (lt8911exb == NULL) + return -ENOMEM; + + lt8911exb->trans_i2c = client; + + lt8911exb->dev = &client->dev; + + lt8911exb->chip_regmap = devm_regmap_init_i2c(client, &chip_regmap_config); + if (IS_ERR(lt8911exb->chip_regmap)) { + dev_err(&client->dev, "Failed to initialize regmap\n"); + return PTR_ERR(lt8911exb->chip_regmap); + } + + ret = chip_parse_dts(lt8911exb->dev); + if (ret<0){ + dev_err(&client->dev, "Failed to parse device tree\n"); + return ret; + } + + i2c_set_clientdata(client, lt8911exb); + + kthread_obj = kthread_run(LT8911EXB_Main, NULL, "LT8911EXB_kthread"); + if (IS_ERR(kthread_obj)) { + kthread_obj = NULL; + chip_dev_exit(); + dev_err(&client->dev, "Failed to create kernel thread\n"); + return PTR_ERR(kthread_obj); + } + + return 0; + +} + +static int chip_remove(struct i2c_client *client) +{ + + if (kthread_obj) { + atomic_set(&thread_should_stop, 1); + kthread_stop(kthread_obj); + kthread_obj = NULL; + } + + chip_dev_exit(); + + printk("driver removed\n"); + return 0; +} + + +static int chip_suspend(struct device *dev) +{ + + //power off + atomic_set(&thread_should_stop, 1); + kthread_stop(kthread_obj); + msleep(5); + gpiod_set_value(lt8911exb->power_gpio,0); + printk(KERN_INFO "lt8911exb Suspend"); + return 0; +} + + + +static int chip_resume(struct device *dev) +{ + + //power on + gpiod_set_value(lt8911exb->power_gpio,1); + msleep(5); + atomic_set(&thread_should_stop, 0); + kthread_obj = kthread_run(LT8911EXB_Main, NULL, "LT8911EXB_kthread"); + printk(KERN_INFO "lt8911exb Resume"); + return 0; +} + + +static const struct dev_pm_ops chip_pm_ops = { + .suspend = chip_suspend, + .resume = chip_resume, +}; + + + + +static const struct i2c_device_id chip_ids[] = { + {"lt8911exb", 0}, + { } +}; +MODULE_DEVICE_TABLE(i2c, chip_ids); + + +static const struct of_device_id chip_id_table[] = { + {.compatible = "lontium,lt8911exb"}, + { } +}; +MODULE_DEVICE_TABLE(of, chip_id_table); + + +static struct i2c_driver chip_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "lt8911exb", + .pm = &chip_pm_ops, + .of_match_table = chip_id_table, + + }, + .probe = chip_probe, + .remove = chip_remove, + .id_table = chip_ids, +}; + + +module_i2c_driver(chip_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("LT8911EXB driver"); +MODULE_AUTHOR("Tony "); diff --git a/source/linux-5.10/drivers/video/lt8911exb/Makefile b/source/linux-5.10/drivers/video/lt8911exb/Makefile new file mode 100755 index 000000000..96c3a1773 --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/Makefile @@ -0,0 +1,5 @@ + +lt8911exb-y := LontiumDrv.o LT8911EXB_Main.o OcmI2cMaster.o lt8911.o + +obj-$(CONFIG_LT8911EXB) += lt8911exb.o + diff --git a/source/linux-5.10/drivers/video/lt8911exb/OcmI2cMaster.c b/source/linux-5.10/drivers/video/lt8911exb/OcmI2cMaster.c new file mode 100755 index 000000000..305d2444b --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/OcmI2cMaster.c @@ -0,0 +1,72 @@ +#include "include/include.h" + + + +static unsigned char g_ucLogLevel = LOG_DEBUG; +static char *messageTypeStr[] = {"DEBUG","INFO","WARN", "ERROR","CRIT"}; + +//void Ocm_PrintLevel_Set(unsigned char ucLvl) +//{ +// g_ucLogLevel = ucLvl; +//} + +void LTLog(unsigned char ucLvl, const char *fmt, ...) +{ + char buf[MAX_NUMBER_BYTES] = {0}; + va_list args; + if (ucLvl > LOG_NOTRACE) + { + return; + } + + //´òÓ¡´óÓÚµÈÓڸü¶±ðµÄ×Ö·û´® + if(ucLvl >= g_ucLogLevel) + { + va_start(args, fmt); + vsprintf(buf, fmt, args); + va_end(args); + //×ó¶ÔÆë5¸ö×Ö·û + printk("\n[%-5s] %s", messageTypeStr[ucLvl], buf); + } +} + + + + +int HDMI_WriteI2C_Byte(u8 addr,u8 data) +{ + int ret = 0; + + + ret = regmap_write(lt8911exb->chip_regmap, addr, data); + + if (ret < 0) { + printk("regmap_write error: (0x%02x 0x%02x 0x%02x) %d", + lt8911exb->trans_i2c->addr, addr, data, ret); + return ret; + } + + + return 0; +} + +int HDMI_ReadI2C_Byte(u8 addr) +{ + int ret = 0; + unsigned int val = 0; + + ret = regmap_read(lt8911exb->chip_regmap, addr, &val); + + if (ret < 0) { + printk("regmap_read error: (0x%02x 0x%02x) %d", + lt8911exb->trans_i2c->addr, addr, ret); + + return ret; + } + + return (u8)val; +} + + +EXPORT_SYMBOL(HDMI_WriteI2C_Byte); +EXPORT_SYMBOL(HDMI_ReadI2C_Byte); diff --git a/source/linux-5.10/drivers/video/lt8911exb/doc/LT8911EXB Linux Driver Introduction document (English).docx b/source/linux-5.10/drivers/video/lt8911exb/doc/LT8911EXB Linux Driver Introduction document (English).docx new file mode 100755 index 000000000..a50187795 Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/doc/LT8911EXB Linux Driver Introduction document (English).docx differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/doc/LT8911EXB Linux Driver Introduction document (English).pdf b/source/linux-5.10/drivers/video/lt8911exb/doc/LT8911EXB Linux Driver Introduction document (English).pdf new file mode 100755 index 000000000..1d0f5334a Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/doc/LT8911EXB Linux Driver Introduction document (English).pdf differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/include/LT8911EXB_Main.h b/source/linux-5.10/drivers/video/lt8911exb/include/LT8911EXB_Main.h new file mode 100755 index 000000000..955acde8e --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/include/LT8911EXB_Main.h @@ -0,0 +1,11 @@ +#ifndef _LT8911EXB_MAIN_H_ +#define _LT8911EXB_MAIN_H_ + + + + +extern bool g_irq_flag; +extern int LT8911EXB_Main(void *data); + + +#endif diff --git a/source/linux-5.10/drivers/video/lt8911exb/include/LontiumDrv.h b/source/linux-5.10/drivers/video/lt8911exb/include/LontiumDrv.h new file mode 100755 index 000000000..41e1dd45b --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/include/LontiumDrv.h @@ -0,0 +1,27 @@ +#ifndef _LONTIUMDRV_H_ +#define _LONTIUMDRV_H_ + + +struct _lt8911exb{ + struct device *dev; + struct mutex ocm_lock; + struct gpio_desc *reset_gpio; + struct gpio_desc *power_gpio; + struct i2c_client *trans_i2c; + struct regmap *chip_regmap; +}; + + + +typedef struct +{ + u8 address; // ¼Ä´æÆ÷µØÖ· + u8 value; // ¼Ä´æÆ÷Öµ +} Chip_Control_Args; + + +extern struct _lt8911exb *lt8911exb; +extern atomic_t thread_should_stop; + + +#endif diff --git a/source/linux-5.10/drivers/video/lt8911exb/include/OcmI2cMaster.h b/source/linux-5.10/drivers/video/lt8911exb/include/OcmI2cMaster.h new file mode 100755 index 000000000..1148e32d7 --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/include/OcmI2cMaster.h @@ -0,0 +1,22 @@ +#ifndef _OCMI2CMASTER_H_ +#define _OCMI2CMASTER_H_ + +#define MAX_NUMBER_BYTES 128 + +typedef enum +{ + LOG_DEBUG =0x00, + LOG_INFO, + LOG_WARN, + LOG_ERROR, + LOG_CRITICAL, + LOG_NOTRACE, +} LT_LogLevel; + +void LTLog(unsigned char ucLvl, const char *fmt, ...); + + +extern int HDMI_WriteI2C_Byte(u8 addr,u8 data); +extern int HDMI_ReadI2C_Byte(u8 addr); + +#endif diff --git a/source/linux-5.10/drivers/video/lt8911exb/include/include.h b/source/linux-5.10/drivers/video/lt8911exb/include/include.h new file mode 100755 index 000000000..8677b1745 --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/include/include.h @@ -0,0 +1,39 @@ +#ifndef _INCLUDE_H_ +#define _INCLUDE_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + + +#include "type.h" +#include "LontiumDrv.h" + +#include "LT8911EXB_Main.h" +#include "lt8911.h" + +#include "OcmI2cMaster.h" + + +#endif diff --git a/source/linux-5.10/drivers/video/lt8911exb/include/lt8911.h b/source/linux-5.10/drivers/video/lt8911exb/include/lt8911.h new file mode 100755 index 000000000..0465481f5 --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/include/lt8911.h @@ -0,0 +1,72 @@ +#ifndef _LT8911EXB_H_ +#define _LT8911EXB_H_ + +//////////////////////LT8911 Config/////////////////// +//#define _1920x1200_eDP_Panel_ +#define _1080P_eDP_Panel_ +//#define _1366x768_eDP_Panel_ +//#define _1280x800_eDP_Panel_ +//#define _1600x900_eDP_Panel_ + +#define SCRAMBLE_MODE 0x00 //0x80: edp, 0x00: dp + +//#define sync_polarity 0x00 //0x00: no_adj; 0x20: vs_adj; 0x10: hs_adj; 0x30: H/Vs adj; + +//#define _6bit_ + +//#define _dither_enable_ + +#define _eDP_2G7_ +//#define _eDP_1G62_ + +#define _link_train_enable_ + +//////////option for debug/////////// +//#define _read_edid_ +//#define _EDP_Pattern_ +//#define _Msa_Active_Only_ +#define _pcr_mk_printk_ +#define _htotal_stable_check_ + +//#define _gpio_sync_output_ +//#define sync_source 0x01 //gpio output lvds Rx sync +#define sync_source 0x02 //gpio output lvds portA sync +//#define sync_source 0x03 //gpio output lvds portB sync +//gpio2: de, gpio3: vs, gpio4: hs. + +struct video_timing{ +u16 hfp; +u16 hs; +u16 hbp; +u16 hact; +u16 htotal; +u16 vfp; +u16 vs; +u16 vbp; +u16 vact; +u16 vtotal; +u32 pclk_khz; +}; + +struct Lane_No{ +u8 swing_high_byte; +u8 swing_low_byte; +u8 emph_high_byte; +u8 emph_low_byte; +}; + + +extern struct video_timing video; + +extern void LT8911_Reset(void); +extern void LT8911_ChipID(void); +extern void LT8911_SetVideoTiming(struct video_timing *video_format); +extern void LT8911_Init(struct video_timing *video_format); +extern void LT8911_LinkTrain(void); +extern void LT8911_LinkTrainResultCheck(void); +extern void LT8911_video_check(void); +extern void LT8911_pcr_mk_printk(void); +extern void LT8911_htotal_stable_printk(void); +extern void LT8911_MainLoop(struct video_timing *video_format); + +#endif diff --git a/source/linux-5.10/drivers/video/lt8911exb/include/type.h b/source/linux-5.10/drivers/video/lt8911exb/include/type.h new file mode 100755 index 000000000..7884ab530 --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/include/type.h @@ -0,0 +1,10 @@ +#ifndef _TYPE_H_ +#define _TYPE_H_ + + +#define HIGH 1 +#define LOW 0 + + + +#endif diff --git a/source/linux-5.10/drivers/video/lt8911exb/lt8911.c b/source/linux-5.10/drivers/video/lt8911exb/lt8911.c new file mode 100755 index 000000000..b1dea190a --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/lt8911.c @@ -0,0 +1,1027 @@ +#include "include/include.h" + +#ifdef _1080P_eDP_Panel_ +#define LANE_CNT 2 +#define PCR_PLL_PREDIV 0x40 +#define PCR_M 0x17 //148.5M //hfp, hs, hbp,hact,htotal,vfp, vs, vbp, vact,vtotal, +struct video_timing video ={88, 44, 148,1920, 2200, 4, 5, 36, 1080, 1125, 148500}; +//const struct video_timing video ={40, 40, 80,1920, 2200, 3, 5, 23, 1080, 1111, 148500}; +#endif + +#ifdef _1366x768_eDP_Panel_ +#define LANE_CNT 1 +#define PCR_PLL_PREDIV 0x40 +#define PCR_M 0x17 //74M + //hfp, hs, hbp,hact,htotal,vfp, vs, vbp, vact,vtotal, +struct video_timing video = {100, 26,100,1366, 1592, 10, 10, 10, 768, 798, 76225}; +#endif + +u8 EDID_DATA[128] = {0}; +static bool edp_idle_flag = 1; + +#define MSA_SW_MODE 0x80 //MSA from register +#define MSA_HW_MODE 0x00 //MSA from video check + +#define EDP_IDLE_PTN_ON 0x04 +#define EDP_IDLE_PTN_OFF 0x00 + +//=======================================// +#define _MIPI_Lane_ 4 // 3 /2 / 1 + +#define _MIPI_data_PN_Swap_En 0xF0 +#define _MIPI_data_PN_Swap_Dis 0x00 + +#define _MIPI_data_PN_ _MIPI_data_PN_Swap_Dis + +//------------------------------------------// + +#define _No_swap_ 0x00 // 3210 default +#define _MIPI_data_3210_ 0 // default +#define _MIPI_data_0123_ 21 +#define _MIPI_data_2103_ 20 + +#define _MIPI_data_sequence_ _No_swap_ + +/* + LT8911EXB pin MIPI RX + D3��37��38�� D3 2 3 2 1 1 3 2 3 2 0 0 3 0 3 0 1 1 2 0 2 0 1 1 + D2��40��41�� D2 3 1 1 2 3 2 3 0 0 2 3 0 3 1 1 0 3 0 2 1 1 0 2 + D1��44��45�� D1 1 2 3 3 2 0 1 2 3 3 2 1 1 0 3 3 0 1 1 0 2 2 0 + D0��47��48�� D0 0 0 0 0 0 1 0 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 + + 0xD003 Reg value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 + //*/ +//===========================================// + +#define _eDP_data_PN_Swap_En 0xF0 // Please refer to the notes below +#define _eDP_data_PN_Swap_Dis 0x00 + +#define _eDP_data_PN_ _eDP_data_PN_Swap_Dis // defailt ; disable + +/* eDP data P/N polarity swap +bit7 RGD_MLCTRL_LANE3_RVSD_EN + 1 = data of lane3 polarity swap; + 0 = normal. + +bit6 RGD_MLCTRL_LANE2_RVSD_EN + 1 = data of lane2 polarity swap; + 0 = normal. + +bit5 RGD_MLCTRL_LANE1_RVSD_EN + 1 = data of lane1 polarity swap; + 0 = normal. + +bit4 RGD_MLCTRL_LANE0_RVSD_EN + 1 = data of lane0 polarity swap; + 0 = normal. +//*/ + +//------------------------------------------// + +#define _Lane0_data_ 0 +#define _Lane1_data_ 1 +#define _Lane2_data_ 2 +#define _Lane3_data_ 3 + +#define _eDP_data3_select_ (_Lane3_data_ << 6) // default; _Lane3_data_select_ is lane3 +#define _eDP_data2_select_ (_Lane2_data_ << 4) // default; _Lane2_data_select_ is lane2 + +#define _eDP_data1_select_ (_Lane1_data_ << 2) // default; _Lane1_data_select_ is lane1 +#define _eDP_data0_select_ (_Lane0_data_ << 0) // default; _Lane0_data_select_ is lane0 + +// example:lane1 and lane0 swap +//#define _eDP_data1_select_ (_Lane0_data_ << 2) // default _Lane1_data_select_ is lane0 +//#define _eDP_data0_select_ (_Lane1_data_ << 0) // default _Lane0_data_select_ is lane1 + +#define _eDP_data_No_swap_ 0xe4 // default + +#define _eDP_data_sequence_ _eDP_data_No_swap_ // default, no swap +// #define _eDP_data_sequence_ (_eDP_data3_select_ + _eDP_data2_select_ + _eDP_data1_select_ + _eDP_data0_select_) + + +//===========================================// + + +//init power gpio level and reset chip +void LT8911_Reset(void) +{ + gpiod_set_value(lt8911exb->power_gpio,1); + msleep(5); + printk("set power High level "); + + //complete chip reset logic + gpiod_set_value(lt8911exb->reset_gpio,1); + msleep(5); + gpiod_set_value(lt8911exb->reset_gpio,0); + msleep(5); + gpiod_set_value(lt8911exb->reset_gpio,1); + msleep(5); + printk("reset chip"); +} + +void LT8911_ChipID(void) +{ + HDMI_WriteI2C_Byte(0xff,0x81);//register bank + HDMI_WriteI2C_Byte(0x08,0x7f); + printk("\r\nLT8911EX chip ID:%x,",HDMI_ReadI2C_Byte(0x00)); + printk("%x, ",HDMI_ReadI2C_Byte(0x01)); + printk("%x, ",HDMI_ReadI2C_Byte(0x02)); +} + +void LT8911_SetVideoTiming(struct video_timing *video_format) +{ + + // u32 pclk_khz; + // u8 dessc_m; + + //edp msa + HDMI_WriteI2C_Byte(0xff,0xa8); + HDMI_WriteI2C_Byte(0x2d,0x88); //bit[7]��o1 = register msa, 0 = hardware msa + +#ifdef _Msa_Active_Only_ + HDMI_WriteI2C_Byte(0x05,0x00); + HDMI_WriteI2C_Byte(0x06,0x00);//htotal + HDMI_WriteI2C_Byte(0x07,0x00); + HDMI_WriteI2C_Byte(0x08,0x00);//h_start + HDMI_WriteI2C_Byte(0x09,0x00); + HDMI_WriteI2C_Byte(0x0a,0x00); //hsa + HDMI_WriteI2C_Byte(0x0b,(u8)(video_format->hact/256)); + HDMI_WriteI2C_Byte(0x0c,(u8)(video_format->hact%256)); //hactive + HDMI_WriteI2C_Byte(0x0d,0x00); + HDMI_WriteI2C_Byte(0x0e,0x00);//vtotal + HDMI_WriteI2C_Byte(0x11,0x00); + HDMI_WriteI2C_Byte(0x12,0x00); + HDMI_WriteI2C_Byte(0x14,0x00); + HDMI_WriteI2C_Byte(0x15,(u8)(video_format->vact/256)); + HDMI_WriteI2C_Byte(0x16,(u8)(video_format->vact%256)); //vactive + +#else + HDMI_WriteI2C_Byte(0x05,(u8)(video_format->htotal/256)); + HDMI_WriteI2C_Byte(0x06,(u8)(video_format->htotal%256));//htotal + HDMI_WriteI2C_Byte(0x07,(u8)((video_format->hs+video_format->hbp)/256)); + HDMI_WriteI2C_Byte(0x08,(u8)((video_format->hs+video_format->hbp)%256));//h_start + HDMI_WriteI2C_Byte(0x09,(u8)(video_format->hs/256)); + HDMI_WriteI2C_Byte(0x0a,(u8)(video_format->hs%256)); //hsa + HDMI_WriteI2C_Byte(0x0b,(u8)(video_format->hact/256)); + HDMI_WriteI2C_Byte(0x0c,(u8)(video_format->hact%256)); //hactive + HDMI_WriteI2C_Byte(0x0d,(u8)(video_format->vtotal/256)); + HDMI_WriteI2C_Byte(0x0e,(u8)(video_format->vtotal%256));//vtotal + HDMI_WriteI2C_Byte(0x11,(u8)((video_format->vs+video_format->vbp)/256)); + HDMI_WriteI2C_Byte(0x12,(u8)((video_format->vs+video_format->vbp)%256));//v_start + HDMI_WriteI2C_Byte(0x14,(u8)(video_format->vs%256)); //vsa + HDMI_WriteI2C_Byte(0x15,(u8)(video_format->vact/256)); + HDMI_WriteI2C_Byte(0x16,(u8)(video_format->vact%256)); //vactive +#endif +} + + + +void LT8911_MIPI_Video_Timing(struct video_timing *video_format) +{ + HDMI_WriteI2C_Byte(0xff,0xd0); + HDMI_WriteI2C_Byte(0x0d,(u8)(video_format->vtotal/256)); + HDMI_WriteI2C_Byte(0x0e,(u8)(video_format->vtotal%256));//vtotal + HDMI_WriteI2C_Byte(0x0f,(u8)(video_format->vact/256)); + HDMI_WriteI2C_Byte(0x10,(u8)(video_format->vact%256)); //vactive + HDMI_WriteI2C_Byte(0x11,(u8)(video_format->htotal/256)); + HDMI_WriteI2C_Byte(0x12,(u8)(video_format->htotal%256));//htotal + HDMI_WriteI2C_Byte(0x13,(u8)(video_format->hact/256)); + HDMI_WriteI2C_Byte(0x14,(u8)(video_format->hact%256)); //hactive + HDMI_WriteI2C_Byte(0x15,(u8)(video_format->vs%256)); //vsa + HDMI_WriteI2C_Byte(0x16,(u8)(video_format->hs%256)); //hsa + HDMI_WriteI2C_Byte(0x17,(u8)(video_format->vfp/256)); + HDMI_WriteI2C_Byte(0x18,(u8)(video_format->vfp%256)); //vfp + HDMI_WriteI2C_Byte(0x19,(u8)(video_format->hfp/256)); + HDMI_WriteI2C_Byte(0x1a,(u8)(video_format->hfp%256)); //hfp +} + +void LT8911_Init(struct video_timing *video_format) +{ + u8 i; + u8 pcr_m; + u32 pclk; + u8 pcr_pll_postdiv; + /* init */ + HDMI_WriteI2C_Byte(0xff,0x81); + HDMI_WriteI2C_Byte(0x08,0x7f); //i2c over aux issue + HDMI_WriteI2C_Byte(0x49,0xff); //enable 0x87xx + + HDMI_WriteI2C_Byte(0xff,0x82); //GPIO test output + HDMI_WriteI2C_Byte(0x5a,0x0e); + + //for power consumption// + HDMI_WriteI2C_Byte(0xff,0x81); + HDMI_WriteI2C_Byte(0x05,0x06); + HDMI_WriteI2C_Byte(0x43,0x00); + HDMI_WriteI2C_Byte(0x44,0x1f); + #if(LANE_CNT == 4) + HDMI_WriteI2C_Byte(0x45,0xff); + HDMI_WriteI2C_Byte(0x46,0xfe); + #else + HDMI_WriteI2C_Byte(0x45,0xf7); + HDMI_WriteI2C_Byte(0x46,0xf6); + #endif + HDMI_WriteI2C_Byte(0x49,0x7f); + + HDMI_WriteI2C_Byte(0xff,0x82); + #if(LANE_CNT == 4) + HDMI_WriteI2C_Byte(0x12,0xff); + #elif (LANE_CNT == 2) + HDMI_WriteI2C_Byte(0x12,0x33); + #else // 1 lane eDP + HDMI_WriteI2C_Byte(0x12,0x11); + #endif + + /* mipi Rx analog */ + HDMI_WriteI2C_Byte(0xff,0x82); + HDMI_WriteI2C_Byte(0x32,0x51); + HDMI_WriteI2C_Byte(0x35,0x22); //EQ current 0x42 + HDMI_WriteI2C_Byte(0x3a,0x77); //0x77:EQ 12.5db ,0x33:EQ 6.5db + HDMI_WriteI2C_Byte(0x3b,0x77); //0x77:EQ 12.5db ,0x33:EQ 6.5db + HDMI_WriteI2C_Byte(0x4c,0x0c); + HDMI_WriteI2C_Byte(0x4d,0x00); + + /* dessc_pcr pll analog */ + HDMI_WriteI2C_Byte(0xff,0x82); + HDMI_WriteI2C_Byte(0x6a,0x40); //final setting: 0x40 + HDMI_WriteI2C_Byte(0x6b,PCR_PLL_PREDIV); //0x44:pre-div = 2 + //HDMI_WriteI2C_Byte(0x6b,0x44); + + pclk = video_format->pclk_khz; + if(pclk< 88000) + { + HDMI_WriteI2C_Byte(0x6e,0x82); + pcr_pll_postdiv = 0x08; + } + else + if(pclk < 176000) + { + HDMI_WriteI2C_Byte(0x6e,0x81); + pcr_pll_postdiv = 0x04; + } + else + { + HDMI_WriteI2C_Byte(0x6e,0x80); + pcr_pll_postdiv = 0x02; + } + + /* dessc pll digital */ + HDMI_WriteI2C_Byte(0xff,0x85); + HDMI_WriteI2C_Byte(0xa9,0x31); + HDMI_WriteI2C_Byte(0xaa,0x17); + HDMI_WriteI2C_Byte(0xab,0xba); + HDMI_WriteI2C_Byte(0xac,0xe1); + HDMI_WriteI2C_Byte(0xad,0x47); + HDMI_WriteI2C_Byte(0xae,0x01); + HDMI_WriteI2C_Byte(0xae,0x11); + + /* Digital Top */ + HDMI_WriteI2C_Byte(0xff,0x85); + HDMI_WriteI2C_Byte(0xc0,0x01); //select mipi Rx + #ifdef _6bit_ + HDMI_WriteI2C_Byte(0xb0,0xd0); //enable dither + #else // 8 bit + HDMI_WriteI2C_Byte(0xb0,0x00); //disable dither + #endif + + /* mipi Rx Digital */ + HDMI_WriteI2C_Byte(0xff, 0xd0); + + HDMI_WriteI2C_Byte( 0x00, _MIPI_data_PN_ + _MIPI_Lane_ % 4 ); // 0: 4 Lane / 1: 1 Lane / 2 : 2 Lane / 3: 3 Lane + //HDMI_WriteI2C_Byte(0x00, 0x00); //0x03: 3lanes, 0x00: 4lanes + HDMI_WriteI2C_Byte(0x02, 0x08); //settle + HDMI_WriteI2C_Byte( 0x03, _MIPI_data_sequence_ ); // default is 0x00 + HDMI_WriteI2C_Byte(0x08, 0x00); + + HDMI_WriteI2C_Byte(0x0c, 0x80); //fifo position + HDMI_WriteI2C_Byte(0x1c, 0x80); //fifo position + HDMI_WriteI2C_Byte(0x24, 0x70); //pcr mode( de hs vs) + + //HDMI_WriteI2C_Byte(0x2d, 0x1f); //M up limit + HDMI_WriteI2C_Byte(0x31, 0x0a); //M down limit + + /*stage1 hs mode*/ + HDMI_WriteI2C_Byte(0x25, 0x90); //line limit + HDMI_WriteI2C_Byte(0x2a, 0x3a); //step in limit + HDMI_WriteI2C_Byte(0x21, 0x4f); //hs_step + HDMI_WriteI2C_Byte(0x22, 0xff); + + /*stage2 de mode*/ + HDMI_WriteI2C_Byte(0x0a, 0x02); //de adjust pre line + HDMI_WriteI2C_Byte(0x38, 0x02); //de_threshold 1 + HDMI_WriteI2C_Byte(0x39, 0x04); //de_threshold 2 + HDMI_WriteI2C_Byte(0x3a, 0x08); //de_threshold 3 + HDMI_WriteI2C_Byte(0x3b, 0x10); //de_threshold 4 + + HDMI_WriteI2C_Byte(0x3f, 0x02); //de_step 1 + HDMI_WriteI2C_Byte(0x40, 0x04); //de_step 2 + HDMI_WriteI2C_Byte(0x41, 0x08); //de_step 3 + HDMI_WriteI2C_Byte(0x42, 0x10); //de_step 4 + + /*stage2 hs mode*/ + HDMI_WriteI2C_Byte(0x1e, 0x01); // hs threshold + HDMI_WriteI2C_Byte(0x23, 0xf0); // hs step + + HDMI_WriteI2C_Byte(0x2b, 0x80); //stable out // V1.8 20200417 + + pcr_m = (u8)( pclk * pcr_pll_postdiv / 25 / 1000 ); + #ifdef _EDP_Pattern_ + HDMI_WriteI2C_Byte(0x26,(pcr_m|0x80)); + #else + HDMI_WriteI2C_Byte(0x26,pcr_m); + #endif + +// #ifndef _1080P_eDP_Panel_ +// LT8911_MIPI_Video_Timing(&video); //defualt setting is 1080P +// #endif + + LT8911_MIPI_Video_Timing(&video); //defualt setting is 1080P + + HDMI_WriteI2C_Byte(0xff,0x81); //PCR reset + HDMI_WriteI2C_Byte(0x03,0x7b); + HDMI_WriteI2C_Byte(0x03,0xff); + + /* Txpll 2.7G*/ +#ifdef _eDP_2G7_ + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x19, 0x31 ); + // HDMI_WriteI2C_Byte( 0x1a, 0x36 ); // sync m + HDMI_WriteI2C_Byte( 0x1a, 0x1b ); + HDMI_WriteI2C_Byte( 0x1b, 0x00 ); // sync_k [7:0] + HDMI_WriteI2C_Byte( 0x1c, 0x00 ); // sync_k [13:8] + + // txpll Analog + HDMI_WriteI2C_Byte( 0xff, 0x82 ); + HDMI_WriteI2C_Byte( 0x09, 0x00 ); // div hardware mode, for ssc. + + // HDMI_WriteI2C_Byte( 0x01, 0x18 );// default : 0x18 + HDMI_WriteI2C_Byte( 0x02, 0x42 ); + HDMI_WriteI2C_Byte( 0x03, 0x00 ); // txpll en = 0 + HDMI_WriteI2C_Byte( 0x03, 0x01 ); // txpll en = 1 + // HDMI_WriteI2C_Byte( 0x04, 0x3a );// default : 0x3A + HDMI_WriteI2C_Byte(0x0a,0x1b); + HDMI_WriteI2C_Byte(0x04,0x2a); + + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x0c, 0x10 ); // cal en = 0 + + HDMI_WriteI2C_Byte( 0xff, 0x81 ); + HDMI_WriteI2C_Byte( 0x09, 0xfc ); + HDMI_WriteI2C_Byte( 0x09, 0xfd ); + + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x0c, 0x11 ); // cal en = 1 + + // ssc + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x13, 0x83 ); + HDMI_WriteI2C_Byte( 0x14, 0x41 ); + HDMI_WriteI2C_Byte( 0x16, 0x0a ); + HDMI_WriteI2C_Byte( 0x18, 0x0a ); + HDMI_WriteI2C_Byte( 0x19, 0x33 ); +#endif + +#ifdef _eDP_1G62_ + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x19, 0x31 ); + HDMI_WriteI2C_Byte( 0x1a, 0x20 ); // sync m + HDMI_WriteI2C_Byte( 0x1b, 0x19 ); // sync_k [7:0] + HDMI_WriteI2C_Byte( 0x1c, 0x99 ); // sync_k [13:8] + + // txpll Analog + HDMI_WriteI2C_Byte( 0xff, 0x82 ); + HDMI_WriteI2C_Byte( 0x09, 0x00 ); // div hardware mode, for ssc. + // HDMI_WriteI2C_Byte( 0x01, 0x18 );// default : 0x18 + HDMI_WriteI2C_Byte( 0x02, 0x42 ); + HDMI_WriteI2C_Byte( 0x03, 0x00 ); // txpll en = 0 + HDMI_WriteI2C_Byte( 0x03, 0x01 ); // txpll en = 1 + // HDMI_WriteI2C_Byte( 0x04, 0x3a );// default : 0x3A + + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x0c, 0x10 ); // cal en = 0 + + HDMI_WriteI2C_Byte( 0xff, 0x81 ); + HDMI_WriteI2C_Byte( 0x09, 0xfc ); + HDMI_WriteI2C_Byte( 0x09, 0xfd ); + + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x0c, 0x11 ); // cal en = 1 + + //ssc + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + HDMI_WriteI2C_Byte( 0x13, 0x83 ); + HDMI_WriteI2C_Byte( 0x14, 0x41 ); + HDMI_WriteI2C_Byte( 0x16, 0x0a ); + HDMI_WriteI2C_Byte( 0x18, 0x0a ); + HDMI_WriteI2C_Byte( 0x19, 0x33 ); +#endif + + HDMI_WriteI2C_Byte( 0xff, 0x87 ); + + for(i=0;i<5;i++) //Check Tx PLL + { + msleep(5); + if (HDMI_ReadI2C_Byte(0x37)&0x02) + { + printk("\r\nLT8911 tx pll locked"); + HDMI_WriteI2C_Byte(0xff,0x87); + HDMI_WriteI2C_Byte(0x1a,0x36); + HDMI_WriteI2C_Byte(0xff,0x82); + HDMI_WriteI2C_Byte(0x0a,0x36); + HDMI_WriteI2C_Byte(0x04,0x3a); + break; + } + else + { + printk("\r\nLT8911 tx pll unlocked"); + HDMI_WriteI2C_Byte(0xff,0x81); + HDMI_WriteI2C_Byte(0x09,0xfc); + HDMI_WriteI2C_Byte(0x09,0xfd); + HDMI_WriteI2C_Byte(0xff,0x87); + HDMI_WriteI2C_Byte(0x0c,0x10); + HDMI_WriteI2C_Byte(0x0c,0x11); + } + } + + HDMI_WriteI2C_Byte( 0xff, 0xac ); // Change Reg bank + HDMI_WriteI2C_Byte( 0x15, _eDP_data_sequence_ ); // eDP data swap + HDMI_WriteI2C_Byte( 0x16, _eDP_data_PN_); // eDP P / N swap + + // AUX reset + HDMI_WriteI2C_Byte( 0xff, 0x81 ); // Change Reg bank + HDMI_WriteI2C_Byte( 0x07, 0xfe ); + HDMI_WriteI2C_Byte( 0x07, 0xff ); + HDMI_WriteI2C_Byte( 0x0a, 0xfc ); + HDMI_WriteI2C_Byte( 0x0a, 0xfe ); + + /* tx phy */ + HDMI_WriteI2C_Byte(0xff,0x82); + HDMI_WriteI2C_Byte(0x11,0x00); + HDMI_WriteI2C_Byte(0x13,0x10); + HDMI_WriteI2C_Byte(0x14,0x0c); + HDMI_WriteI2C_Byte(0x14,0x08); + HDMI_WriteI2C_Byte(0x13,0x20); + HDMI_WriteI2C_Byte(0xff,0x82); + HDMI_WriteI2C_Byte(0x0e,0x25); + //HDMI_WriteI2C_Byte(0x12,0xff); + HDMI_WriteI2C_Byte(0xff,0x80); + HDMI_WriteI2C_Byte(0x40,0x22); + + /*eDP Tx Digital */ + HDMI_WriteI2C_Byte(0xff,0xa8); + #ifdef _EDP_Pattern_ + HDMI_WriteI2C_Byte( 0x24, 0x50 ); // bit2 ~ bit 0 : test panttern image mode + HDMI_WriteI2C_Byte( 0x25, 0x70 ); // bit6 ~ bit 4 : test Pattern color + HDMI_WriteI2C_Byte( 0x27, 0x50 ); //0x50:Pattern; 0x10:mipi video + + // HDMI_WriteI2C_Byte( 0x2d, 0x00 ); // pure color setting + // HDMI_WriteI2C_Byte( 0x2d, 0x84 ); // black color + HDMI_WriteI2C_Byte( 0x2d, 0x88 ); // block + #else + HDMI_WriteI2C_Byte(0x27,0x10); //0x50:Pattern; 0x10:mipi video + //HDMI_WriteI2C_Byte(0x27,0x50); //0x50:Pattern; 0x10:mipi video + #endif + + #ifdef _6bit_ + HDMI_WriteI2C_Byte(0x17,0x00); + HDMI_WriteI2C_Byte(0x18,0x00); + #else + // _8bit_ + HDMI_WriteI2C_Byte( 0x17, 0x10 ); + HDMI_WriteI2C_Byte( 0x18, 0x20 ); + #endif + +// #ifndef _1080P_eDP_Panel_ +// LT8911_eDP_Video_Timing(&video); +// #endif + + HDMI_WriteI2C_Byte(0xff,0xa0); //nvid = 0x080000; + HDMI_WriteI2C_Byte(0x00,0x00); + HDMI_WriteI2C_Byte(0x01,0x80); +} + + void LT8911_InterruptEnable(void) + { + HDMI_WriteI2C_Byte(0xff,0x85); + HDMI_WriteI2C_Byte(0x08,0x3f); //fm clr + + HDMI_WriteI2C_Byte(0x65,0x7f); //vid chk hact clr + HDMI_WriteI2C_Byte(0x07,0x7f); //vid chk clr + } + +u8 DpcdRead(u32 Address) +{ + /*************************** + ע���С�˵�����! + ����Ĭ���Ǵ��ģʽ + + Pay attention to the Big-Endian and Little-Endian! + The default mode is Big-Endian here. + + ****************************/ + + u8 DpcdValue = 0x00; + u8 AddressH = 0x0f & (Address>>16); + u8 AddressM = 0xff & (Address>>8); + u8 AddressL = 0xff & Address ; + u8 reg; + + HDMI_WriteI2C_Byte(0xff,0xac); + HDMI_WriteI2C_Byte(0x00,0x00); //Soft Link train + HDMI_WriteI2C_Byte(0xff,0xa6); + HDMI_WriteI2C_Byte(0x2a,0x01); + + HDMI_WriteI2C_Byte(0xff,0xa6); + HDMI_WriteI2C_Byte(0x2b,(0x90|AddressH)); //CMD + HDMI_WriteI2C_Byte(0x2b,AddressM); //addr[15:8] + HDMI_WriteI2C_Byte(0x2b,AddressL); //addr[7:0] + HDMI_WriteI2C_Byte(0x2b,0x00); //data lenth + HDMI_WriteI2C_Byte(0x2c,0x00); //start Aux read edid + + msleep(10); //more than 10ms + reg = HDMI_ReadI2C_Byte(0x25); + if((reg&0x0f)== 0x0c) + { + if(HDMI_ReadI2C_Byte(0x39) == 0x22) + { + HDMI_ReadI2C_Byte(0x2b); + DpcdValue = HDMI_ReadI2C_Byte(0x2b); + } + else + goto no_reply; + } + else if((reg&0x0f)== 0x0a) + goto reply_nack; + else if((reg&0x0f)== 0x09) + goto reply_defer; + else + goto no_reply; + + printk("\r\nDpcdRead: 0x%x%x%x= 0x%x ",AddressH,AddressM,AddressL,DpcdValue); + + + return DpcdValue; +/*error handle*/ +no_reply: + printk("\r\nDpcdRead error: no_reply "); + return 0; +reply_nack: + printk("\r\nDpcdRead error: reply_nack "); + return 0; +reply_defer: + printk("\r\nDpcdRead error: reply_nack "); + return 0; +} + + +bool DpcdWrite(u32 Address,u8 value ) +{ + /*************************** + ע���С�˵�����! + ����Ĭ���Ǵ��ģʽ + + Pay attention to the Big-Endian and Little-Endian! + The default mode is Big-Endian here. + + ****************************/ + + u8 AddressH = 0x0f & (Address>>16); + u8 AddressM = 0xff & (Address>>8); + u8 AddressL = 0xff & Address ; + u8 reg; + printk("\r\nDpcdWrite: 0x%x,0x%x,0x%x= 0x%x ",AddressH,AddressM,AddressL,value); + + HDMI_WriteI2C_Byte(0xff,0xac); + HDMI_WriteI2C_Byte(0x00,0x00); //Soft Link train + HDMI_WriteI2C_Byte(0xff,0xa6); + HDMI_WriteI2C_Byte(0x2a,0x01); + + HDMI_WriteI2C_Byte(0xff,0xa6); + HDMI_WriteI2C_Byte(0x2b,(0x80|AddressH)); //CMD + HDMI_WriteI2C_Byte(0x2b,AddressM); //addr[15:8] + HDMI_WriteI2C_Byte(0x2b,AddressL); //addr[7:0] + HDMI_WriteI2C_Byte(0x2b,0x00); //data lenth + HDMI_WriteI2C_Byte(0x2b,value); //data lenth + HDMI_WriteI2C_Byte(0x2c,0x00); //start Aux read edid + + msleep(10); //more than 10ms + reg = HDMI_ReadI2C_Byte(0x25); + if((reg&0x0f)== 0x0c) + { + return 0; + } + else if((reg&0x0f)== 0x0a) + goto reply_nack; + else if((reg&0x0f)== 0x09) + goto reply_defer; + else + goto no_reply; + +/*error handle*/ +no_reply: + printk("\r\nDpcdRead error: no_reply "); + return 1; +reply_nack: + printk("\r\nDpcdRead error: reply_nack "); + return 1; +reply_defer: + printk("\r\nDpcdRead error: reply_nack "); + return 1; +} + /* +void LT8911_LinkTrain(void) +{ + printk("\r\nlink train start"); + + HDMI_WriteI2C_Byte(0xff,0xac); + HDMI_WriteI2C_Byte(0x00,0x60); //Soft Link train + HDMI_WriteI2C_Byte(0xff,0xa6); + HDMI_WriteI2C_Byte(0x2a,0x00); + + HDMI_WriteI2C_Byte(0xff,0x81); + HDMI_WriteI2C_Byte(0x07,0xfe); + HDMI_WriteI2C_Byte(0x07,0xff); + HDMI_WriteI2C_Byte(0x0a,0xfc); + HDMI_WriteI2C_Byte(0x0a,0xfe); + + + + HDMI_WriteI2C_Byte(0xff,0xa8); + HDMI_WriteI2C_Byte(0x2d,0x80); //edp output video ; + + HDMI_WriteI2C_Byte(0xff,0x85); + HDMI_WriteI2C_Byte(0x1a,LANE_CNT); + //HDMI_WriteI2C_Byte(0x13,0xd1); + HDMI_WriteI2C_Byte(0xff,0xac); + HDMI_WriteI2C_Byte(0x00,0x64); + HDMI_WriteI2C_Byte(0x01,0x0a); + HDMI_WriteI2C_Byte(0x0c,0x85); + HDMI_WriteI2C_Byte(0x0c,0xc5); + msleep(500); + + edp_idle_flag = 0; +} +*/ + void LT8911_LinkTrain(void) +{ + HDMI_WriteI2C_Byte( 0xff, 0x81 ); + HDMI_WriteI2C_Byte( 0x06, 0xdf ); // rset VID TX + HDMI_WriteI2C_Byte( 0x06, 0xff ); + + if(SCRAMBLE_MODE == 0x80) + { + /* Aux operater init */ + HDMI_WriteI2C_Byte( 0xff, 0xac ); + HDMI_WriteI2C_Byte( 0x00, 0x20 ); //Soft Link train + HDMI_WriteI2C_Byte( 0xff, 0xa6 ); + HDMI_WriteI2C_Byte( 0x2a, 0x01 ); + + DpcdWrite(0x10a,0x01); + } + + /* Aux setup */ + HDMI_WriteI2C_Byte( 0xff, 0xac ); + HDMI_WriteI2C_Byte( 0x00, 0x60 ); //Soft Link train + HDMI_WriteI2C_Byte(0xff,0xa6); + HDMI_WriteI2C_Byte(0x2a,0x00); + + HDMI_WriteI2C_Byte(0xff,0x81); + HDMI_WriteI2C_Byte(0x07,0xfe); + HDMI_WriteI2C_Byte(0x07,0xff); + HDMI_WriteI2C_Byte(0x0a,0xfc); + HDMI_WriteI2C_Byte(0x0a,0xfe); + + /* link train */ + HDMI_WriteI2C_Byte(0xff,0xa8); + HDMI_WriteI2C_Byte(0x2d,MSA_SW_MODE|EDP_IDLE_PTN_OFF); //edp output video ; + + HDMI_WriteI2C_Byte(0xff,0x85); + HDMI_WriteI2C_Byte(0x17,0xc0); + HDMI_WriteI2C_Byte(0x1a,LANE_CNT); + HDMI_WriteI2C_Byte(0xa1,(SCRAMBLE_MODE|0x02)); //scramble mode + //HDMI_WriteI2C_Byte(0x13,0xd1); + +#ifdef _link_train_enable_ + HDMI_WriteI2C_Byte(0xff,0xac); + HDMI_WriteI2C_Byte(0x00,0x60); + HDMI_WriteI2C_Byte(0x01,0x0a); + HDMI_WriteI2C_Byte(0x0c,0x05); + HDMI_WriteI2C_Byte(0x0c,0x45); + //printk("\r\n\33[35mLT8911 link trian: hardware linktrain start...\033[37m"); + printk("LT8911 link trian: hardware linktrain start...\r\n"); +// msleep(500); +#else // NO_AUX_HANDSHAKE_LINK_TRAINING,�fFast training + HDMI_WriteI2C_Byte(0xff,0xac); + HDMI_WriteI2C_Byte(0x00,0x00); + HDMI_WriteI2C_Byte(0x01,0x0a); + HDMI_WriteI2C_Byte(0x14,0x80); + HDMI_WriteI2C_Byte(0x14,0x81); + msleep(50); + HDMI_WriteI2C_Byte(0x14,0x84); + msleep(50); + HDMI_WriteI2C_Byte(0x14,0xc0); + printk("\r\n\33[35mLT8911 link trian: no handshake linktrain\033[37m"); +#endif + + edp_idle_flag = 0; +} + + + +void LT8911_LinkTrainResultCheck(void) +{ +#ifdef _link_train_enable_ + u8 i; + u8 val; + //int ret; + + HDMI_WriteI2C_Byte(0xff,0xac); + for(i = 0; i< 10; i++) + { + val = HDMI_ReadI2C_Byte(0x82); + if(val & 0x20) + { + if((val & 0x1f)==0x1e){ + printk("\r\nLT8911_LinkTrainResultCheck: edp link train successed: 0x%x", val); + } + else{ + printk("\r\nLT8911_LinkTrainResultCheck: edp link train failed: 0x%x", val); + //while(1); + HDMI_WriteI2C_Byte(0xff,0xac); + HDMI_WriteI2C_Byte(0x00,0x00); + HDMI_WriteI2C_Byte(0x01,0x0a); + HDMI_WriteI2C_Byte(0x14,0x80); + HDMI_WriteI2C_Byte(0x14,0x81); + msleep(50); + HDMI_WriteI2C_Byte(0x14,0x84); + msleep(50); + HDMI_WriteI2C_Byte(0x14,0xc0); + printk("\r\nLT8911_LinkTrainResultCheck: Enable eDP video output while linktrian fail"); + //while(1); + } + + val = HDMI_ReadI2C_Byte(0x83); + printk("\r\nLT8911_LinkTrainResultCheck: panel link rate: 0x%x",val); + val = HDMI_ReadI2C_Byte(0x84); + printk("\r\nLT8911_LinkTrainResultCheck: panel link count: 0x%x",val); + return; + } + else + printk("\r\nLT8911_LinkTrainResultCheck: link trian on going..."); + msleep(100); + } +#endif +} + + +/* mipi should be ready before configuring below video check setting*/ +void LT8911_video_check(void) +{ + //u8 temp; + u32 reg=0x00; + printk("\r\n----------------------------------------------------------------------"); + /* mipi byte clk check*/ + HDMI_WriteI2C_Byte(0xff,0x85); + HDMI_WriteI2C_Byte(0x1d,0x00); //FM select byte clk + HDMI_WriteI2C_Byte(0x40,0xf7); + HDMI_WriteI2C_Byte(0x41,0x30); + HDMI_WriteI2C_Byte(0xa1,(SCRAMBLE_MODE|0x02)); //video chech from mipi + + HDMI_WriteI2C_Byte(0xff,0x81); //video check rst + HDMI_WriteI2C_Byte(0x09,0x7d); + HDMI_WriteI2C_Byte(0x09,0xfd); + + HDMI_WriteI2C_Byte(0xff,0x85); + msleep(30); + if(HDMI_ReadI2C_Byte(0x50)== 0x03) + { + reg = HDMI_ReadI2C_Byte(0x4d); + reg = reg*256 + HDMI_ReadI2C_Byte(0x4e); + reg = reg*256 + HDMI_ReadI2C_Byte(0x4f); + + printk("\r\nvideo check: mipi byteclk = %d",reg); + } + else + printk("\r\nvideo check: mipi clk unstable"); + + /* mipi vtotal check*/ + reg = HDMI_ReadI2C_Byte(0x76); + reg = reg*256 + HDMI_ReadI2C_Byte(0x77); + + printk("\r\nvideo check: Vtotal = %d",reg); + + /* mipi word count check*/ + HDMI_WriteI2C_Byte(0xff,0xd0); + reg = HDMI_ReadI2C_Byte(0x82); + reg = reg*256 + HDMI_ReadI2C_Byte(0x83); + reg = reg/3; + + printk("\r\nvideo check: Hact(word counter) = %d",reg); + //printk(reg); + + /* mipi Vact check*/ + reg = HDMI_ReadI2C_Byte(0x85); + reg = reg*256 + HDMI_ReadI2C_Byte(0x86); + + printk("\r\nvideo check: Vact = %d",reg); + //printk(reg); + + printk("\r\nlane0 settle: 0x%x ",HDMI_ReadI2C_Byte(0x88)); + printk("\r\nlane1 settle: 0x%x ",HDMI_ReadI2C_Byte(0x8a)); + printk("\r\nlane2 settle: 0x%x ",HDMI_ReadI2C_Byte(0x8c)); + printk("\r\nlane3 settle: 0x%x ",HDMI_ReadI2C_Byte(0x8e)); + + printk("\r\nlane0 sot: 0x%x ",HDMI_ReadI2C_Byte(0x89)); + printk("\r\nlane1 sot: 0x%x ",HDMI_ReadI2C_Byte(0x8b)); + printk("\r\nlane2 sot: 0x%x ",HDMI_ReadI2C_Byte(0x8d)); + printk("\r\nlane3 sot: 0x%x ",HDMI_ReadI2C_Byte(0x8f)); + printk("\r\n----------------------------------------------------------------------"); +} + +void LT8911_MainLoop(struct video_timing *video_format) +{ + u16 reg; + u16 vtotal; + static int flag_mipi_on = 1; + + vtotal = video_format->vtotal; + HDMI_WriteI2C_Byte(0xff,0x85); + //HDMI_WriteI2C_Byte(0x1d,0x00); //FM select byte clk + //HDMI_WriteI2C_Byte(0x40,0xf7); + //HDMI_WriteI2C_Byte(0x41,0x30); + HDMI_WriteI2C_Byte(0xa1,(SCRAMBLE_MODE|0x02)); //video chech from mipi + + HDMI_WriteI2C_Byte(0xff,0x81); //video check rst + HDMI_WriteI2C_Byte(0x09,0x7d); + HDMI_WriteI2C_Byte(0x09,0xfd); + msleep(50); + + HDMI_WriteI2C_Byte(0xff,0x85); + reg = HDMI_ReadI2C_Byte(0x76); + reg = reg*256 + HDMI_ReadI2C_Byte(0x77); + + //printk("\r\nPCR reset: %d",reg); + //printk("\r\nvtotal: %d",vtotal); + if((reg <= (vtotal + 3))&&(reg >= (vtotal - 3))) + { + if(!flag_mipi_on) + { + msleep(1000); + HDMI_WriteI2C_Byte(0xff,0x81); //PCR reset + HDMI_WriteI2C_Byte(0x03,0x7b); + HDMI_WriteI2C_Byte(0x03,0xff); + msleep(100); + HDMI_WriteI2C_Byte(0xff,0xa8); + HDMI_WriteI2C_Byte(0x2d,0x88); //edp disable idle pattern; + flag_mipi_on = 1; + printk("\r\nPCR reset0"); + } + + HDMI_WriteI2C_Byte(0xff,0xd0); + if((HDMI_ReadI2C_Byte(0x84)&0x40) == 0x00) + { + HDMI_WriteI2C_Byte(0xff,0x81); //PCR reset + HDMI_WriteI2C_Byte(0x03,0x7b); + HDMI_WriteI2C_Byte(0x03,0xff); + msleep(500); + printk("\r\nPCR reset1"); + } + else + { + +// printk("\r\npcr stable:%x, mk: %x, %x, %x, %x", +// HDMI_ReadI2C_Byte(0x84), +// HDMI_ReadI2C_Byte(0x94), +// HDMI_ReadI2C_Byte(0x95), +// HDMI_ReadI2C_Byte(0x96), +// HDMI_ReadI2C_Byte(0x97)); + +// if((HDMI_ReadI2C_Byte(0x94)==0x17)&&((HDMI_ReadI2C_Byte(0x95)==0x53)||(HDMI_ReadI2C_Byte(0x95)==0x47))) +// { +// return; +// } +// else +// { +// HDMI_WriteI2C_Byte(0xff,0x81); //PCR reset +// HDMI_WriteI2C_Byte(0x03,0x7b); +// HDMI_WriteI2C_Byte(0x03,0xff); +// msleep(500); +// printk("\r\nPCR reset2"); +// } + } + } + else + { + HDMI_WriteI2C_Byte(0xff,0xa8); + HDMI_WriteI2C_Byte(0x2d,0x8c); //edp enable idle pattern; + flag_mipi_on = 0; + } +} + + +void LT8911_pcr_mk_printk(void) +{ + #ifdef _pcr_mk_printk_ + u8 loopx = 0; + + for(loopx = 0; loopx < 30; loopx++) + { + HDMI_WriteI2C_Byte(0xff,0xd0); + //printk("\r\npcr stable bit[4]:%x, mk: %x, %x, %x, %x", + HDMI_ReadI2C_Byte(0x84), + HDMI_ReadI2C_Byte(0x94), + HDMI_ReadI2C_Byte(0x95), + HDMI_ReadI2C_Byte(0x96), + HDMI_ReadI2C_Byte(0x97); + msleep(500); + } + #endif +} + +void LT8911_htotal_stable_printk(void) +{ + #ifdef _htotal_stable_check_ + u8 loopx = 0; + u32 val; + + for(loopx = 0; loopx < 30; loopx++) + { + HDMI_WriteI2C_Byte(0xff,0x85); + val = HDMI_ReadI2C_Byte(0x90); + val = val*256 + HDMI_ReadI2C_Byte(0x91); + //printk("\r\nmipi htotal: %d ",val); + msleep(10); + } + #endif +} + +void LT8911_LinkTrainRresultDebug(void) +{ + u8 i; + u8 val; + + HDMI_WriteI2C_Byte(0xff,0xac); + for(i = 0; i< 10; i++) + { + val = HDMI_ReadI2C_Byte(0x82); + if(val & 0x20) + { + if((val & 0x1f)==0x1e) + { + //val = HDMI_ReadI2C_Byte(0x82); + printk("\r\nedp link train successed: %x", val); + } + else{ + //val = HDMI_ReadI2C_Byte(0x82); + printk("\r\nedp link train failed: %x", val); + } + val = HDMI_ReadI2C_Byte(0x83); + printk("\r\npanel link rate: %x",val); + val = HDMI_ReadI2C_Byte(0x84); + printk("\r\npanel link count: %x",val); + return; + } + else + printk("\r\nlink trian on going..."); + msleep(100); + } +} + + + +//void IntbInterruptFun(void) interrupt 7 +//{ +// g_irq_flag = 1; +//} +// +//void InterruptTaskHandle(void) +//{ +// if(g_irq_flag) // interrupt event happened +// { +// printk("\r\nirq task happened..."); +// +// HDMI_WriteI2C_Byte(0xff,0xa8); +// HDMI_WriteI2C_Byte(0x2d,0x84); //edp output idle pattern; +// +// msleep(1500); +// HDMI_WriteI2C_Byte(0xff,0x85); //clr LT +// HDMI_WriteI2C_Byte(0x08,0xc0); +// HDMI_WriteI2C_Byte(0x08,0x00); +// +// +// HDMI_WriteI2C_Byte(0x65,0xff); //vid chk hact clr +// HDMI_WriteI2C_Byte(0x65,0x7f); //vid chk hact clr +// +// HDMI_WriteI2C_Byte(0x07,0xff); //vid chk clr +// HDMI_WriteI2C_Byte(0x07,0x7f); //vid chk clr +// +// edp_idle_flag = 1; +// if(PIF == 0x08) //clear MCU interrupt flag to handle next interrupt request. +// { +// PIF = 0x00; +// clr_IE0; +// } +// g_irq_flag = 0; +// } +//} + diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IAB b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IAB new file mode 100755 index 000000000..0d62f9672 Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IAB differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IAD b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IAD new file mode 100755 index 000000000..65d9ac6ec Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IAD differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IMB b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IMB new file mode 100755 index 000000000..1f0362a4f Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IMB differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IMD b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IMD new file mode 100755 index 000000000..6982d34fe Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.IMD differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PFI b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PFI new file mode 100755 index 000000000..1a8d5222a Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PFI differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PO b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PO new file mode 100755 index 000000000..6a463b3de Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PO differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PR b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PR new file mode 100755 index 000000000..6b8299d76 Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PR differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PRI b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PRI new file mode 100755 index 000000000..b90c0a9e5 Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PRI differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PS b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PS new file mode 100755 index 000000000..067a928af Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.PS differ diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.SearchResults b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.SearchResults new file mode 100755 index 000000000..564b4da31 --- /dev/null +++ b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.SearchResults @@ -0,0 +1,4 @@ +---- LT8911_Init Matches (3 in 3 files) ---- +Lt8911.c (d:\ÁúѸ²úÆ·³ÌÐòÕûÀí(ÉîÛÚ)\lt8911\lt8911\lt8911exb\democode\for linux\lt8911exb_linux_driver_v1.0.2):void LT8911_Init(struct video_timing *video_format) +Lt8911.h (d:\ÁúѸ²úÆ·³ÌÐòÕûÀí(ÉîÛÚ)\lt8911\lt8911\lt8911exb\democode\for linux\lt8911exb_linux_driver_v1.0.2\include):extern void LT8911_Init(struct video_timing *video_format); +LT8911EXB_Main.c (d:\ÁúѸ²úÆ·³ÌÐòÕûÀí(ÉîÛÚ)\lt8911\lt8911\lt8911exb\democode\for linux\lt8911exb_linux_driver_v1.0.2): LT8911_Init(); diff --git a/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.WK3 b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.WK3 new file mode 100755 index 000000000..329cbb463 Binary files /dev/null and b/source/linux-5.10/drivers/video/lt8911exb/si/LT8911EXB.WK3 differ diff --git a/source/uboot-2021.10/configs/d211_demo128_nand_defconfig b/source/uboot-2021.10/configs/d211_demo128_nand_defconfig index db2ee33ec..49c1a8db5 100644 --- a/source/uboot-2021.10/configs/d211_demo128_nand_defconfig +++ b/source/uboot-2021.10/configs/d211_demo128_nand_defconfig @@ -138,8 +138,8 @@ CONFIG_DM_VIDEO=y CONFIG_DISPLAY=y CONFIG_ARTINCHIP_GRAPHICS=y CONFIG_VIDEO_ARTINCHIP=y -CONFIG_AIC_DISP_LVDS=y -CONFIG_AIC_PANEL_LVDS_GENERAL=y +CONFIG_AIC_DISP_MIPI_DSI=y +CONFIG_AIC_PANEL_DSI_SIMPLE=y # CONFIG_WATCHDOG is not set # CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_WDT=y diff --git a/source/uboot-2021.10/drivers/clk/artinchip/aic-cmu.c b/source/uboot-2021.10/drivers/clk/artinchip/aic-cmu.c index 9c3c9e7da..dc05b95e5 100644 --- a/source/uboot-2021.10/drivers/clk/artinchip/aic-cmu.c +++ b/source/uboot-2021.10/drivers/clk/artinchip/aic-cmu.c @@ -139,12 +139,16 @@ static struct aic_pll clk_plls[] = { 0, AIC_PLL_INT), CLK_PLL(CLK_PLL_INT1, PLL_INT1_GEN_REG, PLL_INT1_CFG_REG, 0, AIC_PLL_INT), + // CLK_PLL(CLK_PLL_FRA0, PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG, + // PLL_FRA0_SDM_REG, AIC_PLL_SDM), CLK_PLL(CLK_PLL_FRA0, PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG, - PLL_FRA0_SDM_REG, AIC_PLL_SDM), + PLL_FRA0_SDM_REG, AIC_PLL_FRA), CLK_PLL(CLK_PLL_FRA1, PLL_FRA1_GEN_REG, PLL_FRA1_CFG_REG, PLL_FRA1_SDM_REG, AIC_PLL_FRA), + // CLK_PLL_VIDEO(CLK_PLL_FRA2, PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG, + // PLL_FRA2_SDM_REG, AIC_PLL_SDM, 0, 1200000000), CLK_PLL_VIDEO(CLK_PLL_FRA2, PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG, - PLL_FRA2_SDM_REG, AIC_PLL_SDM, 0, 1200000000), + PLL_FRA2_SDM_REG, AIC_PLL_FRA, 0, 1200000000), }; diff --git a/source/uboot-2021.10/drivers/mtd/nand/spi/gigadevice.c b/source/uboot-2021.10/drivers/mtd/nand/spi/gigadevice.c index c5d1cf849..fadba3d02 100644 --- a/source/uboot-2021.10/drivers/mtd/nand/spi/gigadevice.c +++ b/source/uboot-2021.10/drivers/mtd/nand/spi/gigadevice.c @@ -192,6 +192,16 @@ static const struct spinand_info gigadevice_spinand_table[] = { SPINAND_HAS_QE_BIT, SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F2GM7UEY1G", + SPINAND_ID(0x92), + NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1), + NAND_ECCREQ(8, 512), + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5, + &write_cache_variants, + &update_cache_variants), + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), }; static int gigadevice_spinand_detect(struct spinand_device *spinand) diff --git a/source/uboot-2021.10/drivers/video/artinchip/display/panel/panel_dsi_simple.c b/source/uboot-2021.10/drivers/video/artinchip/display/panel/panel_dsi_simple.c index e088433f7..0e7decf4f 100644 --- a/source/uboot-2021.10/drivers/video/artinchip/display/panel/panel_dsi_simple.c +++ b/source/uboot-2021.10/drivers/video/artinchip/display/panel/panel_dsi_simple.c @@ -62,6 +62,15 @@ static struct aic_panel_funcs panel_funcs = { /* Init the videomode parameter, dts will override the initial value. */ static struct fb_videomode panel_vm = { + .pixclock = 150 * 1000 * 1000, + .xres = 1920, + .right_margin = 188, + .left_margin = 148, + .hsync_len = 44, + .yres = 1080, + .lower_margin = 4, + .upper_margin = 36, + .vsync_len = 5, .flag = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE }; diff --git a/source/uboot-2021.10/include/configs/image_cfg.json b/source/uboot-2021.10/include/configs/image_cfg.json new file mode 120000 index 000000000..a801252da --- /dev/null +++ b/source/uboot-2021.10/include/configs/image_cfg.json @@ -0,0 +1 @@ +/home/hyx/work/linuxOS_D21X/target/d211/demo128_nand/image_cfg.json \ No newline at end of file diff --git a/target/configs/d211_demo128_nand_defconfig b/target/configs/d211_demo128_nand_defconfig index a277e8dc5..44d738d75 100644 --- a/target/configs/d211_demo128_nand_defconfig +++ b/target/configs/d211_demo128_nand_defconfig @@ -35,7 +35,6 @@ BR2_LINUX_KERNEL_DEFCONFIG="d211_demo128_nand" BR2_LINUX_KERNEL_IMAGEGZ=y BR2_PACKAGE_LINUX_TOOLS_SELFTESTS=y # BR2_PACKAGE_AIC_AUTHORIZATION is not set -BR2_PACKAGE_LVGL_UI=y # BR2_PACKAGE_TEST_DVP is not set # BR2_PACKAGE_TEST_TOUCHSCREEN is not set BR2_PACKAGE_BUSYBOX_CONFIG="package/third-party/busybox/configs/d211_demo128_nand_defconfig" diff --git a/target/d211/common/env.txt b/target/d211/common/env.txt index 206b3cdc5..d2f8df84c 100644 --- a/target/d211/common/env.txt +++ b/target/d211/common/env.txt @@ -34,7 +34,7 @@ kernel_comp_size=0x1000000 # set_commonargs=setenv bootargs earlycon=${earlycon} earlyprintk rdinit=${init} initramfs_dbg=${ramfs_dbg} set_commonargs_recovery=setenv bootargs earlycon=${earlycon} earlyprintk rdinit=/linuxrc # Case 2: Mount rootfs directly -set_commonargs=setenv bootargs quiet earlycon=${earlycon} earlyprintk init=/linuxrc firmware_class.path=/etc/firmware +set_commonargs=setenv bootargs earlycon=${earlycon} earlyprintk init=/linuxrc firmware_class.path=/etc/firmware #=============================================================================== diff --git a/target/d211/demo128_nand/board.dts b/target/d211/demo128_nand/board.dts index d06f237bd..e5907f446 100644 --- a/target/d211/demo128_nand/board.dts +++ b/target/d211/demo128_nand/board.dts @@ -167,90 +167,31 @@ }; #endif - panel_rgb { - compatible = "artinchip,aic-general-rgb-panel"; - status = "disabled"; - - enable-gpios = <&gpio_e 19 GPIO_ACTIVE_HIGH>; - rgb-mode = ; - interface-format = ; - clock-phase = ; - data-order = ; - disp-dither = ; + panel_dsi { + compatible = "artinchip,aic-dsi-panel-simple"; u-boot,dm-pre-reloc; - - port { - u-boot,dm-pre-reloc; - panel_rgb_in: endpoint { - remote-endpoint = <&rgb0_out>; - u-boot,dm-pre-reloc; - }; - }; - - display-timings { - native-mode = <&timing0>; - u-boot,dm-pre-reloc; - timing0: 1024x600 { - clock-frequency = <52000000>; - hactive = <1024>; - vactive = <600>; - hback-porch = <160>; - hfront-porch = <160>; - hsync-len = <20>; - vback-porch = <12>; - vfront-porch = <20>; - vsync-len = <3>; - de-active = <1>; - pixelclk-active = <1>; - u-boot,dm-pre-reloc; - }; - }; - }; - - panel_lvds { - compatible = "artinchip,aic-general-lvds-panel"; - data-mapping = "vesa-24"; - data-channel = "single-link1"; + backlight = <&backlight>; status = "okay"; - u-boot,dm-pre-reloc; - enable-gpios = <&gpio_c 7 GPIO_ACTIVE_HIGH>; - sleep-gpios = <&gpio_a 3 GPIO_ACTIVE_HIGH>; + //reset-gpios = <&gpio_e 1 GPIO_ACTIVE_HIGH>; + port { - panel_lvds_in: endpoint { - remote-endpoint = <&lvds0_out>; - u-boot,dm-pre-reloc; - }; - }; - - display-timings { - native-mode = <&timing1>; u-boot,dm-pre-reloc; - timing1: 1024x600 { - clock-frequency = <52000000>; - hactive = <1024>; - vactive = <600>; - hback-porch = <160>; - hfront-porch = <160>; - hsync-len = <20>; - vback-porch = <20>; - vfront-porch = <12>; - vsync-len = <3>; - de-active = <1>; - pixelclk-active = <1>; + panel_dsi_in: endpoint { u-boot,dm-pre-reloc; + remote-endpoint = <&dsi0_out>; }; }; - }; + }; backlight: backlight { compatible = "pwm-backlight"; /* pwm node name; pwm device No.; period_ns; pwm_polarity */ - pwms = <&pwm 3 1000000 0>; + pwms = <&pwm 0 1000000 0>; brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>; default-brightness-level = <6>; u-boot,dm-pre-reloc; - status = "disabled"; + status = "okay"; }; rfkill_bt { compatible = "rfkill-gpio"; @@ -409,11 +350,16 @@ &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_b>; - status = "disabled"; - rtc@32 { - compatible = "epson,rx8010"; - reg = <0x32>; + status = "okay"; + + lt8911exb@29 { + status = "okay"; + compatible = "lontium,lt8911exb"; + reg = <0x29>; + reset-gpios = <&gpio_e 6 GPIO_ACTIVE_HIGH>; + power-gpios = <&gpio_e 2 GPIO_ACTIVE_HIGH>; }; + }; &i2c1 { @@ -431,10 +377,10 @@ &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins_a>; - status = "okay"; + status = "disabled"; gt9xx@5d { - status = "okay"; + status = "disabled"; compatible = "goodix,gt9xx"; reg = <0x5d>; reset-gpios = <&gpio_a 8 GPIO_ACTIVE_LOW>; @@ -610,9 +556,9 @@ }; }; - pwm3_pins_d: pwm3-3 { + pwm0_pins_d: pwm0-3 { pins { - pinmux = ; + pinmux = ; bias-disable; drive-strength = <3>; }; @@ -643,12 +589,12 @@ gpio_f: bank-5 { u-boot,dm-pre-reloc; }; - lvds1_pins: lvds1-0 { - u-boot,dm-pre-reloc; - pins { - u-boot,dm-pre-reloc; - }; - }; + dsi_pins: dsi-0 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + }; + }; uart0_pins_a: uart0-0 { u-boot,dm-pre-reloc; pins1 { @@ -664,6 +610,12 @@ u-boot,dm-pre-reloc; }; }; + pwm0_pins_d: pwm0-3 { + u-boot,dm-pre-reloc; + pins { + u-boot,dm-pre-reloc; + }; + }; sdmc1_pins: sdmc1-0 { u-boot,dm-pre-reloc; pins { @@ -683,7 +635,7 @@ aic,use_extclk; - status = "okay"; + status = "disabled"; gmac0_mdio: mdio { compatible = "aicmac-mdio"; @@ -718,7 +670,7 @@ &fb0 { artinchip,uboot-logo-on=<1>; - height-virtual = <1200>; + height-virtual = <2160>; u-boot,dm-pre-reloc; port { u-boot,dm-pre-reloc; @@ -739,6 +691,7 @@ port@0 { reg = <0>; + u-boot,dm-pre-reloc; de0_in: endpoint { remote-endpoint = <&fb0_out>; u-boot,dm-pre-reloc; @@ -747,48 +700,27 @@ port@1 { reg = <1>; + u-boot,dm-pre-reloc; de0_out: endpoint { - remote-endpoint = <&lvds0_in>; + remote-endpoint = <&dsi0_in>; u-boot,dm-pre-reloc; }; }; }; -&rgb0 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&lcd_rgb565_ld_pins>; - pinctrl-1 = <&lcd_rgb565_ld_sleep_pins>; - u-boot,dm-pre-reloc; - status = "disabled"; - port@0 { - reg = <0>; - u-boot,dm-pre-reloc; - rgb0_in: endpoint { - remote-endpoint = <&rgb0_in>; - u-boot,dm-pre-reloc; - }; - }; - - port@1 { - reg = <1>; - u-boot,dm-pre-reloc; - rgb0_out: endpoint { - remote-endpoint = <&panel_rgb_in>; - u-boot,dm-pre-reloc; - }; - }; -}; - -&lvds0 { +&dsi0 { pinctrl-names = "default"; - pinctrl-0 = <&lvds1_pins>; + pinctrl-0 = <&dsi_pins>; status = "okay"; u-boot,dm-pre-reloc; + data-lanes = <3 2 1 0>; + lane-polarities = <0 0 0 0>; port@0 { reg = <0>; - lvds0_in: endpoint { + u-boot,dm-pre-reloc; + dsi0_in: endpoint { remote-endpoint = <&de0_out>; u-boot,dm-pre-reloc; }; @@ -796,8 +728,9 @@ port@1 { reg = <1>; - lvds0_out: endpoint { - remote-endpoint = <&panel_lvds_in>; + u-boot,dm-pre-reloc; + dsi0_out: endpoint { + remote-endpoint = <&panel_dsi_in>; u-boot,dm-pre-reloc; }; }; @@ -877,10 +810,10 @@ }; &pwm { - status = "disabled"; + status = "okay"; u-boot,dm-pre-reloc; pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pins_d>; + pinctrl-0 = <&pwm0_pins_d>; /* mode: up-count, down-count, up-down-count action: none, low, high, inverse */ pwm0 { @@ -891,7 +824,7 @@ /* CBD, CBU, CAD, CAU, PRD, ZRO */ aic,action0 = "none", "none", "none", "low", "none", "high"; aic,action1 = "none", "none", "none", "high", "none", "low"; - status = "disabled"; + status = "okay"; u-boot,dm-pre-reloc; };