120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021, Artinchip Technology Co., Ltd
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*/
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#include <dt-bindings/clock/artinchip,aic-cmu.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/types.h>
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#include "clk-aic.h"
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#ifdef CONFIG_DEBUG_ON_FPGA_BOARD_ARTINCHIP
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#define CLOCK1_FREQ 48000000
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#define CLOCK2_FREQ 100000000
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#define CLOCK3_FREQ 24576000
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#define CLOCK4_FREQ 62500000
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#define CLOCK5_FREQ 48000000
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#define CLOCK6_FREQ 60000000
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#define CLOCK_120M 120000000
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#define CLOCK_100M 100000000
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#define CLOCK_72M 72000000
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#define CLOCK_60M 60000000
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#define CLOCK_50M 50000000
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#define CLOCK_30M 30000000
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#define CLOCK_24M 24000000
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#define CLOCK_12M 12000000
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#define CLOCK_1M 1000000
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#define CLOCK_32K 32768
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const unsigned long fpga_board_rate[] = {
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[CLK_OSC24M] = CLOCK_24M,
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[CLK_OSC32K] = CLOCK_32K,
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[CLK_RC1M] = CLOCK_1M,
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[CLK_PLL_INT0] = CLOCK_24M,
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[CLK_PLL_INT1] = CLOCK_24M,
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[CLK_PLL_FRA0] = CLOCK_24M,
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[CLK_PLL_FRA1] = CLOCK_24M,
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[CLK_PLL_FRA2] = CLOCK_24M,
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[CLK_AXI0_SRC1] = CLOCK4_FREQ,
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[CLK_AHB0_SRC1] = CLOCK_60M,
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[CLK_APB0_SRC1] = CLOCK_30M,
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[CLK_APB1_SRC1] = CLOCK_24M,
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[CLK_CPU_SRC1] = CLOCK_100M,
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[CLK_AXI0] = CLOCK4_FREQ,
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[CLK_AHB0] = CLOCK_24M,
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[CLK_APB0] = CLOCK_24M,
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[CLK_APB1] = CLOCK_24M,
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[CLK_CPU] = CLOCK_100M,
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[CLK_DMA] = CLOCK_60M,
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[CLK_CE] = CLOCK_72M,
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[CLK_USBD] = CLOCK_60M,
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[CLK_USBH0] = CLOCK_60M,
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[CLK_USBH1] = CLOCK_60M,
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[CLK_USB_PHY0] = CLOCK_60M,
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[CLK_USB_PHY1] = CLOCK_60M,
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[CLK_GMAC0] = CLOCK_50M,
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[CLK_GMAC1] = CLOCK_50M,
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[CLK_SPI0] = CLOCK_24M,
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[CLK_SPI1] = CLOCK_24M,
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[CLK_SDMC0] = CLOCK1_FREQ,
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[CLK_SDMC1] = CLOCK1_FREQ,
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[CLK_SDMC2] = CLOCK1_FREQ,
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[CLK_SYSCFG] = CLOCK_24M,
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[CLK_RTC] = CLOCK_1M,
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[CLK_I2S0] = CLOCK3_FREQ,
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[CLK_I2S1] = CLOCK3_FREQ,
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[CLK_CODEC] = CLOCK3_FREQ,
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[CLK_RGB] = CLOCK_100M,
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[CLK_LVDS] = CLOCK_100M,
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[CLK_MIPIDSI] = CLOCK_100M,
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[CLK_DE] = CLOCK_72M,
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[CLK_GE] = CLOCK_72M,
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[CLK_VE] = CLOCK_72M,
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[CLK_WDOG] = CLOCK_1M,
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[CLK_SID] = CLOCK_24M,
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[CLK_GTC] = CLOCK_24M,
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[CLK_GPIO] = CLOCK_24M,
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#ifdef CONFIG_CLK_ARTINCHIP_V01
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[CLK_UART0] = CLOCK_24M,
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[CLK_UART1] = CLOCK_24M,
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[CLK_UART2] = CLOCK_24M,
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[CLK_UART3] = CLOCK_24M,
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[CLK_UART4] = CLOCK_24M,
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[CLK_UART5] = CLOCK_24M,
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[CLK_UART6] = CLOCK_24M,
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[CLK_UART7] = CLOCK_24M,
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#else
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[CLK_UART0] = CLOCK_60M,
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[CLK_UART1] = CLOCK_60M,
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[CLK_UART2] = CLOCK_60M,
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[CLK_UART3] = CLOCK_60M,
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[CLK_UART4] = CLOCK_60M,
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[CLK_UART5] = CLOCK_60M,
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[CLK_UART6] = CLOCK_60M,
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[CLK_UART7] = CLOCK_60M,
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#endif
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[CLK_TWI0] = CLOCK_24M,
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[CLK_TWI1] = CLOCK_24M,
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[CLK_TWI2] = CLOCK_24M,
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[CLK_TWI3] = CLOCK_24M,
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[CLK_CAN0] = CLOCK_24M,
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[CLK_CAN1] = CLOCK_24M,
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[CLK_PWM] = CLOCK_24M,
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[CLK_ADCIM] = CLOCK_24M,
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[CLK_GPAI] = CLOCK_24M,
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[CLK_RTP] = CLOCK_24M,
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[CLK_TSEN] = CLOCK_24M,
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[CLK_CIR] = CLOCK_24M,
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[CLK_OUT0] = CLOCK_24M,
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[CLK_OUT1] = CLOCK_24M,
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[CLK_OUT2] = CLOCK_24M,
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[CLK_OUT3] = CLOCK_24M,
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};
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#endif
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