584 lines
19 KiB
C
584 lines
19 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2022 ArtInChip Inc.
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* Authors: matteo <mintao.duan@artinchip.com>
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*/
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#ifndef _ARTINCHIP_MMC_H_
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#define _ARTINCHIP_MMC_H_
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#include <linux/scatterlist.h>
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#include <linux/mmc/core.h>
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#include <linux/dmaengine.h>
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#include <linux/reset.h>
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#include <linux/interrupt.h>
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enum artinchip_mmc_state {
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STATE_IDLE = 0,
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STATE_SENDING_CMD,
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STATE_SENDING_DATA,
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STATE_DATA_BUSY,
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STATE_SENDING_STOP,
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STATE_DATA_ERROR,
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STATE_SENDING_CMD11,
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STATE_WAITING_CMD11_DONE,
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};
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enum {
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EVENT_CMD_COMPLETE = 0,
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EVENT_XFER_COMPLETE,
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EVENT_DATA_COMPLETE,
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EVENT_DATA_ERROR,
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};
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enum artinchip_mmc_cookie {
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COOKIE_UNMAPPED,
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COOKIE_PRE_MAPPED, /* mapped by pre_req() of aicmmc */
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COOKIE_MAPPED, /* mapped by prepare_data() of aicmmc */
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};
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struct mmc_data;
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enum data_width {
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DATA_WIDTH_16BIT = 1,
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DATA_WIDTH_32BIT,
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DATA_WIDTH_64BIT
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};
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/**
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* struct artinchip_mmc - MMC controller state shared between all slots
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* @lock: Spinlock protecting the queue and associated data.
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* @irq_lock: Spinlock protecting the INTMASK setting.
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* @regs: Pointer to MMIO registers.
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* @fifo_reg: Pointer to MMIO registers for data FIFO
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* @sg: Scatterlist entry currently being processed by PIO code, if any.
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* @sg_miter: PIO mapping scatterlist iterator.
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* @mrq: The request currently being processed on @slot,
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* or NULL if the controller is idle.
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* @cmd: The command currently being sent to the card, or NULL.
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* @data: The data currently being transferred, or NULL if no data
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* transfer is in progress.
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* @stop_abort: The command currently prepared for stopping transfer.
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* @prev_blksz: The former transfer blksz record.
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* @timing: Record of current ios timing.
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* @use_dma: Which DMA channel is in use for the current transfer, zero
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* denotes PIO mode.
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* @using_dma: Whether DMA is in use for the current transfer.
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* @sg_dma: Bus address of DMA buffer.
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* @sg_cpu: Virtual address of DMA buffer.
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* @dma_ops: Pointer to platform-specific DMA callbacks.
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* @cmd_status: Snapshot of SR taken upon completion of the current
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* @ring_size: Buffer size for idma descriptors.
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* command. Only valid when EVENT_CMD_COMPLETE is pending.
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* @phy_regs: physical address of controller's register map
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* @data_status: Snapshot of SR taken upon completion of the current
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* data transfer. Only valid when EVENT_DATA_COMPLETE or
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* EVENT_DATA_ERROR is pending.
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* @stop_cmdr: Value to be loaded into CMDR when the stop command is
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* to be sent.
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* @dir_status: Direction of current transfer.
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* @tasklet: Tasklet running the request state machine.
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* @pending_events: Bitmask of events flagged by the interrupt handler
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* to be processed by the tasklet.
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* @completed_events: Bitmask of events which the state machine has
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* processed.
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* @state: Tasklet state.
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* @queue: List of slots waiting for access to the controller.
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* @sclk_rate: The rate of SDMC clk in Hz. It's the basis clk for SDMC.
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* @current_speed: Configured rate of the controller.
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* @fifoth_val: The value of FIFOTH register.
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* @verid: Denote Version ID.
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* @dev: Device associated with the MMC controller.
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* @pdata: Platform data associated with the MMC controller.
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* @drv_data: Driver specific data for identified variant of the controller
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* @priv: Implementation defined private data.
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* @hif_clk: Pointer to the interface of SDMC host.
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* @slot: Slots sharing this MMC controller.
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* @fifo_depth: depth of FIFO.
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* @data_addr_override: override fifo reg offset with this value.
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* @wm_aligned: force fifo watermark equal with data length in PIO mode.
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* Set as true if alignment is needed.
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* @data_shift: log2 of FIFO item size.
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* @part_buf_start: Start index in part_buf.
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* @part_buf_count: Bytes of partial data in part_buf.
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* @part_buf: Simple buffer for partial fifo reads/writes.
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* @push_data: Pointer to FIFO push function.
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* @pull_data: Pointer to FIFO pull function.
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* @vqmmc_enabled: Status of vqmmc, should be true or false.
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* @irq_flags: The flags to be passed to request_irq.
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* @irq: The irq value to be passed to request_irq.
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* @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
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* @cto_timer: Timer for broken command transfer over scheme.
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* @dto_timer: Timer for broken data transfer over scheme.
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*
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* Locking
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* =======
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*
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* @lock is a softirq-safe spinlock protecting @queue as well as
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* @slot, @mrq and @state. These must always be updated
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* at the same time while holding @lock.
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* The @mrq field of struct artinchip_mmc_slot is also protected by @lock,
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* and must always be written at the same time as the slot is added to
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* @queue.
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*
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* @irq_lock is an irq-safe spinlock protecting the INTMASK register
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* to allow the interrupt handler to modify it directly. Held for only long
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* enough to read-modify-write INTMASK and no other locks are grabbed when
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* holding this one.
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*
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* @pending_events and @completed_events are accessed using atomic bit
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* operations, so they don't need any locking.
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*
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* None of the fields touched by the interrupt handler need any
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* locking. However, ordering is important: Before EVENT_DATA_ERROR or
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* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
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* interrupts must be disabled and @data_status updated with a
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* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
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* CMDRDY interrupt must be disabled and @cmd_status updated with a
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* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
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* bytes_xfered field of @data must be written. This is ensured by
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* using barriers.
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*/
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struct artinchip_mmc {
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spinlock_t lock;
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spinlock_t irq_lock;
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struct attribute_group attrs;
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void __iomem *regs;
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void __iomem *fifo_reg;
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bool wm_aligned;
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struct scatterlist *sg;
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struct sg_mapping_iter sg_miter;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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struct mmc_command stop_abort;
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unsigned int prev_blksz;
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unsigned char timing;
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/* DMA interface members*/
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bool use_dma;
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bool using_dma;
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dma_addr_t sg_dma;
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void *sg_cpu;
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const struct artinchip_mmc_dma_ops *dma_ops;
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/* For idmac */
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unsigned int ring_size;
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/* Registers's physical base address */
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resource_size_t phy_regs;
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u32 cmd_status;
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u32 data_status;
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u32 stop_cmdr;
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u32 dir_status;
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struct tasklet_struct tasklet;
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unsigned long pending_events;
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unsigned long completed_events;
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enum artinchip_mmc_state state;
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struct list_head queue;
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u32 sclk_rate;
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u32 current_speed;
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u32 fifoth_val;
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u16 verid;
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struct device *dev;
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struct artinchip_mmc_board *pdata;
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const struct artinchip_mmc_drv_data *drv_data;
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void *priv;
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struct clk *hif_clk;
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struct reset_control *reset;
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struct artinchip_mmc_slot *slot;
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/* FIFO push and pull */
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int fifo_depth;
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int data_shift;
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u8 part_buf_start;
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u8 part_buf_count;
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enum data_width data_width;
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union {
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u16 part_buf16;
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u32 part_buf32;
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u64 part_buf;
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};
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bool vqmmc_enabled;
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unsigned long irq_flags; /* IRQ flags */
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int irq;
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struct timer_list cmd11_timer;
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struct timer_list cto_timer;
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struct timer_list dto_timer;
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u32 sample_phase;
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u32 sample_delay;
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u32 driver_phase;
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u32 driver_delay;
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u32 power_gpio;
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};
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/* DMA ops for Internal/External DMAC interface */
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struct artinchip_mmc_dma_ops {
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/* DMA Ops */
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int (*init)(struct artinchip_mmc *host);
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int (*start)(struct artinchip_mmc *host, unsigned int sg_len);
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void (*complete)(void *host);
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void (*stop)(struct artinchip_mmc *host);
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void (*cleanup)(struct artinchip_mmc *host);
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void (*exit)(struct artinchip_mmc *host);
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};
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struct dma_pdata;
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/* Board platform data */
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struct artinchip_mmc_board {
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u32 sclk_rate; /* SDMC clk rate */
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u32 caps; /* Capabilities */
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u32 caps2; /* More capabilities */
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u32 pm_caps; /* PM capabilities */
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/*
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* Override fifo depth. If 0, autodetect it from the FIFOTH register,
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* but note that this may not be reliable after a bootloader has used
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* it.
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*/
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unsigned int fifo_depth;
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/* delay in mS before detecting cards after interrupt */
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u32 detect_delay_ms;
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struct artinchip_mmc_dma_ops *dma_ops;
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struct dma_pdata *data;
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};
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#define ARTINCHIP_MMC_FREQ_MAX 200000000 /* unit: HZ */
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#define ARTINCHIP_MMC_FREQ_MIN 100000 /* unit: HZ */
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#define ARTINCHIP_MMC_SEND_STATUS 1
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#define ARTINCHIP_MMC_RECV_STATUS 2
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#define ARTINCHIP_MMC_DMA_THRESHOLD 16
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/* SDMC controller register */
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#define SDMC_BLKCNT 0x000
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#define SDMC_BLKSIZ 0x004
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#define SDMC_CMDARG 0x008
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#define SDMC_CMD 0x00c
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#define SDMC_RESP0 0x010
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#define SDMC_RESP1 0x014
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#define SDMC_RESP2 0x018
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#define SDMC_RESP3 0x01c
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#define SDMC_TTMC 0x020
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#define SDMC_TCBC 0x024
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#define SDMC_TFBC 0x028
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#define SDMC_CTRST 0x02c
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#define SDMC_HCTRL1 0x030
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#define SDMC_CLKCTRL 0x034
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#define SDMC_HCTRL2 0x038
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#define SDMC_INTEN 0x03c
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#define SDMC_INTST 0x040
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#define SDMC_OINTST 0x044
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#define SDMC_FIFOCFG 0x048
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#define SDMC_HINFO 0x050
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#define SDMC_CDET 0x054
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#define SDMC_PBUSCFG 0x080
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#define SDMC_IDMARCAP 0x084
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#define SDMC_IDMASADDR 0x088
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#define SDMC_IDMAST 0x08c
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#define SDMC_IDMAINTEN 0x090
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#define SDMC_IDMACDA 0x094
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#define SDMC_IDMACBA 0x098
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#define SDMC_CTC 0x100
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#define SDMC_DLYCTRL 0x104
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#define SDMC_EMCR 0x108
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#define SDMC_VERID 0x118
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#define SDMC_FIFO_DATA 0x200
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/* Command configure register defines */
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#define SDMC_CMD_START BIT(31)
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#define SDMC_CMD_USE_HOLD_REG BIT(29)
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#define SDMC_CMD_VOLT_SWITCH BIT(28)
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#define SDMC_CMD_UPD_CLK BIT(21)
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#define SDMC_CMD_CARDNUMB_MASK GENMASK(20, 16)
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#define SDMC_CMD_INIT BIT(15)
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#define SDMC_CMD_STOP BIT(14)
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#define SDMC_CMD_PRV_DAT_WAIT BIT(13)
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#define SDMC_CMD_SEND_STOP BIT(12)
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#define SDMC_CMD_TRANSFER_MODE BIT(11)
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#define SDMC_CMD_DAT_WR BIT(10)
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#define SDMC_CMD_DAT_EXP BIT(9)
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#define SDMC_CMD_RESP_CRC BIT(8)
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#define SDMC_CMD_RESP_LEN BIT(7)
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#define SDMC_CMD_RESP_EXP BIT(6)
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#define SDMC_CMD_INDX(n) ((n) & 0x1F)
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/* Transfer timeout control register defines */
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#define SDMC_TTMC_DATA_SHIFT 8
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#define SDMC_TTMC_DATA_MASK GENMASK(31, 8)
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#define SDMC_TTMC_DATA(n) ((n) << SDMC_TTMC_DATA_SHIFT)
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#define SDMC_TTMC_RESP_MASK GENMASK(7, 0)
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#define SDMC_TTMC_RESP(n) ((n) & SDMC_TTMC_RESP_MASK)
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/* Controller status register defines */
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#define SDMC_CTRST_DMA_REQ BIT(31)
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#define SDMC_CTRST_FCNT(x) (((x) >> 17) & 0x1FFF)
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#define SDMC_CTRST_BUSY BIT(9)
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/* Host control 1 register defines */
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#define SDMC_HCTRL1_USE_IDMAC BIT(25)
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#define SDMC_HCTRL1_ABRT_READ_DATA BIT(8)
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#define SDMC_HCTRL1_SEND_IRQ_RESP BIT(7)
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#define SDMC_HCTRL1_READ_WAIT BIT(6)
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#define SDMC_HCTRL1_DMA_EN BIT(5)
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#define SDMC_HCTRL1_INT_EN BIT(4)
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#define SDMC_HCTRL1_CARD_RESET BIT(3)
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#define SDMC_HCTRL1_DMA_RESET BIT(2)
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#define SDMC_HCTRL1_FIFO_RESET BIT(1)
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#define SDMC_HCTRL1_RESET BIT(0)
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#define SDMC_HCTRL1_RESET_ALL \
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(SDMC_HCTRL1_RESET | SDMC_HCTRL1_FIFO_RESET | SDMC_HCTRL1_DMA_RESET)
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/* Clock control register defines */
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#define SDMC_CLKCTRL_LOW_PWR BIT(16)
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#define SDMC_CLKCTRL_DIV_SHIFT 8
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#define SDMC_CLKCTRL_DIV_MASK GENMASK(15, 8)
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#define SDMC_CLKCTRL_DIV_MAX \
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(SDMC_CLKCTRL_DIV_MASK >> SDMC_CLKCTRL_DIV_SHIFT)
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#define SDMC_GET_CLK_DIV(x) \
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((((x) & SDMC_CLKCTRL_DIV_MASK) >> SDMC_CLKCTRL_DIV_SHIFT) * 2)
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#define SDMC_CLKCTRL_EN BIT(0)
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/* Host control 2 register defines */
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#define SDMC_HCTRL2_BW_8BIT BIT(29)
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#define SDMC_HCTRL2_BW_4BIT BIT(28)
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#define SDMC_HCTRL2_BW_1BIT 0
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#define SDMC_HCTRL2_DDR_MODE BIT(16)
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#define SDMC_HCTRL2_VOLT_18V BIT(0)
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/* Interrupt status & enable register defines */
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#define SDMC_INT_SDIO BIT(16)
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#define SDMC_INT_EBE BIT(15)
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#define SDMC_INT_AUTO_CMD_DONE BIT(14)
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#define SDMC_INT_SBE BIT(13)
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#define SDMC_INT_HLE BIT(12)
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#define SDMC_INT_FRUN BIT(11)
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#define SDMC_INT_HTO BIT(10)
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#define SDMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
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#define SDMC_INT_DRTO BIT(9)
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#define SDMC_INT_RTO BIT(8)
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#define SDMC_INT_DCRC BIT(7)
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#define SDMC_INT_RCRC BIT(6)
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#define SDMC_INT_RXDR BIT(5)
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#define SDMC_INT_TXDR BIT(4)
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#define SDMC_INT_DAT_DONE BIT(3)
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#define SDMC_INT_CMD_DONE BIT(2)
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#define SDMC_INT_RESP_ERR BIT(1)
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#define SDMC_INT_CD BIT(0)
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#define SDMC_INT_ERROR \
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(SDMC_INT_EBE | SDMC_INT_SBE | SDMC_INT_HLE | \
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SDMC_INT_FRUN | SDMC_INT_HTO | SDMC_INT_DRTO | SDMC_INT_RTO \
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SDMC_INT_DCRC | SDMC_INT_RCRC | SDMC_INT_RESP_ERR)
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#define SDMC_DAT_ERROR_FLAGS (SDMC_INT_EBE | SDMC_INT_SBE | SDMC_INT_HLE | \
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SDMC_INT_HTO | SDMC_INT_DRTO | SDMC_INT_DCRC)
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#define SDMC_CMD_ERROR_FLAGS (SDMC_INT_RTO | SDMC_INT_RCRC | \
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SDMC_INT_RESP_ERR | SDMC_INT_HLE)
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#define SDMC_ERROR_FLAGS (SDMC_DAT_ERROR_FLAGS | SDMC_CMD_ERROR_FLAGS)
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/* FIFO configuration register defines */
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#define SDMC_FIFOCFG_SET_THD(m, r, t) \
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(((m) & 0x7) << 28 | ((r) & 0xFFF) << 16 | ((t) & 0xFFF))
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/* Hardware information register defines */
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#define SDMC_HINFO_IF_IDMA (0x0)
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#define SDMC_HINFO_IF_AICDMA (0x1)
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#define SDMC_HINFO_IF_GDMA (0x2)
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#define SDMC_HINFO_IF_NODMA (0x3)
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#define SDMC_HINFO_TRANS_MODE(x) (((x) >> 16) & 0x3)
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#define SDMC_HINFO_HDATA_WIDTH(x) (((x) >> 7) & 0x7)
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#define SDMC_HINFO_ADDR_CONFIG(x) (((x) >> 27) & 0x1)
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/* Card Detect Configuration register defines */
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#define SDMC_CDET_ABSENT BIT(24)
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/* Peripheral bus configuration register defines */
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#define SDMC_PBUSCFG_IDMAC_EN BIT(7)
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#define SDMC_PBUSCFG_IDMAC_FB BIT(1)
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#define SDMC_PBUSCFG_IDMAC_SWR BIT(0)
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/* Internal DMAC interrupt defines */
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#define SDMC_IDMAC_INT_AIS BIT(9)
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#define SDMC_IDMAC_INT_NIS BIT(8)
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#define SDMC_IDMAC_INT_CES BIT(5)
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#define SDMC_IDMAC_INT_DU BIT(4)
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#define SDMC_IDMAC_INT_FBE BIT(2)
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#define SDMC_IDMAC_INT_RI BIT(1)
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#define SDMC_IDMAC_INT_TI BIT(0)
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#define SDMC_IDMAC_INT_MASK (SDMC_IDMAC_INT_AIS | SDMC_IDMAC_INT_NIS | \
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SDMC_IDMAC_INT_CES | SDMC_IDMAC_INT_DU | \
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SDMC_IDMAC_INT_FBE | SDMC_IDMAC_INT_RI | \
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SDMC_IDMAC_INT_TI)
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/* Card threshold control register defines */
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#define SDMC_CTC_THD_SHIFT 16
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#define SDMC_CTC_THD_MASK GENMASK(27, 16)
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#define SDMC_CTC_SET_THD(v, x) \
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(((v) & SDMC_CTC_THD_MASK) << SDMC_CTC_THD_SHIFT | (x))
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#define SDMC_CTC_WR_THD_EN BIT(2)
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#define SDMC_CTC_RD_THD_EN BIT(0)
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/* DDR register defines */
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#define SDMC_DDR_HS400_ENABLE BIT(31)
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/* Enable shift register defines */
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#define SDMC_ENABLE_PHASE BIT(0)
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#define SDMC_DLYCTRL_EXT_CLK_MUX_SHIFT 30
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#define SDMC_DLYCTRL_EXT_CLK_MUX_MASK GENMASK(31, 30)
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#define SDMC_DLYCTRL_EXT_CLK_MUX_1 2
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#define SDMC_DLYCTRL_EXT_CLK_MUX_2 1
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#define SDMC_DLYCTRL_EXT_CLK_MUX_4 0
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#define SDMC_DLYCTRL_CLK_DRV_PHA_MASK GENMASK(29, 28)
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#define SDMC_DLYCTRL_CLK_DRV_PHA_SHIFT 28
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#define SDMC_DLYCTRL_CLK_DRV_PHA_0 0
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#define SDMC_DLYCTRL_CLK_DRV_PHA_90 1
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#define SDMC_DLYCTRL_CLK_DRV_PHA_180 2
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#define SDMC_DLYCTRL_CLK_DRV_PHA_270 3
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#define SDMC_DLYCTRL_CLK_DRV_DLY_MASK GENMASK(27, 23)
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#define SDMC_DLYCTRL_CLK_DRV_DLY_SHIFT 23
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#define SDMC_DLYCTRL_CLK_SMP_PHA_MASK GENMASK(22, 21)
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#define SDMC_DLYCTRL_CLK_SMP_PHA_SHIFT 21
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#define SDMC_DLYCTRL_CLK_SMP_PHA_0 0
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#define SDMC_DLYCTRL_CLK_SMP_PHA_90 1
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#define SDMC_DLYCTRL_CLK_SMP_PHA_180 2
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#define SDMC_DLYCTRL_CLK_SMP_PHA_270 3
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#define SDMC_DLYCTRL_CLK_DRV_DLY_MAX \
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(SDMC_DLYCTRL_CLK_DRV_DLY_MASK >> SDMC_DLYCTRL_CLK_DRV_DLY_SHIFT)
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#define SDMC_DLYCTRL_CLK_SMP_DLY_MASK GENMASK(20, 16)
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#define SDMC_DLYCTRL_CLK_SMP_DLY_SHIFT 16
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#define SDMC_DLYCTRL_CLK_SMP_DLY_MAX \
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(SDMC_DLYCTRL_CLK_SMP_DLY_MASK >> SDMC_DLYCTRL_CLK_SMP_DLY_SHIFT)
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/* CLKSEL register defines */
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#define SDMMC_DLYCTRL_CCLK_DRIVER(x) (((x) & 3) << SDMC_DLYCTRL_CLK_DRV_PHA_SHIFT)
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#define SDMMC_DLYCTRL_CCLK_UP_DRIVER(x, y) (((x) & ~SDMMC_DLYCTRL_CCLK_DRIVER(3)) |\
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SDMMC_DLYCTRL_CCLK_DRIVER(y))
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/* Version ID register define */
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#define SDMC_VERID_GET(x) ((x) & 0xFFFF)
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/* FIFO register access macros. These should not change the data endian-ness
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* as they are written to memory to be dealt with by the upper layers
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*/
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#define mci_fifo_readw(__reg) __raw_readw(__reg)
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#define mci_fifo_readl(__reg) __raw_readl(__reg)
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#define mci_fifo_readq(__reg) __raw_readq(__reg)
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#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
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#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
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#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
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|
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/* Register access macros */
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#define mci_readl(dev, reg) \
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readl_relaxed((dev)->regs + reg)
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#define mci_writel(dev, reg, value) \
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writel_relaxed((value), (dev)->regs + reg)
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|
|
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/* 16-bit FIFO access macros */
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|
#define mci_readw(dev, reg) \
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|
readw_relaxed((dev)->regs + reg)
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#define mci_writew(dev, reg, value) \
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|
writew_relaxed((value), (dev)->regs + reg)
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|
|
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/* 64-bit FIFO access macros */
|
|
#ifdef readq
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|
#define mci_readq(dev, reg) \
|
|
readq_relaxed((dev)->regs + reg)
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|
#define mci_writeq(dev, reg, value) \
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|
writeq_relaxed((value), (dev)->regs + reg)
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|
#else
|
|
/*
|
|
* Dummy readq implementation for architectures that don't define it.
|
|
*
|
|
* We would assume that none of these architectures would configure
|
|
* the IP block with a 64bit FIFO width, so this code will never be
|
|
* executed on those machines. Defining these macros here keeps the
|
|
* rest of the code free from ifdefs.
|
|
*/
|
|
#define mci_readq(dev, reg) \
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|
(*(volatile u64 __force *)((dev)->regs + reg))
|
|
#define mci_writeq(dev, reg, value) \
|
|
(*(volatile u64 __force *)((dev)->regs + reg) = (value))
|
|
|
|
#define __raw_writeq(__value, __reg) \
|
|
(*(volatile u64 __force *)(__reg) = (__value))
|
|
#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
|
|
#endif
|
|
|
|
extern int artinchip_mmc_probe(struct artinchip_mmc *host);
|
|
extern void artinchip_mmc_remove(struct artinchip_mmc *host);
|
|
#ifdef CONFIG_PM
|
|
extern int artinchip_mmc_runtime_suspend(struct device *device);
|
|
extern int artinchip_mmc_runtime_resume(struct device *device);
|
|
#endif
|
|
|
|
/**
|
|
* struct artinchip_mmc_slot - MMC slot state
|
|
* @mmc: The mmc_host representing this slot.
|
|
* @host: The MMC controller this slot is using.
|
|
* @ctype: Card type for this slot.
|
|
* @mrq: mmc_request currently being processed or waiting to be
|
|
* processed, or NULL when the slot is idle.
|
|
* @queue_node: List node for placing this node in the @queue list of
|
|
* &struct artinchip_mmc.
|
|
* @clock: Clock rate configured by set_ios(). Protected by host->lock.
|
|
* @__clk_old: The last clock value that was requested from core.
|
|
* Keeping track of this helps us to avoid spamming the console.
|
|
* @flags: Random state bits associated with the slot.
|
|
* @id: Number of this slot.
|
|
*/
|
|
struct artinchip_mmc_slot {
|
|
struct mmc_host *mmc;
|
|
struct artinchip_mmc *host;
|
|
|
|
u32 ctype;
|
|
|
|
struct mmc_request *mrq;
|
|
struct list_head queue_node;
|
|
|
|
unsigned int clock;
|
|
unsigned int __clk_old;
|
|
|
|
unsigned long flags;
|
|
#define ARTINCHIP_MMC_CARD_PRESENT 0
|
|
#define ARTINCHIP_MMC_CARD_NEED_INIT 1
|
|
#define ARTINCHIP_MMC_CARD_NO_LOW_PWR 2
|
|
#define ARTINCHIP_MMC_CARD_NO_USE_HOLD 3
|
|
#define ARTINCHIP_MMC_CARD_NEEDS_POLL 4
|
|
};
|
|
|
|
/**
|
|
* artinchip_mmc driver data - aic-shmc implementation specific driver data.
|
|
* @caps: mmc subsystem specified capabilities of the controller(s).
|
|
* @num_caps: number of capabilities specified by @caps.
|
|
* @init: early implementation specific initialization.
|
|
* @set_ios: handle bus specific extensions.
|
|
* @parse_dt: parse implementation specific device tree properties.
|
|
* @execute_tuning: implementation specific tuning procedure.
|
|
*
|
|
* Provide controller implementation specific extensions. The usage of this
|
|
* data structure is fully optional and usage of each member in this structure
|
|
* is optional as well.
|
|
*/
|
|
struct artinchip_mmc_drv_data {
|
|
unsigned long *caps;
|
|
u32 num_caps;
|
|
int (*init)(struct artinchip_mmc *host);
|
|
int (*parse_dt)(struct artinchip_mmc *host);
|
|
int (*execute_tuning)(struct artinchip_mmc_slot *slot, u32 opcode);
|
|
int (*prepare_hs400_tuning)(struct artinchip_mmc *host,
|
|
struct mmc_ios *ios);
|
|
int (*switch_voltage)(struct mmc_host *mmc,
|
|
struct mmc_ios *ios);
|
|
};
|
|
#endif /* _ARTINCHIP_MMC_H_ */
|