183 lines
5.6 KiB
C
183 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021, Artinchip Technology Co., Ltd
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* Author: Dehuang Wu <dehuang.wu@artinchip.com>
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*/
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#include <linux/regulator/consumer.h>
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#include <linux/bits.h>
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#ifndef _AIC_SPI_H_
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#define _AIC_SPI_H_
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#define SPI_FIFO_DEPTH 64
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#define SPI_MAX_FREQUENCY 133000000
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#define AIC_SPI_MAX_XFER_SIZE 0xffffff
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/* SPI Registers offset */
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#define SPI_REG_VER (0x00)
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#define SPI_REG_GCR (0x04)
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#define SPI_REG_TCR (0x08)
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#define SPI_REG_ICR (0x10)
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#define SPI_REG_ISR (0x14)
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#define SPI_REG_FCR (0x18)
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#define SPI_REG_FSR (0x1C)
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#define SPI_REG_WCR (0x20)
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#define SPI_REG_CCR (0x24)
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#define SPI_REG_BCR (0x30)
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#define SPI_REG_MTC (0x34)
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#define SPI_REG_BCC (0x38)
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#define SPI_REG_BTC (0x40)
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#define SPI_REG_BCLK (0x44)
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#define SPI_REG_TBR (0x48)
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#define SPI_REG_RBR (0x4C)
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#define SPI_REG_DCR (0x88)
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#define SPI_REG_TXDATA (0x200)
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#define SPI_REG_RXDATA (0x300)
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/* SPI Global Control Register Bit Fields & Masks */
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#define GCR_BIT_EN BIT(0)
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#define GCR_BIT_MODE BIT(1)
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#define GCR_BIT_PAUSE BIT(7)
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#define GCR_BIT_SRST BIT(31)
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/* SPI Transfer Control Register Bit Fields & Masks */
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#define TCR_BIT_CPHA BIT(0)
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#define TCR_BIT_CPOL BIT(1)
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#define TCR_BIT_SPOL BIT(2)
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#define TCR_BIT_SSCTL BIT(3)
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#define TCR_BIT_SS_OWNER BIT(6)
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#define TCR_BIT_SS_LEVEL BIT(7)
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#define TCR_BIT_DHB BIT(8)
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#define TCR_BIT_DDB BIT(9)
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#define TCR_BIT_RPSM BIT(10)
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#define TCR_BIT_RXINDLY_EN BIT(11)
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#define TCR_BIT_FBS BIT(12)
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#define TCR_BIT_RXDLY_DIS BIT(13)
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#define TCR_BIT_SDDM BIT(14)
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#define TCR_BIT_3WIRE BIT(25)
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#define TCR_BIT_XCH BIT(31)
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#define TCR_BIT_SS_SEL_OFF (4)
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#define TCR_BIT_SS_SEL_MSK GENMASK(5, 4)
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#define TCR_RX_SAMPDLY_MSK (TCR_BIT_RXINDLY_EN | TCR_BIT_RXDLY_DIS)
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#define TCR_RX_SAMPDLY_NONE (TCR_BIT_RXDLY_DIS)
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#define TCR_RX_SAMPDLY_HALF (0)
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#define TCR_RX_SAMPDLY_ONE (TCR_BIT_RXINDLY_EN)
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/* SPI Interrupt Control Register Bit Fields & Masks */
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#define ICR_BIT_RX_RDY BIT(0)
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#define ICR_BIT_RX_EMP BIT(1)
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#define ICR_BIT_RX_FULL BIT(2)
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#define ICR_BIT_TX_ERQ BIT(4)
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#define ICR_BIT_TX_EMP BIT(5)
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#define ICR_BIT_TX_FULL BIT(6)
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#define ICR_BIT_RX_OVF BIT(8)
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#define ICR_BIT_RX_UDR BIT(9)
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#define ICR_BIT_TX_OVF BIT(10)
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#define ICR_BIT_TX_UDR BIT(11)
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#define ICR_BIT_TC BIT(12)
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#define ICR_BIT_SSI BIT(13)
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#define ICR_BIT_ERRS (ICR_BIT_TX_OVF | ICR_BIT_RX_UDR | \
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ICR_BIT_RX_OVF)
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#define ICR_BIT_ALL_MSK (0x77 | (0x3f << 8))
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/* SPI Interrupt Status Register Bit Fields & Masks */
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#define ISR_BIT_RX_RDY BIT(0)
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#define ISR_BIT_RX_EMP BIT(1)
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#define ISR_BIT_RX_FULL BIT(2)
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#define ISR_BIT_TX_RDY BIT(4)
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#define ISR_BIT_TX_EMP BIT(5)
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#define ISR_BIT_TX_FULL BIT(6)
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#define ISR_BIT_RX_OVF BIT(8)
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#define ISR_BIT_RX_UDR BIT(9)
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#define ISR_BIT_TX_OVF BIT(10)
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#define ISR_BIT_TX_UDR BIT(11)
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#define ISR_BIT_TC BIT(12)
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#define ISR_BIT_SSI BIT(13)
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#define ISR_BIT_ERRS (ISR_BIT_TX_OVF | ISR_BIT_RX_UDR | \
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ISR_BIT_RX_OVF)
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#define ISR_BIT_ALL_MSK (0x77 | (0x3f << 8))
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/* SPI FIFO Control Register Bit Fields & Masks */
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#define FCR_BIT_RX_LEVEL_MSK GENMASK(7, 0)
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#define FCR_BIT_RX_DMA_EN BIT(8)
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#define FCR_BIT_RX_RST BIT(15)
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#define FCR_BIT_TX_LEVEL_MSK GENMASK(23, 16)
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#define FCR_BIT_TX_DMA_EN BIT(24)
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#define FCR_BIT_TX_RST BIT(31)
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#define FCR_BIT_DMA_EN_MSK (FCR_BIT_TX_DMA_EN | FCR_BIT_RX_DMA_EN)
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/* SPI FIFO Status Register Bit Fields & Masks */
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#define FSR_BIT_RX_CNT_MSK GENMASK(7, 0)
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#define FSR_BIT_RB_CNT_MSK GENMASK(14, 12)
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#define FSR_BIT_RB_WR_EN BIT(15)
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#define FSR_BIT_TX_CNT_MSK GENMASK(23, 16)
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#define FSR_BIT_TB_CNT_MSK GENMASK(30, 28)
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#define FSR_BIT_TB_WR_EN BIT(31)
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#define FSR_BIT_RXCNT_OFF (0)
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#define FSR_BIT_TXCNT_OFF (16)
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/* SPI Wait Clock Register Bit Fields & Masks */
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#define WCR_BIT_WCC_MSK GENMASK(15, 0)
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#define WCR_BIT_SWC_MSK GENMASK(19, 16)
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/* SPI Clock Control Register Bit Fields & Masks */
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#define CCR_BIT_CDR2_OFF (0)
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#define CCR_BIT_CDR1_OFF (8)
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#define CCR_BIT_CDR2_MSK GENMASK(7, 0)
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#define CCR_BIT_CDR1_MSK GENMASK(11, 8)
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#define CCR_BIT_DRS BIT(12)
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#define CCR_BIT_MSK GENMASK(12, 0)
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/* SPI Master Burst Counter Register Bit Fields & Masks */
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#define BCR_BIT_CNT_MSK GENMASK(23, 0)
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/* SPI Master Transmit Counter reigster */
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#define MTC_BIT_CNT_MSK GENMASK(23, 0)
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/* SPI Master Burst Control Counter reigster Bit Fields & Masks */
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#define BCC_BIT_STC_MSK GENMASK(23, 0)
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#define BCC_BIT_DBC_MSK GENMASK(27, 24)
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#define BCC_BIT_DUAL_MODE BIT(28)
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#define BCC_BIT_QUAD_MODE BIT(29)
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#define BTC_BIT_WM_OFS (0)
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#define BTC_BIT_WM_MSK GENMASK(1, 0)
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#define BTC_BIT_WM_BYTE (0x0)
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#define BTC_BIT_WM_BIT_3WIRE (0x2)
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#define BTC_BIT_WM_BIT_STD (0x3)
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#define BTC_BIT_SS_SEL_OFS (2)
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#define BTC_BIT_SS_SEL_MSK GENMASK(3, 2)
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#define BTC_BIT_SPOL_OFS (5)
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#define BTC_BIT_SPOL_MSK BIT(5)
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#define BTC_BIT_SS_OWNER_OFS (6)
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#define BTC_BIT_SS_OWNER_MSK BIT(6)
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#define BTC_BIT_SS_LEVEL_OFS (7)
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#define BTC_BIT_SS_LEVEL_MSK BIT(7)
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#define BTC_BIT_TX_BIT_LEN_OFS (8)
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#define BTC_BIT_TX_BIT_LEN_MSK GENMASK(13, 8)
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#define BTC_BIT_RX_BIT_LEN_OFS (16)
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#define BTC_BIT_RX_BIT_LEN_MSK GENMASK(21, 16)
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#define BTC_BIT_XFER_COMP_OFS (25)
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#define BTC_BIT_XFER_COMP_MSK BIT(25)
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#define BTC_BIT_SAMP_MODE_OFS (30)
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#define BTC_BIT_SAMP_MODE_MSK BIT(30)
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#define BTC_BIT_XFER_EN_OFS (31)
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#define BTC_BIT_XFER_EN_MSK BIT(31)
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#define DCR_BIT_DMA_CYCLE_MSK GENMASK(4, 0)
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/* spi_device mode options, only can be used in AIC controller */
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#define SPI_DUMMY_FILL_ONE BIT(30)
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#define SPI_RECEIVE_ALL_BURST BIT(31)
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#define AIC_SPI_DEV_NAME "spi"
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#define AIC_SPI_BUS_MASK(bus) BIT(bus)
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#define AIC_SPI_DMA_RX(ch) (DMASRC_SPI0_RX + ch)
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#define AIC_SPI_DMA_TX(ch) (DMADST_SPI0_TX + ch)
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#define SUPPORT_SPI_3WIRE_IN_BIT_MODE
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#endif
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