500 lines
15 KiB
C
500 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021, Artinchip Technology Co., Ltd
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*/
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#ifndef __AIC_UDC_H__
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#define __AIC_UDC_H__
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/* --------- AIC usb request ------------ */
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struct aic_usb_req {
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struct usb_request req;
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struct list_head queue;
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void *saved_req_buf;
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};
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/* --------- AIC usb endpoint ------------ */
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struct aic_usb_ep {
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struct usb_ep ep;
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struct aic_usb_gadget *parent;
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struct list_head queue;
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struct aic_usb_req *req;
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struct dentry *debugfs;
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unsigned char dir_in;
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unsigned char index;
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unsigned char mc;
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u16 interval;
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unsigned short fifo_size;
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unsigned short fifo_index;
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unsigned long total_data;
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unsigned int size_loaded;
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unsigned int last_load;
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unsigned int halted:1;
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unsigned int periodic:1;
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unsigned int isochronous:1;
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unsigned int send_zlp:1;
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unsigned int target_frame;
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#define TARGET_FRAME_INITIAL 0xFFFFFFFF
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bool frame_overrun;
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char name[10];
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};
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/* --------- Global Define ------------ */
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/* Size of control and EP0 buffers */
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#define CTRL_BUFF_SIZE 8
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#define EP0_MPS_LIMIT 64
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#define IRQ_RETRY_MASK (USBINTSTS_NPTXFEMP | \
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USBINTSTS_RXFLVL)
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#define DIS_EP_TIMOUT 100
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#define aic_gadget_driver_cb(_hs, _entry) \
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do { \
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if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
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(_hs)->driver && (_hs)->driver->_entry) { \
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spin_unlock(&_hs->lock); \
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(_hs)->driver->_entry(&(_hs)->gadget); \
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spin_lock(&_hs->lock); \
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} \
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} while (0)
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/* Gadget ep0 states */
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enum aic_ep0_state {
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AIC_EP0_SETUP,
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AIC_EP0_DATA_IN,
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AIC_EP0_DATA_OUT,
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AIC_EP0_STATUS_IN,
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AIC_EP0_STATUS_OUT,
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};
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/* --------- AIC UDC Parameters ------------ */
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#define MAX_EPS_NUM 16
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#define EPS_NUM 5
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#define PERIOD_IN_EP_NUM 2
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#define TOTAL_FIFO_SIZE 0x3f6
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#if 1
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/* configure 1 */
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#define RX_FIFO_SIZE 0x119
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#define NP_TX_FIFO_SIZE 0x100
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#define PERIOD_TX_FIFO1_SIZE 0x100
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#define PERIOD_TX_FIFO2_SIZE 0xDD
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#else
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/* configure 2 */
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#define RX_FIFO_SIZE 0x119
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#define NP_TX_FIFO_SIZE 0x200
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#define PERIOD_TX_FIFO1_SIZE 0x6E
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#define PERIOD_TX_FIFO2_SIZE 0x6E
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/* configure 0 */
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#define RX_FIFO_SIZE 0x17c
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#define NP_TX_FIFO_SIZE 0x258
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#define PERIOD_TX_FIFO1_SIZE 0x8
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#define PERIOD_TX_FIFO2_SIZE 0x8
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#endif
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#define EP_DIRS 0x0
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/* phy type */
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#define AIC_PHY_TYPE_PARAM_FS 0
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#define AIC_PHY_TYPE_PARAM_UTMI 1
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#define AIC_PHY_TYPE_PARAM_ULPI 2
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/* speed */
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#define AIC_SPEED_PARAM_HIGH 0
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#define AIC_SPEED_PARAM_FULL 1
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#define AIC_SPEED_PARAM_LOW 2
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#define SYSCFG_USB_RES_CAL_EN_SHIFT 8
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#define SYSCFG_USB_RES_CAL_EN_MASK BIT(8)
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#define SYSCFG_USB_RES_CAL_VAL_SHIFT 0
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#define SYSCFG_USB_RES_CAL_VAL_MASK GENMASK(7, 0)
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#define SYSCFG_USB_RES_CAL_VAL_DEF 0x40
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struct aic_usb_res_cfg {
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void __iomem *addr;
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u32 resis;
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};
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struct aic_gadget_params {
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struct aic_usb_res_cfg usb_res_cfg;
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unsigned int num_ep;
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unsigned int num_perio_in_ep;
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unsigned int total_fifo_size;
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unsigned int rx_fifo_size;
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unsigned int np_tx_fifo_size;
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unsigned int p_tx_fifo_size[MAX_EPS_NUM];
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u32 ep_dirs;
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unsigned int speed;
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/* phy */
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unsigned int phy_type;
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unsigned int phy_ulpi_ddr;
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unsigned int phy_utmi_width;
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};
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/* --------- AIC gadget ------------ */
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#define USB_MAX_CLKS_RSTS 2
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struct aic_usb_gadget {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct device *dev;
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void __iomem *regs;
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int irq;
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struct clk *clks[USB_MAX_CLKS_RSTS];
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struct reset_control *reset;
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struct reset_control *reset_ecc;
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struct phy *phy;
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struct usb_phy *uphy;
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struct aic_gadget_params params;
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spinlock_t lock;
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struct aic_usb_ep *eps_in[MAX_EPS_NUM];
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struct aic_usb_ep *eps_out[MAX_EPS_NUM];
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/* ep0 */
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enum aic_ep0_state ep0_state;
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struct usb_request *ep0_reply;
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struct usb_request *ctrl_req;
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void *ep0_buff;
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void *ctrl_buff;
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u32 fifo_map;
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u32 tx_fifo_map;
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unsigned int enabled:1;
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unsigned int connected:1;
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unsigned int remote_wakeup_allowed:1;
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unsigned int delayed_status : 1;
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u8 test_mode;
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u16 frame_number;
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struct dentry *debug_root;
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struct debugfs_regset32 *regset;
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};
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/* --------- UDC register define ------------ */
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#define UDC_REG(x) (x)
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#define AHBBASIC UDC_REG(0x000)
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#define AHBBASIC_NOTI_ALL_DMA_WRIT BIT(8)
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#define AHBBASIC_REM_MEM_SUPP BIT(7)
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#define AHBBASIC_INV_DESC_ENDIANNESS BIT(6)
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#define AHBBASIC_AHB_SINGLE BIT(5)
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#define AHBBASIC_TXENDDELAY BIT(3)
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#define AHBBASIC_AHBIDLE BIT(2)
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#define AHBBASIC_DMAREQ BIT(1)
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#define USBDEVINIT UDC_REG(0x004)
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#define USBDEVINIT_HBSTLEN_MASK (0xf << 12)
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#define USBDEVINIT_HBSTLEN_SHIFT 12
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#define USBDEVINIT_HBSTLEN_SINGLE 0
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#define USBDEVINIT_HBSTLEN_INCR 1
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#define USBDEVINIT_HBSTLEN_INCR4 3
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#define USBDEVINIT_HBSTLEN_INCR8 5
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#define USBDEVINIT_HBSTLEN_INCR16 7
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#define USBDEVINIT_DMA_EN BIT(11)
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#define USBDEVINIT_NP_TXF_EMP_LVL BIT(10)
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#define USBDEVINIT_GLBL_INTR_EN BIT(9)
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#define USBDEVINIT_CTRL_MASK (USBDEVINIT_NP_TXF_EMP_LVL | \
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USBDEVINIT_DMA_EN | \
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USBDEVINIT_GLBL_INTR_EN)
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#define USBDEVINIT_IN_TKNQ_FLSH BIT(8)
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#define USBDEVINIT_TXFNUM_MASK (0x1f << 3)
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#define USBDEVINIT_TXFNUM_SHIFT 3
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#define USBDEVINIT_TXFNUM_LIMIT 0x1f
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#define USBDEVINIT_TXFNUM(_x) ((_x) << 3)
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#define USBDEVINIT_TXFFLSH BIT(2)
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#define USBDEVINIT_RXFFLSH BIT(1)
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#define USBDEVINIT_CSFTRST BIT(0)
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#define USBPHYIF UDC_REG(0x008)
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#define USBPHYIF_ULPI_CLK_SUSP_M BIT(19)
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#define USBPHYIF_ULPI_AUTO_RES BIT(18)
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#define USBPHYIF_PHY_LP_CLK_SEL BIT(15)
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#define USBPHYIF_USBTRDTIM_MASK (0xf << 10)
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#define USBPHYIF_USBTRDTIM_SHIFT 10
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#define USBPHYIF_DDRSEL BIT(7)
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#define USBPHYIF_ULPI_UTMI_SEL BIT(4)
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#define USBPHYIF_PHYIF16 BIT(3)
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#define USBPHYIF_PHYIF8 (0 << 3)
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#define USBPHYIF_TOUTCAL_MASK (0x7 << 0)
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#define USBPHYIF_TOUTCAL_SHIFT 0
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#define USBPHYIF_TOUTCAL_LIMIT 0x7
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#define USBPHYIF_TOUTCAL(_x) ((_x) << 0)
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#define USBULPIPHY UDC_REG(0x000C)
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#define USBINTSTS UDC_REG(0x010)
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#define USBINTMSK UDC_REG(0x014)
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#define USBINTSTS_WKUPINT BIT(31)
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#define USBINTSTS_FET_SUSP BIT(22)
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#define USBINTSTS_INCOMPL_IP BIT(21)
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#define USBINTSTS_INCOMPL_SOOUT BIT(21)
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#define USBINTSTS_INCOMPL_SOIN BIT(20)
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#define USBINTSTS_OEPINT BIT(19)
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#define USBINTSTS_IEPINT BIT(18)
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#define USBINTSTS_EPMIS BIT(17)
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#define USBINTSTS_EOPF BIT(15)
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#define USBINTSTS_ISOUTDROP BIT(14)
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#define USBINTSTS_ENUMDONE BIT(13)
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#define USBINTSTS_USBRST BIT(12)
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#define USBINTSTS_USBSUSP BIT(11)
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#define USBINTSTS_ERLYSUSP BIT(10)
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#define USBINTSTS_ULPI_CK_INT BIT(8)
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#define USBINTSTS_GOUTNAKEFF BIT(7)
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#define USBINTSTS_GINNAKEFF BIT(6)
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#define USBINTSTS_NPTXFEMP BIT(5)
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#define USBINTSTS_RXFLVL BIT(4)
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#define USBINTSTS_SOF BIT(3)
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#define RXFIFOSIZ UDC_REG(0x018)
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#define RXFIFOSIZ_DEPTH_MASK (0xffff << 0)
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#define RXFIFOSIZ_DEPTH_SHIFT 0
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#define RXFIFOSTS UDC_REG(0x01C)
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#define RXFIFOSTS_FN_MASK (0x7f << 25)
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#define RXFIFOSTS_FN_SHIFT 25
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#define RXFIFOSTS_PKTSTS_MASK (0xf << 17)
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#define RXFIFOSTS_PKTSTS_SHIFT 17
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#define RXFIFOSTS_PKTSTS_GLOBALOUTNAK 1
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#define RXFIFOSTS_PKTSTS_OUTRX 2
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#define RXFIFOSTS_PKTSTS_HCHIN 2
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#define RXFIFOSTS_PKTSTS_OUTDONE 3
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#define RXFIFOSTS_PKTSTS_HCHIN_XFER_COMP 3
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#define RXFIFOSTS_PKTSTS_SETUPDONE 4
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#define RXFIFOSTS_PKTSTS_DATATOGGLEERR 5
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#define RXFIFOSTS_PKTSTS_SETUPRX 6
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#define RXFIFOSTS_PKTSTS_HCHHALTED 7
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#define RXFIFOSTS_HCHNUM_MASK (0xf << 0)
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#define RXFIFOSTS_HCHNUM_SHIFT 0
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#define RXFIFOSTS_DPID_MASK (0x3 << 15)
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#define RXFIFOSTS_DPID_SHIFT 15
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#define RXFIFOSTS_BYTECNT_MASK (0x7ff << 4)
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#define RXFIFOSTS_BYTECNT_SHIFT 4
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#define RXFIFOSTS_EPNUM_MASK (0xf << 0)
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#define RXFIFOSTS_EPNUM_SHIFT 0
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#define NPTXFIFOSIZ UDC_REG(0x020)
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#define NPTXFIFOSTS UDC_REG(0x024)
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#define NPTXFIFOSTS_NP_TXQ_TOP_MASK (0x7f << 24)
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#define NPTXFIFOSTS_NP_TXQ_TOP_SHIFT 24
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#define NPTXFIFOSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
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#define NPTXFIFOSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
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#define NPTXFIFOSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
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#define NPTXFIFOSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
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#define NPTXFIFOSTS_NP_TXF_SPC_AVAIL_SHIFT 0
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#define NPTXFIFOSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
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#define TXFIFOSIZ(_a) UDC_REG(0x28 + (((_a) - 1) * 4))
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#define FIFOSIZE_DEPTH_MASK (0xffff << 16)
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#define FIFOSIZE_DEPTH_SHIFT 16
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#define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
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#define FIFOSIZE_STARTADDR_SHIFT 0
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#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
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#define RXFIFOSTS_DBG UDC_REG(0x030)
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/* Device mode registers */
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#define USBDEVCONF UDC_REG(0x200)
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#define USBDEVCONF_DESCDMA_EN BIT(23)
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#define USBDEVCONF_EPMISCNT_MASK (0x1f << 18)
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#define USBDEVCONF_EPMISCNT_SHIFT 18
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#define USBDEVCONF_EPMISCNT_LIMIT 0x1f
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#define USBDEVCONF_EPMISCNT(_x) ((_x) << 18)
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#define USBDEVCONF_IPG_ISOC_SUPPORDED BIT(17)
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#define USBDEVCONF_PERFRINT_MASK (0x3 << 11)
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#define USBDEVCONF_PERFRINT_SHIFT 11
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#define USBDEVCONF_PERFRINT_LIMIT 0x3
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#define USBDEVCONF_PERFRINT(_x) ((_x) << 11)
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#define USBDEVCONF_DEVADDR_MASK (0x7f << 4)
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#define USBDEVCONF_DEVADDR_SHIFT 4
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#define USBDEVCONF_DEVADDR_LIMIT 0x7f
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#define USBDEVCONF_DEVADDR(_x) ((_x) << 4)
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#define USBDEVCONF_NZ_STS_OUT_HSHK BIT(2)
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#define USBDEVCONF_DEVSPD_MASK (0x3 << 0)
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#define USBDEVCONF_DEVSPD_SHIFT 0
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#define USBDEVCONF_DEVSPD_HS 0
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#define USBDEVCONF_DEVSPD_FS 1
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#define USBDEVCONF_DEVSPD_LS 2
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#define USBDEVCONF_DEVSPD_FS48 3
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#define USBDEVFUNC UDC_REG(0x204)
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#define USBDEVFUNC_SERVICE_INTERVAL_SUPPORTED BIT(19)
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#define USBDEVFUNC_PWRONPRGDONE BIT(11)
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#define USBDEVFUNC_CGOUTNAK BIT(10)
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#define USBDEVFUNC_SGOUTNAK BIT(9)
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#define USBDEVFUNC_CGNPINNAK BIT(8)
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#define USBDEVFUNC_SGNPINNAK BIT(7)
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#define USBDEVFUNC_TSTCTL_MASK (0x7 << 4)
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#define USBDEVFUNC_TSTCTL_SHIFT 4
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#define USBDEVFUNC_GOUTNAKSTS BIT(3)
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#define USBDEVFUNC_GNPINNAKSTS BIT(2)
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#define USBDEVFUNC_SFTDISCON BIT(1)
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#define USBDEVFUNC_RMTWKUPSIG BIT(0)
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#define USBLINESTS UDC_REG(0x208)
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#define USBLINESTS_SOFFN_MASK (0x3fff << 8)
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#define USBLINESTS_SOFFN_SHIFT 8
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#define USBLINESTS_SOFFN_LIMIT 0x3fff
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#define USBLINESTS_SOFFN(_x) ((_x) << 8)
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#define USBLINESTS_ERRATICERR BIT(3)
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#define USBLINESTS_ENUMSPD_MASK (0x3 << 1)
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#define USBLINESTS_ENUMSPD_SHIFT 1
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#define USBLINESTS_ENUMSPD_HS 0
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#define USBLINESTS_ENUMSPD_FS 1
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#define USBLINESTS_ENUMSPD_LS 2
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#define USBLINESTS_ENUMSPD_FS48 3
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#define USBLINESTS_SUSPSTS BIT(0)
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#define INEPINTMSK UDC_REG(0x20C)
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#define INEPINTMSK_NAKMSK BIT(13)
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#define INEPINTMSK_TXFIFOEMPTY BIT(7)
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#define INEPINTMSK_INEPNAKEFFMSK BIT(6)
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#define INEPINTMSK_INTKNEPMISMSK BIT(5)
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#define INEPINTMSK_INTKNTXFEMPMSK BIT(4)
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#define INEPINTMSK_TIMEOUTMSK BIT(3)
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#define INEPINTMSK_AHBERRMSK BIT(2)
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#define INEPINTMSK_EPDISBLDMSK BIT(1)
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#define INEPINTMSK_XFERCOMPLMSK BIT(0)
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#define OUTEPINTMSK UDC_REG(0x210)
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#define OUTEPINTMSK_BACK2BACKSETUP BIT(6)
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#define OUTEPINTMSK_STSPHSERCVDMSK BIT(5)
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#define OUTEPINTMSK_OUTTKNEPDISMSK BIT(4)
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#define OUTEPINTMSK_SETUPMSK BIT(3)
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#define OUTEPINTMSK_AHBERRMSK BIT(2)
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#define OUTEPINTMSK_EPDISBLDMSK BIT(1)
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#define OUTEPINTMSK_XFERCOMPLMSK BIT(0)
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#define USBEPINT UDC_REG(0x214)
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#define USBEPINTMSK UDC_REG(0x218)
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#define USBEPINT_OUTEP_SHIFT 16
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#define USBEPINT_OUTEP(_x) (1 << ((_x) + 16))
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#define USBEPINT_INEP(_x) (1 << (_x))
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#define INEPCFG0 UDC_REG(0x220)
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#define INEPCFG(_a) UDC_REG(0x220 + ((_a) * 0x4))
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#define OUTEPCFG0 UDC_REG(0x240)
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#define OUTEPCFG(_a) UDC_REG(0x240 + ((_a) * 0x4))
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#define EP0CTL_MPS_MASK (0x3 << 0)
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#define EP0CTL_MPS_SHIFT 0
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#define EP0CTL_MPS_64 0
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#define EP0CTL_MPS_32 1
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#define EP0CTL_MPS_16 2
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#define EP0CTL_MPS_8 3
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#define EPCTL_EPENA BIT(31)
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#define EPCTL_EPDIS BIT(30)
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#define EPCTL_SETD1PID BIT(29)
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#define EPCTL_SETODDFR BIT(29)
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#define EPCTL_SETD0PID BIT(28)
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#define EPCTL_SETEVENFR BIT(28)
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#define EPCTL_SNAK BIT(27)
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#define EPCTL_CNAK BIT(26)
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#define EPCTL_TXFNUM_MASK (0xf << 22)
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#define EPCTL_TXFNUM_SHIFT 22
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#define EPCTL_TXFNUM_LIMIT 0xf
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#define EPCTL_TXFNUM(_x) ((_x) << 22)
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#define EPCTL_STALL BIT(21)
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#define EPCTL_SNP BIT(20)
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#define EPCTL_EPTYPE_MASK (0x3 << 18)
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#define EPCTL_EPTYPE_CONTROL (0x0 << 18)
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#define EPCTL_EPTYPE_ISO (0x1 << 18)
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#define EPCTL_EPTYPE_BULK (0x2 << 18)
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#define EPCTL_EPTYPE_INTERRUPT (0x3 << 18)
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#define EPCTL_NAKSTS BIT(17)
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#define EPCTL_DPID BIT(16)
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#define EPCTL_EOFRNUM BIT(16)
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#define EPCTL_USBACTEP BIT(15)
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#define EPCTL_NEXTEP_MASK (0xf << 11)
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#define EPCTL_NEXTEP_SHIFT 11
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#define EPCTL_NEXTEP_LIMIT 0xf
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#define EPCTL_NEXTEP(_x) ((_x) << 11)
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#define EPCTL_MPS_MASK (0x7ff << 0)
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#define EPCTL_MPS_SHIFT 0
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#define EPCTL_MPS_LIMIT 0x7ff
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#define EPCTL_MPS(_x) ((_x) << 0)
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#define INEPINT(_a) UDC_REG(0x260 + ((_a) * 0x4))
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#define OUTEPINT(_a) UDC_REG(0x280 + ((_a) * 0x4))
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#define EPINT_SETUP_RCVD BIT(15)
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#define EPINT_NYETINTRPT BIT(14)
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#define EPINT_NAKINTRPT BIT(13)
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#define EPINT_BBLEERRINTRPT BIT(12)
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#define EPINT_PKTDRPSTS BIT(11)
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#define EPINT_TXFEMP BIT(7)
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#define EPINT_INEPNAKEFF BIT(6)
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#define EPINT_BACK2BACKSETUP BIT(6)
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#define EPINT_INTKNEPMIS BIT(5)
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#define EPINT_STSPHSERCVD BIT(5)
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#define EPINT_INTKNTXFEMP BIT(4)
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#define EPINT_OUTTKNEPDIS BIT(4)
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#define EPINT_TIMEOUT BIT(3)
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#define EPINT_SETUP BIT(3)
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#define EPINT_AHBERR BIT(2)
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#define EPINT_EPDISBLD BIT(1)
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#define EPINT_XFERCOMPL BIT(0)
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#define INEPTSFSIZ0 UDC_REG(0x2A0)
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#define INEPTSFSIZ0_PKTCNT_MASK (0x3 << 19)
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#define INEPTSFSIZ0_PKTCNT_SHIFT 19
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#define INEPTSFSIZ0_PKTCNT_LIMIT 0x3
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#define INEPTSFSIZ0_PKTCNT(_x) ((_x) << 19)
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#define INEPTSFSIZ0_XFERSIZE_MASK (0x7f << 0)
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#define INEPTSFSIZ0_XFERSIZE_SHIFT 0
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#define INEPTSFSIZ0_XFERSIZE_LIMIT 0x7f
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#define INEPTSFSIZ0_XFERSIZE(_x) ((_x) << 0)
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#define OUTEPTSFSIZ0 UDC_REG(0x2C0)
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#define OUTEPTSFSIZ0_SUPCNT_MASK (0x3 << 29)
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#define OUTEPTSFSIZ0_SUPCNT_SHIFT 29
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#define OUTEPTSFSIZ0_SUPCNT_LIMIT 0x3
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#define OUTEPTSFSIZ0_SUPCNT(_x) ((_x) << 29)
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#define OUTEPTSFSIZ0_PKTCNT BIT(19)
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#define OUTEPTSFSIZ0_XFERSIZE_MASK (0x7f << 0)
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#define OUTEPTSFSIZ0_XFERSIZE_SHIFT 0
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#define INEPTSFSIZ(_a) UDC_REG(0x2A0 + ((_a) * 0x4))
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#define OUTEPTSFSIZ(_a) UDC_REG(0x2C0 + ((_a) * 0x4))
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#define EPTSIZ_MC_MASK (0x3 << 29)
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#define EPTSIZ_MC_SHIFT 29
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#define EPTSIZ_MC_LIMIT 0x3
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#define EPTSIZ_MC(_x) ((_x) << 29)
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#define EPTSIZ_PKTCNT_MASK (0x3ff << 19)
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#define EPTSIZ_PKTCNT_SHIFT 19
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#define EPTSIZ_PKTCNT_LIMIT 0x3ff
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#define EPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
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#define EPTSIZ_PKTCNT(_x) ((_x) << 19)
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#define EPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
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#define EPTSIZ_XFERSIZE_SHIFT 0
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#define EPTSIZ_XFERSIZE_LIMIT 0x7ffff
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#define EPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
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#define EPTSIZ_XFERSIZE(_x) ((_x) << 0)
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#define INEPDMAADDR(_a) UDC_REG(0x300 + ((_a) * 0x4))
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#define OUTEPDMAADDR(_a) UDC_REG(0x320 + ((_a) * 0x4))
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#define INEPTXSTS(_a) UDC_REG(0x340 + ((_a) * 0x4))
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#define DTKNQR1 UDC_REG(0x360)
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#define DTKNQR2 UDC_REG(0x364)
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#define DTKNQR3 UDC_REG(0x368)
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#define DTKNQR4 UDC_REG(0x36C)
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#define PCGCTL UDC_REG(0x0040)
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#define PCGCTL_STOPPCLK BIT(0)
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#define UDCVERSION UDC_REG(0x0FFC)
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#define EP_FIFO(_a) UDC_REG(0x1000 + ((_a) * 0x1000))
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#endif /* __AIC_UDC_REG_H__ */
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