100 lines
2.1 KiB
C
100 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Device Tree support for Artinchip SoCs
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*
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* Copyright (C) 2021 Artinchip Technology Co., Ltd
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*/
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#ifndef __DT_BINDINGS_CLOCK_AIC_CMU_H
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#define __DT_BINDINGS_CLOCK_AIC_CMU_H
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/* Fixed rate clock */
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#define CLK_DUMMY 0
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#define CLK_OSC24M 1
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#define CLK_OSC32K 2
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#define CLK_RC1M 3
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/* PLL clock */
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#define CLK_PLL_INT0 4
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#define CLK_PLL_INT1 5
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#define CLK_PLL_FRA0 6
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#define CLK_PLL_FRA1 7
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#define CLK_PLL_FRA2 8
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/* system clock */
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#define CLK_AXI0 9
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#define CLK_AHB0 10
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#define CLK_APB0 11
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#define CLK_APB1 12
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#define CLK_CPU 13
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/* Peripheral clock */
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#define CLK_DMA 14
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#define CLK_CE 15
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#define CLK_USBD 16
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#define CLK_USBH0 17
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#define CLK_USBH1 18
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#define CLK_USB_PHY0 19
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#define CLK_USB_PHY1 20
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#define CLK_GMAC0 21
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#define CLK_GMAC1 22
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#define CLK_SPI0 23
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#define CLK_SPI1 24
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#define CLK_SPI2 25
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#define CLK_SPI3 26
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#define CLK_SDMC0 27
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#define CLK_SDMC1 28
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#define CLK_SDMC2 29
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#define CLK_SYSCFG 30
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#define CLK_RTC 31
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#define CLK_SPIENC 32
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#define CLK_I2S0 33
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#define CLK_I2S1 34
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#define CLK_CODEC 35
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#define CLK_RGB 36
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#define CLK_DBI 36
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#define CLK_LVDS 37
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#define CLK_MIPIDSI 38
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#define CLK_DE 39
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#define CLK_GE 40
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#define CLK_VE 41
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#define CLK_WDOG 42
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#define CLK_SID 43
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#define CLK_GTC 44
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#define CLK_GPIO 45
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#define CLK_UART0 46
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#define CLK_UART1 47
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#define CLK_UART2 48
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#define CLK_UART3 49
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#define CLK_UART4 50
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#define CLK_UART5 51
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#define CLK_UART6 52
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#define CLK_UART7 53
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#define CLK_I2C0 54
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#define CLK_I2C1 55
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#define CLK_I2C2 56
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#define CLK_I2C3 57
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#define CLK_CAN0 58
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#define CLK_CAN1 59
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#define CLK_PWM 60
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#define CLK_ADCIM 61
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#define CLK_GPAI 62
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#define CLK_RTP 63
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#define CLK_TSEN 64
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#define CLK_CIR 65
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#define CLK_DVP 66
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#define CLK_PBUS 67
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#define CLK_MTOP 68
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#define CLK_DM 69
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#define CLK_PWMCS 70
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#define CLK_PSADC 71
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#define CLK_DDR 72
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/* Display clock */
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#define CLK_PIX 73
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#define CLK_SCLK 74
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/* Output clock */
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#define CLK_OUT0 75
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#define CLK_OUT1 76
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#define CLK_OUT2 77
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#define CLK_OUT3 78
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#define AIC_CLK_END 79
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#endif
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