277 lines
9.7 KiB
C
277 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021-2024 ArtInChip Technology Co., Ltd
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* Authors: Dehuang Wu <dehuang.wu@artinchip.com>
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*/
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#include <common.h>
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#include <mapmem.h>
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#include <dm.h>
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#include <errno.h>
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#include <reset-uclass.h>
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#include <dt-structs.h>
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#include <asm/io.h>
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#include <dm/lists.h>
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#include <linux/log2.h>
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#include <dt-bindings/reset/artinchip,aic-reset-v20.h>
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#include "reset-artinchip-common.h"
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struct aic_reset_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_artinchip_aic_reset_v2_0 dtplat;
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#endif
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};
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/* artinchip,aic-reset-v2.0 */
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#define CLK_SESS_CPU_REG (0x0180)
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#define CLK_SE_WDOG_REG (0x018C)
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#define CLK_SE_DMA_REG (0x0190)
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#define CLK_SE_CE_REG (0x0194)
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#define CLK_SE_SPI_REG (0x0198)
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#define CLK_SE_SID_REG (0x01A0)
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#define CLK_SE_I2C_REG (0x01A4)
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#define CLK_SE_GPIO_REG (0x01A8)
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#define CLK_SE_SPIENC_REG (0x01AC)
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#define CLK_SCSS_CPU_REG (0x01F0)
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#define CLK_SC_WDOG_REG (0x01FC)
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#define CLK_CORE_CPU_REG (0x0200)
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#define CLK_CORE_WDOG_REG (0x020C)
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#define CLK_DDR_REG (0x0210)
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#define CLK_DISP_REG (0x0220)
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#define CLK_DMA0_REG (0x0410)
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#define CLK_DMA1_REG (0x0414)
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#define CLK_DMA2_REG (0x0418)
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#define CLK_DCE_REG (0x041C)
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#define CLK_USBH0_REG (0x0420)
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#define CLK_USBH1_REG (0x0424)
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#define CLK_USB_PHY0_REG (0x0430)
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#define CLK_USB_PHY1_REG (0x0434)
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#define CLK_SPI0_REG (0x045C)
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#define CLK_SPI1_REG (0x0460)
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#define CLK_SPI2_REG (0x0464)
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#define CLK_SPI3_REG (0x0468)
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#define CLK_SPI4_REG (0x046C)
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#define CLK_SDMC0_REG (0x0470)
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#define CLK_SDMC1_REG (0x0474)
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#define CLK_SYSCFG_REG (0x0800)
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#define CLK_MTOP_REG (0x081C)
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#define CLK_I2S0_REG (0x0820)
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#define CLK_AUDIO_REG (0x0830)
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#define CLK_UART0_REG (0x0840)
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#define CLK_UART1_REG (0x0844)
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#define CLK_UART2_REG (0x0848)
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#define CLK_UART3_REG (0x084C)
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#define CLK_UART4_REG (0x0850)
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#define CLK_UART5_REG (0x0854)
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#define CLK_LCD_REG (0x0880)
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#define CLK_LVDS_REG (0x0884)
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#define CLK_DVP_REG (0x0890)
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#define CLK_DE_REG (0x08C0)
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#define CLK_SID_REG (0x0904)
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#define CLK_I2C0_REG (0x0960)
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#define CLK_I2C1_REG (0x0964)
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#define CLK_I2C2_REG (0x0968)
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#define CLK_I2C3_REG (0x096C)
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#define CLK_I2C4_REG (0x0970)
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#define CLK_ADCIM_REG (0x09A0)
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#define CLK_GPAI_REG (0x09A4)
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#define CLK_THS_REG (0x09AC)
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#define CLK_SCAN_REG (0x0C00)
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#define CLK_PRT_REG (0x0C00)
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#define CLK_PRT_LSU_REG (0x0C04)
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#define CLK_PRT_FUSER_REG (0x0C08)
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#define CLK_PRT_SBP_REG (0x0C0C)
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#define CLK_IMG_ROT_REG (0x0C10)
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#define CLK_IMG_HT_REG (0x0C14)
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#define CLK_IMG_CRS0_REG (0x0C18)
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#define CLK_IMG_CRS1_REG (0x0C1C)
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#define CLK_IMG_PP0_REG (0x0C20)
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#define CLK_IMG_PP1_REG (0x0C24)
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#define CLK_IMG_EHC0_REG (0x0C28)
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#define CLK_IMG_EHC1_REG (0x0C2C)
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#define CLK_USM_SCALE_REG (0x0C30)
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#define CLK_IMG_JBIG0_REG (0x0C38)
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#define CLK_IMG_JBIG1_REG (0x0C3C)
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#define CLK_IMG_JPEG0_REG (0x0C40)
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#define CLK_IMG_JPEG1_REG (0x0C44)
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#define CLK_XPWM_SDFM_REG (0x0240)
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#define CLK_PWM_SDFM_REG (0x0244)
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#define CLK_CAP_SDFM_REG (0x0248)
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#define CLK_XPWM_REG(x) ((x) * 0x4 + 0x0B00) /* 0 ~ 7 */
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#define CLK_PWM_REG(x) ((x) * 0x4 + 0x0B40) /* 0 ~ 15 */
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#define CLK_CAP_REG(x) ((x) * 0x4 + 0x0B80) /* 0 ~ 4 */
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#define CLK_GPT_REG(x) ((x) * 0x4 + 0x0BC0) /* 0 ~ 9 */
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#define CLK_QSPI_REG(x) ((x) * 0x4 + 0x0460) /* 0 ~ 4 */
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#define CLK_NULL_REG (0x0FFC)
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#define CLK_VER_REG (0x0FFC)
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#define CLK_SP_CPU_REG (0x0038)
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#define CLK_SP_WDT_REG (0x0040)
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#define CLK_SP_USBD_REG (0x0044)
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#define CLK_SP_USB_PHY0_REG (0x0048)
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#define CLK_SP_GMAC_REG (0x004C)
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#define CLK_SP_GPIO_REG (0x0050)
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#define CLK_SP_UART0_REG (0x0054)
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#define CLK_SP_UART1_REG (0x0058)
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#define CLK_SP_RTC_REG (0x005C)
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#define CLK_SP_GTC_REG (0x0060)
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#define CLK_SP_I2C_REG (0x0064)
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#define CLK_SP_GMAC_CFG_REG (0x0084)
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#define PM_VDD11 (0x0070)
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#define PM_USBD_REXT (0x0080)
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#define PM_BAK (0x0080)
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#define RESET_DESC(_id, _reg) {.id = _id, .bit = 13, .reg = _reg}
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static struct artinchip_reset rest_info[] = {
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/* id reg */
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RESET_DESC(RESET_SE_WDOG, CLK_SE_WDOG_REG),
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RESET_DESC(RESET_SE_DMA, CLK_SE_DMA_REG),
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RESET_DESC(RESET_SE_CE, CLK_SE_CE_REG),
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RESET_DESC(RESET_SE_SPI, CLK_SE_SPI_REG),
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RESET_DESC(RESET_SE_I2C, CLK_SE_I2C_REG),
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RESET_DESC(RESET_SE_SPIENC, CLK_SE_SPIENC_REG),
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RESET_DESC(RESET_SC_WDOG, CLK_SC_WDOG_REG),
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RESET_DESC(RESET_SC_CPU, CLK_SCSS_CPU_REG),
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RESET_DESC(RESET_CORE_CPU, CLK_CORE_CPU_REG),
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RESET_DESC(RESET_CORE_WDOG, CLK_CORE_WDOG_REG),
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RESET_DESC(RESET_DCE, CLK_DCE_REG),
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RESET_DESC(RESET_DMA0, CLK_DMA0_REG),
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RESET_DESC(RESET_DMA1, CLK_DMA1_REG),
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RESET_DESC(RESET_DMA2, CLK_DMA2_REG),
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RESET_DESC(RESET_DCE, CLK_DCE_REG),
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RESET_DESC(RESET_USBH0, CLK_USBH0_REG),
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RESET_DESC(RESET_USBH1, CLK_USBH1_REG),
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RESET_DESC(RESET_USB_PHY0, CLK_USB_PHY0_REG),
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RESET_DESC(RESET_USB_PHY1, CLK_USB_PHY1_REG),
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RESET_DESC(RESET_SPI0, CLK_SPI0_REG),
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RESET_DESC(RESET_SPI1, CLK_SPI1_REG),
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RESET_DESC(RESET_SPI2, CLK_SPI2_REG),
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RESET_DESC(RESET_SPI3, CLK_SPI3_REG),
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RESET_DESC(RESET_SPI4, CLK_SPI4_REG),
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RESET_DESC(RESET_SDMC0, CLK_SDMC0_REG),
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RESET_DESC(RESET_SDMC1, CLK_SDMC1_REG),
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RESET_DESC(RESET_MTOP, CLK_MTOP_REG),
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RESET_DESC(RESET_I2S0, CLK_I2S0_REG),
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RESET_DESC(RESET_AUDIO, CLK_AUDIO_REG),
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RESET_DESC(RESET_UART0, CLK_UART0_REG),
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RESET_DESC(RESET_UART1, CLK_UART1_REG),
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RESET_DESC(RESET_UART2, CLK_UART2_REG),
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RESET_DESC(RESET_UART3, CLK_UART3_REG),
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RESET_DESC(RESET_UART4, CLK_UART4_REG),
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RESET_DESC(RESET_UART5, CLK_UART5_REG),
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RESET_DESC(RESET_ADCIM, CLK_ADCIM_REG),
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RESET_DESC(RESET_GPAI, CLK_GPAI_REG),
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RESET_DESC(RESET_THS, CLK_THS_REG),
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RESET_DESC(RESET_LCD, CLK_LCD_REG),
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RESET_DESC(RESET_LVDS, CLK_LVDS_REG),
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RESET_DESC(RESET_DVP, CLK_DVP_REG),
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RESET_DESC(RESET_DE, CLK_DE_REG),
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RESET_DESC(RESET_I2C0, CLK_I2C0_REG),
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RESET_DESC(RESET_I2C1, CLK_I2C1_REG),
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RESET_DESC(RESET_I2C2, CLK_I2C2_REG),
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RESET_DESC(RESET_I2C3, CLK_I2C3_REG),
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RESET_DESC(RESET_I2C4, CLK_I2C4_REG),
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RESET_DESC(RESET_SCAN, CLK_SCAN_REG),
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RESET_DESC(RESET_PRT, CLK_PRT_REG),
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RESET_DESC(RESET_PRT, CLK_PRT_LSU_REG),
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RESET_DESC(RESET_PRT, CLK_PRT_FUSER_REG),
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RESET_DESC(RESET_PRT, CLK_PRT_SBP_REG),
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RESET_DESC(RESET_IMG_ROT, CLK_IMG_ROT_REG),
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RESET_DESC(RESET_IMG_HT, CLK_IMG_HT_REG),
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RESET_DESC(RESET_IMG_CRS0, CLK_IMG_CRS0_REG),
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RESET_DESC(RESET_IMG_CRS1, CLK_IMG_CRS1_REG),
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RESET_DESC(RESET_IMG_PP0, CLK_IMG_PP0_REG),
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RESET_DESC(RESET_IMG_PP1, CLK_IMG_PP1_REG),
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RESET_DESC(RESET_IMG_EHC0, CLK_IMG_EHC0_REG),
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RESET_DESC(RESET_IMG_EHC1, CLK_IMG_EHC1_REG),
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RESET_DESC(RESET_IMG_USM_SCALE, CLK_USM_SCALE_REG),
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RESET_DESC(RESET_IMG_JBIG0, CLK_IMG_JBIG0_REG),
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RESET_DESC(RESET_IMG_JBIG1, CLK_IMG_JBIG1_REG),
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RESET_DESC(RESET_IMG_JPEG0, CLK_IMG_JPEG0_REG),
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RESET_DESC(RESET_IMG_JPEG1, CLK_IMG_JPEG1_REG),
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RESET_DESC(RESET_XPWM0, CLK_XPWM_REG(0)),
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RESET_DESC(RESET_XPWM1, CLK_XPWM_REG(1)),
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RESET_DESC(RESET_XPWM2, CLK_XPWM_REG(2)),
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RESET_DESC(RESET_XPWM3, CLK_XPWM_REG(3)),
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RESET_DESC(RESET_XPWM4, CLK_XPWM_REG(4)),
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RESET_DESC(RESET_XPWM5, CLK_XPWM_REG(5)),
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RESET_DESC(RESET_XPWM6, CLK_XPWM_REG(6)),
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RESET_DESC(RESET_XPWM7, CLK_XPWM_REG(7)),
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RESET_DESC(RESET_PWM0, CLK_PWM_REG(0)),
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RESET_DESC(RESET_PWM1, CLK_PWM_REG(1)),
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RESET_DESC(RESET_PWM2, CLK_PWM_REG(2)),
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RESET_DESC(RESET_PWM3, CLK_PWM_REG(3)),
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RESET_DESC(RESET_PWM4, CLK_PWM_REG(4)),
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RESET_DESC(RESET_PWM5, CLK_PWM_REG(5)),
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RESET_DESC(RESET_PWM6, CLK_PWM_REG(6)),
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RESET_DESC(RESET_PWM7, CLK_PWM_REG(7)),
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RESET_DESC(RESET_PWM8, CLK_PWM_REG(8)),
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RESET_DESC(RESET_PWM9, CLK_PWM_REG(9)),
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RESET_DESC(RESET_PWM10, CLK_PWM_REG(10)),
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RESET_DESC(RESET_PWM11, CLK_PWM_REG(11)),
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RESET_DESC(RESET_PWM12, CLK_PWM_REG(12)),
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RESET_DESC(RESET_PWM13, CLK_PWM_REG(13)),
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RESET_DESC(RESET_PWM14, CLK_PWM_REG(14)),
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RESET_DESC(RESET_PWM15, CLK_PWM_REG(15)),
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RESET_DESC(RESET_CAP0, CLK_CAP_REG(0)),
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RESET_DESC(RESET_CAP1, CLK_CAP_REG(1)),
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RESET_DESC(RESET_CAP2, CLK_CAP_REG(2)),
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RESET_DESC(RESET_CAP3, CLK_CAP_REG(3)),
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RESET_DESC(RESET_CAP4, CLK_CAP_REG(4)),
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RESET_DESC(RESET_GPT0, CLK_GPT_REG(0)),
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RESET_DESC(RESET_GPT1, CLK_GPT_REG(1)),
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RESET_DESC(RESET_GPT2, CLK_GPT_REG(2)),
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RESET_DESC(RESET_GPT3, CLK_GPT_REG(3)),
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RESET_DESC(RESET_GPT4, CLK_GPT_REG(4)),
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RESET_DESC(RESET_GPT5, CLK_GPT_REG(5)),
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RESET_DESC(RESET_GPT6, CLK_GPT_REG(6)),
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RESET_DESC(RESET_GPT7, CLK_GPT_REG(7)),
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RESET_DESC(RESET_GPT8, CLK_GPT_REG(8)),
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RESET_DESC(RESET_GPT9, CLK_GPT_REG(9)),
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RESET_DESC(RESET_SP_USBD, CLK_SP_USBD_REG),
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RESET_DESC(RESET_SP_USB_PHY0, CLK_SP_USB_PHY0_REG),
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RESET_DESC(RESET_SP_UART0, CLK_SP_UART0_REG),
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RESET_DESC(RESET_SP_UART1, CLK_SP_UART1_REG),
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};
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static int aic_reset_probe(struct udevice *dev)
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{
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struct artinchip_reset_priv *priv = dev_get_priv(dev);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct aic_reset_plat *plat = dev_get_plat(dev);
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struct dtd_artinchip_aic_reset_v2_0 *dtplat = &plat->dtplat;
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priv->base = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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priv->cz_base = map_sysmem(dtplat->reg[2], dtplat->reg[3]);
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#else
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priv->base = dev_read_addr_ptr(dev);
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priv->cz_base = (void *)(uintptr_t)dev_read_addr_index(dev, 1);
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#endif
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priv->count = ARRAY_SIZE(rest_info);
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priv->max_id = RESET_NUMBER;
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priv->rests = rest_info;
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return 0;
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}
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static const struct udevice_id aic_clk_ids[] = {
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{ .compatible = "artinchip,aic-reset-v2.0", },
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{ }
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};
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static struct reset_ops aic_reset_ops = {
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.request = artinchip_reset_request,
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.rfree = artinchip_reset_free,
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.rst_assert = artinchip_reset_assert,
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.rst_deassert = artinchip_reset_deassert,
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};
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U_BOOT_DRIVER(aic_reset_v2_0) = {
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.name = "artinchip_aic_reset_v2_0",
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.id = UCLASS_RESET,
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.of_match = aic_clk_ids,
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.ops = &aic_reset_ops,
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.probe = aic_reset_probe,
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.priv_auto = sizeof(struct artinchip_reset_priv),
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.plat_auto = sizeof(struct aic_reset_plat),
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};
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