291 lines
9.9 KiB
C
291 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 ArtInChip Technology Co., Ltd
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* Dehuang Wu <dehuang.wu@artinchip.com>
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*/
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#include <common.h>
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#include <mapmem.h>
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#include <dm.h>
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#include <errno.h>
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#include <reset-uclass.h>
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#include <dt-structs.h>
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#include <asm/io.h>
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#include <dm/lists.h>
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#include <linux/log2.h>
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#include <dt-bindings/reset/artinchip,aic-reset-v30.h>
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#include "reset-artinchip-common.h"
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struct aic_reset_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_artinchip_aic_reset_v3_0 dtplat;
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#endif
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};
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/* clk-out */
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#define CLK_OUT_REG(x) ((x) * 0x4 + 0x00E0) /* 0 ~ 3 */
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#define CLK_AXI_REG (0x0100)
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#define CLK_AHB_REG (0x0110)
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#define CLK_APB_REG (0x0120)
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#define CLK_CPU0_REG (0x0180)
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#define CLK_CPU1_REG (0x0190)
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#define RST_ENTRY_CPU0_REG (0x0184)
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#define RST_ENTRY_CPU1_REG (0x0194)
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#define CLK_PRE_DIV(x) ((x) * 0x4 + 0x01C0) /* 0 ~ 7 */
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#define CLK_WDOG_REG (0x020C)
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#define CLK_DDR_REG (0x0210)
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#define CLK_DDR_PHY_REG (0x0214)
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#define CLK_DISP0_SCLK_REG (0x0220)
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#define CLK_DISP0_PIX_REG (0x0224)
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#define CLK_DISP1_SCLK_REG (0x0228)
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#define CLK_DISP1_PIX_REG (0x022C)
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#define CLK_AUDIO_SCLK_REG (0x0230)
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#define CLK_DMA0_REG (0x0400)
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#define CLK_DMA1_REG (0x0404)
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#define CLK_DCE_REG (0x0414)
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#define CLK_CE_REG (0x0418)
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#define CLK_USB_DEV_REG (0x041C)
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#define CLK_USBH0_REG (0x0420)
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#define CLK_USBH1_REG (0x0424)
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#define CLK_USB_PHY0_REG (0x0430)
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#define CLK_USB_PHY1_REG (0x0434)
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#define CLK_USB_FS_DR_REG (0x043C)
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#define CLK_GMAC0_REG (0x0440)
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#define CLK_GMAC1_REG (0x0444)
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#define CLK_CANFD_REG (0x0450)
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#define CLK_XSPI_REG (0x045C)
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#define CLK_QSPI_REG(x) ((x) * 0x4 + 0x0460) /* 0 ~ 3 */
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#define CLK_SDMC_REG(x) ((x) * 0x4 + 0x0470) /* 0 ~ 2 */
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#define CLK_PBUS_REG (0x04A0)
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#define CLK_SYSCFG_REG (0x0800)
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#define CLK_SPIENC_REG (0x0810)
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#define CLK_PWMCS_REG (0x0814)
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#define CLK_MTOP_REG (0x081C)
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#define CLK_I2S_REG(x) ((x) * 0x4 + 0x0820) /* 0 ~ 2 */
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#define CLK_SAI_REG (0x082C)
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#define CLK_AUDIO_REG (0x0830)
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#define CLK_GPIO_REG (0x083C)
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#define CLK_UART_REG(x) ((x) * 0x4 + 0x0840) /* 0 ~ 7 */
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#define CLK_LCD0_REG (0x0880)
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#define CLK_LVDS0_REG (0x0884)
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#define CLK_MIPI_DSI_REG (0x0888)
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#define CLK_MIPI_DPHY0_REG (0x088C)
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#define CLK_DVP_REG (0x0890)
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#define CLK_MIPI_CSI_REG (0x0898)
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#define CLK_MIPI_DPHY1_REG (0x089C)
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#define CLK_LCD1_REG (0x08A0)
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#define CLK_LVDS1_REG (0x08A4)
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#define CLK_TVE_REG (0x08B4)
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#define CLK_DE_REG (0x08C0)
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#define CLK_GE_REG (0x08C4)
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#define CLK_VE_REG (0x08C8)
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#define CLK_SID_REG (0x0904)
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/* clk-core system */
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#define CLK_I2C_REG(x) ((x) * 0x4 + 0x0960) /* 0 ~ 2 */
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#define CLK_XPWM_REG(x) ((x) * 0x4 + 0x0990) /* 0 ~ 3 */
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#define CLK_ADCIM_REG (0x09A0)
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#define CLK_GPAI_REG (0x09A4)
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#define CLK_RTP_REG (0x09A8)
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#define CLK_THS_REG (0x09AC)
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#define CLK_CIR_REG (0x09B0)
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#define CLK_CMP_REG (0x09E4)
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#define CLK_GPT_REG(x) ((x) * 0x4 + 0x0A00) /* 0 ~ 5 */
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/* clk-dpll */
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#define CLK_DPLL_CFG0_REG(x) ((x) * 0x10 + 0x0E00) /* 0 ~ 4 */
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#define CLK_DPLL_CFG1_REG(x) ((x) * 0x10 + 0x0E04) /* 0 ~ 4 */
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#define CLK_DPLL_CFG2_REG(x) ((x) * 0x10 + 0x0E08) /* 0 ~ 4 */
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#define CLK_DPLL_STS_REG(x) ((x) * 0x10 + 0x0E0C) /* 0 ~ 4 */
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/* clk-pll_int */
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#define CLK_PLL_INT_CFG_REG(x) ((x) * 0x10 + 0x0F00) /* 0 ~ 1 */
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#define CLK_PLL_INT_STS_REG(x) ((x) * 0x10 + 0x0F0C) /* 0 ~ 1 */
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/* clk-pll_fra */
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#define CLK_PLL_FRA_GEN_REG(x) ((x) * 0x10 + 0x0F80) /* 0 ~ 2 */
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#define CLK_PLL_FRA_CFG_REG(x) ((x) * 0x10 + 0x0F84) /* 0 ~ 2 */
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#define CLK_PLL_FRA_SDM_REG(x) ((x) * 0x10 + 0x0F88) /* 0 ~ 2 */
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#define CLK_PLL_FRA_STS_REG(x) ((x) * 0x10 + 0x0F8C) /* 0 ~ 2 */
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#ifdef CONFIG_DEBUG_ON_FPGA_BOARD_ARTINCHIP
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#define FPGA_MMCM2_CFG_REG (0x0FE0)
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#define FPGA_MMCM2_STS_REG (0x0FE4)
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#endif
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#define PLL_COM_REG (0x0FF0)
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#define PLL_IN_REG (0x0FF4)
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#define CMU_AFE_VER_REG (0x0FF8)
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#define CMU_VER_REG (0x0FFC)
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#define CLK_NULL_REG (0x0FFC)
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/* PRCM Real-Time system clk */
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#define CLK_R_AXI_REG (0x0100)
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#define CLK_R_AHB_REG (0x0110)
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#define CLK_R_CPU_REG (0x0180)
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#define CLK_R_PRE_DIV_REG (0x01C0)
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#define CLK_R_WDOG_REG (0x020C)
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#define CLK_R_DMA_REG (0x0400)
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#define CLK_R_CANFD0_REG (0x0450)
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#define CLK_R_CANFD1_REG (0x0454)
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#define CLK_R_SPI_REG (0x0460)
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#define CLK_R_GPIO_REG (0x083C)
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#define CLK_R_UART0_REG (0x0840)
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#define CLK_R_UART1_REG (0x0844)
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#define CLK_R_RTC_REG (0x0908)
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#define CLK_R_GTC_REG (0x090C)
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#define CLK_R_I2C0_REG (0x0960)
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#define CLK_R_I2C1_REG (0x0964)
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#define CLK_R_XPWM0_REG (0x0990)
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#define CLK_R_XPWM1_REG (0x0994)
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#define CLK_R_XPWM2_REG (0x0998)
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#define CLK_R_XPWM3_REG (0x099C)
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#define CLK_R_CIR_REG (0x09B0)
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#define CLK_R_DPLL_CFG0_REG (0x0E00)
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#define CLK_R_DPLL_CFG1_REG (0x0E04)
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#define CLK_R_DPLL_CFG2_REG (0x0E08)
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#define CLK_R_DPLL_STS_REG (0x0E0C)
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#define CLK_R_PLL_INT_CFG_REG (0x0F00)
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#define CLK_R_PLL_INT_STS_REG (0x0FF4)
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#define RESET_DESC(_id, _reg) {.id = _id, .bit = 24, .reg = _reg}
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static struct artinchip_reset rest_info[] = {
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/* id reg */
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RESET_DESC(RESET_CPU0, CLK_CPU0_REG),
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RESET_DESC(RESET_CPU1, CLK_CPU1_REG),
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RESET_DESC(RESET_WDOG, CLK_WDOG_REG),
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RESET_DESC(RESET_DDR, CLK_DDR_REG),
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RESET_DESC(RESET_DMA0, CLK_DMA0_REG),
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RESET_DESC(RESET_DMA1, CLK_DMA1_REG),
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RESET_DESC(RESET_DCE, CLK_DCE_REG),
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RESET_DESC(RESET_CE, CLK_CE_REG),
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RESET_DESC(RESET_USB_DEV, CLK_USB_DEV_REG),
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RESET_DESC(RESET_USBH0, CLK_USBH0_REG),
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RESET_DESC(RESET_USBH1, CLK_USBH1_REG),
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RESET_DESC(RESET_USB_PHY0, CLK_USB_PHY0_REG),
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RESET_DESC(RESET_USB_PHY1, CLK_USB_PHY1_REG),
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RESET_DESC(RESET_USB_FS_DR, CLK_USB_FS_DR_REG),
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RESET_DESC(RESET_GMAC0, CLK_GMAC0_REG),
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RESET_DESC(RESET_GMAC1, CLK_GMAC1_REG),
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RESET_DESC(RESET_CANFD, CLK_CANFD_REG),
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RESET_DESC(RESET_XSPI, CLK_XSPI_REG),
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RESET_DESC(RESET_QSPI0, CLK_QSPI_REG(0)),
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RESET_DESC(RESET_QSPI1, CLK_QSPI_REG(1)),
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RESET_DESC(RESET_QSPI2, CLK_QSPI_REG(2)),
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RESET_DESC(RESET_QSPI3, CLK_QSPI_REG(3)),
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RESET_DESC(RESET_SDMC0, CLK_SDMC_REG(0)),
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RESET_DESC(RESET_SDMC1, CLK_SDMC_REG(1)),
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RESET_DESC(RESET_SDMC2, CLK_SDMC_REG(2)),
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RESET_DESC(RESET_PBUS, CLK_PBUS_REG),
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RESET_DESC(RESET_SPIENC, CLK_SPIENC_REG),
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RESET_DESC(RESET_PWMCS, CLK_PWMCS_REG),
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RESET_DESC(RESET_MTOP, CLK_MTOP_REG),
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RESET_DESC(RESET_I2S0, CLK_I2S_REG(0)),
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RESET_DESC(RESET_I2S1, CLK_I2S_REG(1)),
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RESET_DESC(RESET_I2S2, CLK_I2S_REG(2)),
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RESET_DESC(RESET_SAI, CLK_SAI_REG),
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RESET_DESC(RESET_AUDIO, CLK_AUDIO_REG),
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RESET_DESC(RESET_GPIO, CLK_GPIO_REG),
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RESET_DESC(RESET_UART0, CLK_UART_REG(0)),
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RESET_DESC(RESET_UART1, CLK_UART_REG(1)),
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RESET_DESC(RESET_UART2, CLK_UART_REG(2)),
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RESET_DESC(RESET_UART3, CLK_UART_REG(3)),
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RESET_DESC(RESET_UART4, CLK_UART_REG(4)),
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RESET_DESC(RESET_UART5, CLK_UART_REG(5)),
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RESET_DESC(RESET_UART6, CLK_UART_REG(6)),
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RESET_DESC(RESET_UART7, CLK_UART_REG(7)),
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RESET_DESC(RESET_LCD0, CLK_LCD0_REG),
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RESET_DESC(RESET_LVDS0, CLK_LVDS0_REG),
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RESET_DESC(RESET_MIPI_DSI, CLK_MIPI_DSI_REG),
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RESET_DESC(RESET_MIPI_DPHY0, CLK_MIPI_DPHY0_REG),
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RESET_DESC(RESET_DVP, CLK_DVP_REG),
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RESET_DESC(RESET_MIPI_CSI, CLK_MIPI_CSI_REG),
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RESET_DESC(RESET_MIPI_DPHY1, CLK_MIPI_DPHY1_REG),
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RESET_DESC(RESET_LCD1, CLK_LCD1_REG),
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RESET_DESC(RESET_LVDS1, CLK_LVDS1_REG),
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RESET_DESC(RESET_TVE, CLK_TVE_REG),
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RESET_DESC(RESET_DE, CLK_DE_REG),
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RESET_DESC(RESET_GE, CLK_GE_REG),
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RESET_DESC(RESET_VE, CLK_VE_REG),
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RESET_DESC(RESET_I2C0, CLK_I2C_REG(0)),
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RESET_DESC(RESET_I2C1, CLK_I2C_REG(1)),
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RESET_DESC(RESET_I2C2, CLK_I2C_REG(2)),
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RESET_DESC(RESET_XPWM0, CLK_XPWM_REG(0)),
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RESET_DESC(RESET_XPWM1, CLK_XPWM_REG(1)),
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RESET_DESC(RESET_XPWM2, CLK_XPWM_REG(2)),
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RESET_DESC(RESET_XPWM3, CLK_XPWM_REG(3)),
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RESET_DESC(RESET_ADCIM, CLK_ADCIM_REG),
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RESET_DESC(RESET_GPAI, CLK_GPAI_REG),
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RESET_DESC(RESET_RTP, CLK_RTP_REG),
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RESET_DESC(RESET_THS, CLK_THS_REG),
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{.id = RESET_CIR, .bit = 13, .reg = CLK_CIR_REG},
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RESET_DESC(RESET_CMP, CLK_CMP_REG),
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RESET_DESC(RESET_GPT0, CLK_GPT_REG(0)),
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RESET_DESC(RESET_GPT1, CLK_GPT_REG(1)),
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RESET_DESC(RESET_GPT2, CLK_GPT_REG(2)),
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RESET_DESC(RESET_GPT3, CLK_GPT_REG(3)),
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RESET_DESC(RESET_GPT4, CLK_GPT_REG(4)),
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RESET_DESC(RESET_GPT5, CLK_GPT_REG(5)),
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/*PRCM Real_Time system*/
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RESET_DESC(RESET_R_CPU, CLK_R_CPU_REG),
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RESET_DESC(RESET_R_WDOG, CLK_R_WDOG_REG),
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RESET_DESC(RESET_R_DMA, CLK_R_DMA_REG),
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RESET_DESC(RESET_R_CANFD0, CLK_R_CANFD0_REG),
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RESET_DESC(RESET_R_CANFD1, CLK_R_CANFD1_REG),
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RESET_DESC(RESET_R_SPI, CLK_R_SPI_REG),
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RESET_DESC(RESET_R_GPIO, CLK_R_GPIO_REG),
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RESET_DESC(RESET_R_UART0, CLK_R_UART0_REG),
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RESET_DESC(RESET_R_UART1, CLK_R_UART1_REG),
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RESET_DESC(RESET_R_GTC, CLK_R_GTC_REG),
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RESET_DESC(RESET_R_I2C0, CLK_R_I2C0_REG),
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RESET_DESC(RESET_R_I2C1, CLK_R_I2C1_REG),
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RESET_DESC(RESET_R_XPWM0, CLK_R_XPWM0_REG),
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RESET_DESC(RESET_R_XPWM1, CLK_R_XPWM1_REG),
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RESET_DESC(RESET_R_XPWM2, CLK_R_XPWM2_REG),
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RESET_DESC(RESET_R_XPWM3, CLK_R_XPWM3_REG),
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RESET_DESC(RESET_R_CIR, CLK_R_CIR_REG),
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};
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static int aic_reset_probe(struct udevice *dev)
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{
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struct artinchip_reset_priv *priv = dev_get_priv(dev);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct aic_reset_plat *plat = dev_get_plat(dev);
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struct dtd_artinchip_aic_reset_v3_0 *dtplat = &plat->dtplat;
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priv->base = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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priv->cz_base = map_sysmem(dtplat->reg[2], dtplat->reg[3]);
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#else
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priv->base = dev_read_addr_ptr(dev);
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priv->cz_base = (void *)(uintptr_t)dev_read_addr_index(dev, 1);
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#endif
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priv->count = ARRAY_SIZE(rest_info);
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priv->max_id = RESET_NUMBER;
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priv->rests = rest_info;
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return 0;
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}
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static const struct udevice_id aic_clk_ids[] = {
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{ .compatible = "artinchip,aic-reset-v3.0", },
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{ }
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};
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static struct reset_ops aic_reset_ops = {
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.request = artinchip_reset_request,
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.rfree = artinchip_reset_free,
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.rst_assert = artinchip_reset_assert,
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.rst_deassert = artinchip_reset_deassert,
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};
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U_BOOT_DRIVER(aic_reset_v3_0) = {
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.name = "artinchip_aic_reset_v3_0",
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.id = UCLASS_RESET,
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.of_match = aic_clk_ids,
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.ops = &aic_reset_ops,
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.probe = aic_reset_probe,
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.priv_auto = sizeof(struct artinchip_reset_priv),
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.plat_auto = sizeof(struct aic_reset_plat),
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};
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