188 lines
6.9 KiB
C
188 lines
6.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 ArtInChip Technology Co., Ltd
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* Dehuang Wu <dehuang.wu@artinchip.com>
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*/
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#include <common.h>
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#include <mapmem.h>
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#include <dm.h>
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#include <errno.h>
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#include <reset-uclass.h>
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#include <dt-structs.h>
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#include <asm/io.h>
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#include <dm/lists.h>
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#include <linux/log2.h>
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#include <dt-bindings/reset/artinchip,aic-reset.h>
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#include "reset-artinchip-common.h"
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struct aic_reset_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_artinchip_aic_reset_v1_0 dtplat;
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#endif
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};
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#define CLK_DMA_REG (0x0410)
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#define CLK_CE_REG (0x0418)
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#define CLK_USBD_REG (0x041C)
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#define CLK_USBH0_REG (0x0420)
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#define CLK_USBH1_REG (0x0424)
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#define CLK_USBPHY0_REG (0x0430)
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#define CLK_USBPHY1_REG (0x0434)
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#define CLK_GMAC0_REG (0x0440)
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#define CLK_GMAC1_REG (0x0444)
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#define CLK_SPI0_REG (0x0460)
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#define CLK_SPI1_REG (0x0464)
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#define CLK_SPI2_REG (0x0468)
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#define CLK_SPI3_REG (0x046C)
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#define CLK_SDMC0_REG (0x0470)
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#define CLK_SDMC1_REG (0x0474)
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#define CLK_SDMC2_REG (0x0478)
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#define CLK_PBUS_REG (0x04A0)
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#define CLK_SYSCFG_REG (0x0800)
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#define CLK_RTC_REG (0x0908)
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#define CLK_SPIENC_REG (0x0810)
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#define CLK_PWMCS_REG (0x0814)
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#define CLK_PSADC_REG (0x0818)
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#define CLK_MTOP_REG (0x081C)
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#define CLK_I2S0_REG (0x0820)
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#define CLK_I2S1_REG (0x0824)
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#define CLK_CODEC_REG (0x0830)
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#define CLK_RGB_REG (0x0880)
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#define CLK_LVDS_REG (0x0884)
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#define CLK_MIPIDSI_REG (0x0888)
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#define CLK_DE_REG (0x08c0)
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#define CLK_GE_REG (0x08c4)
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#define CLK_VE_REG (0x08c8)
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#define CLK_WDOG_REG (0x020C)
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#define CLK_SID_REG (0x0904)
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#define CLK_GTC_REG (0x090C)
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#define CLK_GPIO_REG (0x083C)
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#define CLK_UART0_REG (0x0840)
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#define CLK_UART1_REG (0x0844)
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#define CLK_UART2_REG (0x0848)
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#define CLK_UART3_REG (0x084C)
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#define CLK_UART4_REG (0x0850)
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#define CLK_UART5_REG (0x0854)
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#define CLK_UART6_REG (0x0858)
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#define CLK_UART7_REG (0x085C)
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#define CLK_I2C0_REG (0x0960)
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#define CLK_I2C1_REG (0x0964)
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#define CLK_I2C2_REG (0x0968)
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#define CLK_I2C3_REG (0x096C)
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#define CLK_CAN0_REG (0x0980)
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#define CLK_CAN1_REG (0x0984)
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#define CLK_PWM_REG (0x0990)
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#define CLK_ADCIM_REG (0x09A0)
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#define CLK_GPAI_REG (0x09A4)
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#define CLK_RTP_REG (0x09A8)
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#define CLK_TSEN_REG (0x09AC)
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#define CLK_CIR_REG (0x09B0)
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#define RESET_DESC(_id, _reg) {.id = _id, .bit = 13, .reg = _reg}
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static struct artinchip_reset rest_info[] = {
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/* id reg */
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RESET_DESC(RESET_DMA, CLK_DMA_REG),
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RESET_DESC(RESET_CE, CLK_CE_REG),
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RESET_DESC(RESET_USBD, CLK_USBD_REG),
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RESET_DESC(RESET_USBH0, CLK_USBH0_REG),
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RESET_DESC(RESET_USBH1, CLK_USBH1_REG),
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RESET_DESC(RESET_USBPHY0, CLK_USBPHY0_REG),
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RESET_DESC(RESET_USBPHY1, CLK_USBPHY1_REG),
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RESET_DESC(RESET_GMAC0, CLK_GMAC0_REG),
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RESET_DESC(RESET_GMAC1, CLK_GMAC1_REG),
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RESET_DESC(RESET_SPI0, CLK_SPI0_REG),
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RESET_DESC(RESET_SPI1, CLK_SPI1_REG),
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RESET_DESC(RESET_SDMC0, CLK_SDMC0_REG),
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RESET_DESC(RESET_SDMC1, CLK_SDMC1_REG),
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RESET_DESC(RESET_SDMC2, CLK_SDMC2_REG),
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RESET_DESC(RESET_PBUS, CLK_PBUS_REG),
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RESET_DESC(RESET_SYSCFG, CLK_SYSCFG_REG),
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RESET_DESC(RESET_RTC, CLK_RTC_REG),
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RESET_DESC(RESET_SPIENC, CLK_SPIENC_REG),
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RESET_DESC(RESET_I2S0, CLK_I2S0_REG),
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RESET_DESC(RESET_I2S1, CLK_I2S1_REG),
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RESET_DESC(RESET_CODEC, CLK_CODEC_REG),
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RESET_DESC(RESET_RGB, CLK_RGB_REG),
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RESET_DESC(RESET_LVDS, CLK_LVDS_REG),
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RESET_DESC(RESET_MIPIDSI, CLK_MIPIDSI_REG),
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RESET_DESC(RESET_DE, CLK_DE_REG),
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RESET_DESC(RESET_GE, CLK_GE_REG),
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RESET_DESC(RESET_VE, CLK_VE_REG),
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RESET_DESC(RESET_WDOG, CLK_WDOG_REG),
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RESET_DESC(RESET_SID, CLK_SID_REG),
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RESET_DESC(RESET_GTC, CLK_GTC_REG),
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RESET_DESC(RESET_GPIO, CLK_GPIO_REG),
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RESET_DESC(RESET_UART0, CLK_UART0_REG),
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RESET_DESC(RESET_UART1, CLK_UART1_REG),
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RESET_DESC(RESET_UART2, CLK_UART2_REG),
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RESET_DESC(RESET_UART3, CLK_UART3_REG),
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RESET_DESC(RESET_UART4, CLK_UART4_REG),
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RESET_DESC(RESET_UART5, CLK_UART5_REG),
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RESET_DESC(RESET_UART6, CLK_UART6_REG),
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RESET_DESC(RESET_UART7, CLK_UART7_REG),
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RESET_DESC(RESET_I2C0, CLK_I2C0_REG),
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RESET_DESC(RESET_I2C1, CLK_I2C1_REG),
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RESET_DESC(RESET_I2C2, CLK_I2C2_REG),
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RESET_DESC(RESET_I2C3, CLK_I2C3_REG),
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RESET_DESC(RESET_CAN0, CLK_CAN0_REG),
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RESET_DESC(RESET_CAN1, CLK_CAN1_REG),
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RESET_DESC(RESET_PWM, CLK_PWM_REG),
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RESET_DESC(RESET_ADCIM, CLK_ADCIM_REG),
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RESET_DESC(RESET_GPAI, CLK_GPAI_REG),
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RESET_DESC(RESET_RTP, CLK_RTP_REG),
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RESET_DESC(RESET_TSEN, CLK_TSEN_REG),
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RESET_DESC(RESET_CIR, CLK_CIR_REG)
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};
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static int aic_reset_probe(struct udevice *dev)
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{
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struct artinchip_reset_priv *priv = dev_get_priv(dev);
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct aic_reset_plat *plat = dev_get_plat(dev);
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struct dtd_artinchip_aic_reset_v1_0 *dtplat = &plat->dtplat;
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priv->base = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
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#else
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priv->base = dev_read_addr_ptr(dev);
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#endif
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priv->count = ARRAY_SIZE(rest_info);
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priv->max_id = RESET_NUMBER;
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priv->rests = rest_info;
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return 0;
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}
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static const struct udevice_id aic_clk_ids[] = {
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{ .compatible = "artinchip,aic-reset-v1.0", },
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{ .compatible = "artinchip,aic-reset-v1.3", },
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{ }
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};
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static struct reset_ops aic_reset_ops = {
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.request = artinchip_reset_request,
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.rfree = artinchip_reset_free,
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.rst_assert = artinchip_reset_assert,
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.rst_deassert = artinchip_reset_deassert,
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};
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U_BOOT_DRIVER(aic_reset_v1_0) = {
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.name = "artinchip_aic_reset_v1_0",
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.id = UCLASS_RESET,
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.of_match = aic_clk_ids,
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.ops = &aic_reset_ops,
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.probe = aic_reset_probe,
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.priv_auto = sizeof(struct artinchip_reset_priv),
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.plat_auto = sizeof(struct aic_reset_plat),
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};
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//U_BOOT_DRIVER(aic_reset_v1_3) = {
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// .name = "artinchip_aic_reset_v1_3",
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// .id = UCLASS_RESET,
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// .of_match = aic_clk_ids,
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// .ops = &aic_reset_ops,
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// .probe = aic_reset_probe,
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// .priv_auto = sizeof(struct artinchip_reset_priv),
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// .plat_auto = sizeof(struct aic_reset_plat),
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//};
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