423 lines
13 KiB
C
423 lines
13 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2021, ArtInChip Technology Co., Ltd
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*/
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#ifndef __AIC_UDC_H
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#define __AIC_UDC_H
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#include <linux/errno.h>
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#include <linux/sizes.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <linux/list.h>
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#include <linux/bitops.h>
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#include <dm/ofnode.h>
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#define PHY0_SLEEP (1 << 5)
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#define AIC_MAX_HW_ENDPOINTS 16
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#define DIS_EP_TIMOUT 100
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#define EP0_RW_WAIT_COUNT 100000
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struct aic_plat_udc_data {
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void *priv;
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ofnode phy_of_node;
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int (*phy_control)(int on);
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uintptr_t regs_phy;
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uintptr_t regs_udc;
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unsigned int usb_phy_ctrl;
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unsigned int usb_flags;
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unsigned int usb_gusbcfg;
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unsigned int rx_fifo_sz;
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unsigned int np_tx_fifo_sz;
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unsigned int tx_fifo_sz;
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unsigned int tx_fifo_sz_array[AIC_MAX_HW_ENDPOINTS];
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unsigned char tx_fifo_sz_nb;
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bool force_b_session_valid;
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bool force_vbus_detection;
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bool activate_stm_id_vb_detection;
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};
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int aic_udc_probe(struct aic_plat_udc_data *pdata);
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/*-------------------------------------------------------------------------*/
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/* DMA bounce buffer size, 16K is enough even for mass storage */
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#define DMA_BUFFER_SIZE (16 * SZ_1K)
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#define EP0_FIFO_SIZE 64
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#define EP_FIFO_SIZE 512
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#define EP_FIFO_SIZE2 1024
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/* ep0-control, ep1in-bulk, ep2out-bulk, ep3in-int */
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#ifdef CONFIG_AIC_USB_UDC_V10
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#define AIC_MAX_ENDPOINTS 4
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#else
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#define AIC_MAX_ENDPOINTS 16
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#endif
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#define WAIT_FOR_SETUP 0
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#define DATA_STATE_XMIT 1
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#define DATA_STATE_NEED_ZLP 2
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#define WAIT_FOR_OUT_STATUS 3
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#define DATA_STATE_RECV 4
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#define WAIT_FOR_COMPLETE 5
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#define WAIT_FOR_OUT_COMPLETE 6
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#define WAIT_FOR_IN_COMPLETE 7
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#define WAIT_FOR_NULL_COMPLETE 8
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#define TEST_J_SEL 0x1
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#define TEST_K_SEL 0x2
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#define TEST_SE0_NAK_SEL 0x3
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#define TEST_PACKET_SEL 0x4
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#define TEST_FORCE_ENABLE_SEL 0x5
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/* ************************************************************************* */
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/* IO
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*/
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enum ep_type {
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ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
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};
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struct aic_ep {
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struct usb_ep ep;
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struct aic_udc *dev;
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const struct usb_endpoint_descriptor *desc;
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struct list_head queue;
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unsigned long pio_irqs;
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int len;
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void *dma_buf;
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u8 stopped;
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u8 bEndpointAddress;
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u8 bmAttributes;
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enum ep_type ep_type;
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int fifo_num;
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};
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struct aic_request {
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struct usb_request req;
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struct list_head queue;
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void *saved_req_buf;
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};
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struct aic_udc {
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struct usb_gadget gadget;
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struct usb_gadget_driver *driver;
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struct aic_plat_udc_data *pdata;
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int ep0state;
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struct aic_ep ep[AIC_MAX_ENDPOINTS];
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unsigned char usb_address;
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unsigned req_pending:1, req_std:1;
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u32 tx_fifo_map;
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};
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#define ep_is_in(EP) (((EP)->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN)
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#define ep_index(EP) ((EP)->bEndpointAddress & 0xF)
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#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
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void udc_phy_init(struct aic_udc *dev);
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void udc_phy_off(struct aic_udc *dev);
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struct ep_fifo {
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u32 fifo;
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u8 res[4092];
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};
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struct aic_udc_reg_v10 {
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u32 ahbbasic; /* 0x0000: AHBBASIC */
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u32 usbdevinit; /* 0x0004: USBDEVINIT */
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u32 usbphyif; /* 0x0008: USBPHYIF */
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u32 usbulpiphy; /* 0x000C: USBULPIPHY */
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u32 usbintsts; /* 0x0010: USBINTSTS */
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u32 usbintmsk; /* 0x0014: USBINTMSK */
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u32 rxfifosiz; /* 0x0018: RXFIFOSIZ */
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u32 rxfifosts; /* 0x001C: RXFIFOSTS */
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u32 nptxfifosiz; /* 0x0020: NPTXFIFOSIZ */
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u32 nptxfifosts; /* 0x0024: NPTXFIFOSTS */
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u32 txfifosiz[2]; /* 0x0028 - 0x002C: TXFIFOSIZ() */
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u32 rxfifosts_dbg; /* 0x0030: RXFIFOSTS_DBG */
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u8 res0[0x1cc];
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u32 usbdevconf; /* 0x0200: USBDEVCONF */
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u32 usbdevfunc; /* 0x0204: USBDEVFUNC */
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u32 usblinests; /* 0x0208: USBLINESTS */
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u32 inepintmsk; /* 0x020C: INEPINTMSK */
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u32 outepintmsk; /* 0x0210: OUTEPINTMSK */
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u32 usbepint; /* 0x0214: USBEPINT */
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u32 usbepintmsk; /* 0x0218: USBEPINTMSK */
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u8 res1[4];
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u32 inepcfg[5]; /* 0x0220 - 0x0230: INEPCFG() */
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u8 res2[0xc];
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u32 outepcfg[5]; /* 0x0240 - 0x0250: OUTEPCFG() */
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u8 res3[0xc];
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u32 inepint[5]; /* 0x0260 - 0x0270: INEPINT() */
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u8 res4[0xc];
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u32 outepint[5]; /* 0x0280 - 0x0290: OUTEPINT() */
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u8 res5[0xc];
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u32 ineptsfsiz[5]; /* 0x02A0 - 0x02B0: INEPTSFSIZ() */
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u8 res6[0xc];
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u32 outeptsfsiz[5]; /* 0x02C0 - 0x02D0: OUTEPTSFSIZ() */
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u8 res7[0x2c];
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u32 inepdmaaddr[5]; /* 0x0300 - 0x0310: INEPDMAADDR() */
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u8 res8[0xc];
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u32 outepdmaaddr[5]; /* 0x0320 - 0x0330: OUTEPDMAADDR() */
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u8 res9[0xc];
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u32 ineptxsts[5]; /* 0x0340 - 0x0350: INEPTXSTS() */
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u8 res10[0xc];
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u32 dtknqr1; /* 0x0360: DTKNQR1 */
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u32 dtknqr2; /* 0x0364: DTKNQR2 */
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u32 dtknqr3; /* 0x0368: DTKNQR3 */
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u32 dtknqr4; /* 0x036C: DTKNQR4 */
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};
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struct aic_udc_reg_v20 {
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u32 ahbbasic; /* 0x0000: AHBBASIC */
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u32 usbdevinit; /* 0x0004: USBDEVINIT */
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u32 usbphyif; /* 0x0008: USBPHYIF */
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u32 usbulpiphy; /* 0x000C: USBULPIPHY */
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u32 usbintsts; /* 0x0010: USBINTSTS */
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u32 usbintmsk; /* 0x0014: USBINTMSK */
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u32 rxfifosiz; /* 0x0018: RXFIFOSIZ */
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u32 rxfifosts; /* 0x001C: RXFIFOSTS */
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u32 ietxfifosiz; /* 0x0020: IETXFIFO0_SIZ */
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u32 thr_ctl; /* 0x0024: THR_CTL */
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u8 res0[0x8];
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u32 rxfifosts_dbg; /* 0x0030: RXFIFOSTS_DBG */
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u8 res1[0xc];
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u32 phyclkctl; /* 0x0040: RXFIFOSTS_DBG */
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u8 res2[0x1c];
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u32 txfifosiz[AIC_MAX_ENDPOINTS - 1]; /* 0x0060 - 0x0098: TXFIFOSIZ() */
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u8 res3[0x164];
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u32 usbdevconf; /* 0x0200: USBDEVCONF */
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u32 usbdevfunc; /* 0x0204: USBDEVFUNC */
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u32 usblinests; /* 0x0208: USBLINESTS */
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u32 inepintmsk; /* 0x020C: INEPINTMSK */
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u32 outepintmsk; /* 0x0210: OUTEPINTMSK */
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u32 usbepint; /* 0x0214: USBEPINT */
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u32 usbepintmsk; /* 0x0218: USBEPINTMSK */
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u8 res4[0x4];
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u32 inepcfg[AIC_MAX_ENDPOINTS]; /* 0x0220 - 0x0260: INEPCFG() */
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u32 outepcfg[AIC_MAX_ENDPOINTS]; /* 0x0260 - 0x02A0: OUTEPCFG() */
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u32 inepint[AIC_MAX_ENDPOINTS]; /* 0x02A0 - 0x02E0: INEPINT() */
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u32 outepint[AIC_MAX_ENDPOINTS]; /* 0x02E0 - 0x0320: OUTEPINT() */
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u32 ineptsfsiz[AIC_MAX_ENDPOINTS]; /* 0x0320 - 0x0360: INEPTSFSIZ() */
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u32 outeptsfsiz[AIC_MAX_ENDPOINTS]; /* 0x0360 - 0x03A0: OUTEPTSFSIZ() */
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u32 inepdmaaddr[AIC_MAX_ENDPOINTS]; /* 0x03A0 - 0x03E0: INEPDMAADDR() */
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u32 outepdmaaddr[AIC_MAX_ENDPOINTS]; /* 0x03E0 - 0x0420: OUTEPDMAADDR() */
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u32 ineptxsts[AIC_MAX_ENDPOINTS]; /* 0x0420 - 0x0460: INEPTXSTS() */
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u32 dtknqr1; /* 0x0360: DTKNQR1 */
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u32 dtknqr2; /* 0x0364: DTKNQR2 */
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u32 dtknqr3; /* 0x0368: DTKNQR3 */
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u32 dtknqr4; /* 0x036C: DTKNQR4 */
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};
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/*===================================================================== */
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/*definitions related to CSR setting */
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/* AHBBASIC */
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#define AHBBASIC_NOTI_ALL_DMA_WRIT BIT(8)
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#define AHBBASIC_REM_MEM_SUPP BIT(7)
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#define AHBBASIC_INV_DESC_ENDIANNESS BIT(6)
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#define AHBBASIC_AHB_SINGLE BIT(5)
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#define AHBBASIC_TXENDDELAY BIT(3)
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#define AHBBASIC_AHBIDLE BIT(2)
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#define AHBBASIC_DMAREQ BIT(1)
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/* USBDEVINIT */
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#define USBDEVINIT_HBSTLEN_MASK (0xf << 12)
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#define USBDEVINIT_HBSTLEN_SHIFT 12
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#define USBDEVINIT_HBSTLEN_SINGLE 0
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#define USBDEVINIT_HBSTLEN_INCR 1
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#define USBDEVINIT_HBSTLEN_INCR4 3
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#define USBDEVINIT_HBSTLEN_INCR8 5
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#define USBDEVINIT_HBSTLEN_INCR16 7
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#define USBDEVINIT_DMA_EN BIT(11)
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#define USBDEVINIT_NP_TXF_EMP_LVL BIT(10)
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#define USBDEVINIT_GLBL_INTR_EN BIT(9)
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#define USBDEVINIT_CTRL_MASK (USBDEVINIT_NP_TXF_EMP_LVL | \
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USBDEVINIT_DMA_EN | \
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USBDEVINIT_GLBL_INTR_EN)
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#define USBDEVINIT_IN_TKNQ_FLSH BIT(8)
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#define USBDEVINIT_TXFNUM_MASK (0x1f << 3)
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#define USBDEVINIT_TXFNUM_SHIFT 3
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#define USBDEVINIT_TXFNUM_LIMIT 0x1f
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#define USBDEVINIT_TXFNUM(_x) ((_x) << 3)
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#define USBDEVINIT_TXFFLSH BIT(2)
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#define USBDEVINIT_RXFFLSH BIT(1)
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#define USBDEVINIT_CSFTRST BIT(0)
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/* USBPHYIF */
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#define USBPHYIF_ULPI_CLK_SUSP_M BIT(19)
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#define USBPHYIF_ULPI_AUTO_RES BIT(18)
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#define USBPHYIF_PHY_LP_CLK_SEL BIT(15)
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#define USBPHYIF_USBTRDTIM_MASK (0xf << 10)
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#define USBPHYIF_USBTRDTIM_SHIFT 10
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#define USBPHYIF_DDRSEL BIT(7)
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#define USBPHYIF_ULPI_UTMI_SEL BIT(4)
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#define USBPHYIF_PHYIF16 BIT(3)
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#define USBPHYIF_PHYIF8 (0 << 3)
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#define USBPHYIF_TOUTCAL_MASK (0x7 << 0)
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#define USBPHYIF_TOUTCAL_SHIFT 0
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#define USBPHYIF_TOUTCAL_LIMIT 0x7
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#define USBPHYIF_TOUTCAL(_x) ((_x) << 0)
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/* USBINTSTS/USBINTMSK interrupt register */
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#define INT_RESUME (1u << 31)
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#define INT_OUT_EP (0x1 << 19)
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#define INT_IN_EP (0x1 << 18)
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#define INT_ENUMDONE (0x1 << 13)
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#define INT_RESET (0x1 << 12)
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#define INT_SUSPEND (0x1 << 11)
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#define INT_EARLY_SUSPEND (0x1 << 10)
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#define INT_NP_TX_FIFO_EMPTY (0x1 << 5)
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#define INT_RX_FIFO_NOT_EMPTY (0x1 << 4)
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#define INT_SOF (0x1 << 3)
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#define INT_GOUTNAKEFF (0x01 << 7)
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#define INT_GINNAKEFF (0x01 << 6)
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#define FULL_SPEED_CONTROL_PKT_SIZE 8
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#define FULL_SPEED_BULK_PKT_SIZE 64
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#define HIGH_SPEED_CONTROL_PKT_SIZE 64
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#define HIGH_SPEED_BULK_PKT_SIZE 512
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#define RX_FIFO_SIZE (1024)
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#define NPTX_FIFO_SIZE (1024)
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#define PTX_FIFO_SIZE (384)
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/* fifo size configure */
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#define EPS_NUM 5
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#ifdef CONFIG_AIC_USB_UDC_V10
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#define TX_FIFO_NUM 3 /* Non-periodic:1 Periodic:2 */
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#else
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#define TX_FIFO_NUM 16
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#endif
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#define TOTAL_FIFO_SIZE 0x3f6
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#define AIC_RX_FIFO_SIZE 0x119
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#define AIC_NP_TX_FIFO_SIZE 0x100
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#define AIC_PERIOD_TX_FIFO1_SIZE 0x100
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#define AIC_PERIOD_TX_FIFO2_SIZE 0xDD
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#define DEPCTL_TXFNUM_0 (0x0 << 22)
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#define DEPCTL_TXFNUM_1 (0x1 << 22)
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#define DEPCTL_TXFNUM_2 (0x2 << 22)
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#define DEPCTL_TXFNUM_3 (0x3 << 22)
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#define DEPCTL_TXFNUM_4 (0x4 << 22)
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/* Enumeration speed */
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#define USB_HIGH_30_60MHZ (0x0 << 1)
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#define USB_FULL_30_60MHZ (0x1 << 1)
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#define USB_LOW_6MHZ (0x2 << 1)
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#define USB_FULL_48MHZ (0x3 << 1)
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/* RXFIFOSTS */
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#define OUT_PKT_RECEIVED (0x2 << 17)
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#define OUT_TRANSFER_COMPLELTED (0x3 << 17)
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#define SETUP_TRANSACTION_COMPLETED (0x4 << 17)
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#define SETUP_PKT_RECEIVED (0x6 << 17)
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#define GLOBAL_OUT_NAK (0x1 << 17)
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/* USBDEVFUNC */
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#define NORMAL_OPERATION (0x1 << 0)
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#define SOFT_DISCONNECT (0x1 << 1)
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#define USBDEVFUNC_SERVICE_INTERVAL_SUPPORTED BIT(19)
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#define USBDEVFUNC_PWRONPRGDONE BIT(11)
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#define USBDEVFUNC_CGOUTNAK BIT(10)
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#define USBDEVFUNC_SGOUTNAK BIT(9)
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#define USBDEVFUNC_CGNPINNAK BIT(8)
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#define USBDEVFUNC_SGNPINNAK BIT(7)
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#define USBDEVFUNC_TSTCTL_MASK (0x7 << 4)
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#define USBDEVFUNC_TSTCTL_SHIFT 4
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#define USBDEVFUNC_GOUTNAKSTS BIT(3)
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#define USBDEVFUNC_GNPINNAKSTS BIT(2)
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#define USBDEVFUNC_SFTDISCON BIT(1)
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#define USBDEVFUNC_RMTWKUPSIG BIT(0)
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/* USBEPINT endpoint interrupt register */
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#define DAINT_OUT_BIT (16)
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#define DAINT_MASK (0xFFFF)
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/* INEPCFG()/OUTEPCFG()
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* devicecontrol IN/OUT endpoint 0 control register
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*/
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#define DEPCTL_EPENA (1u << 31)
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#define DEPCTL_EPDIS (0x1 << 30)
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#define DEPCTL_SETD1PID (0x1 << 29)
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#define DEPCTL_SETD0PID (0x1 << 28)
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#define DEPCTL_SNAK (0x1 << 27)
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#define DEPCTL_CNAK (0x1 << 26)
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#define DEPCTL_STALL (0x1 << 21)
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#define DEPCTL_TYPE_BIT (18)
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#define DEPCTL_TYPE_MASK (0x3 << 18)
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#define DEPCTL_CTRL_TYPE (0x0 << 18)
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#define DEPCTL_ISO_TYPE (0x1 << 18)
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#define DEPCTL_BULK_TYPE (0x2 << 18)
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#define DEPCTL_INTR_TYPE (0x3 << 18)
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#define DEPCTL_USBACTEP (0x1 << 15)
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#define DEPCTL_NEXT_EP_BIT (11)
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#define DEPCTL_MPS_BIT (0)
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#define DEPCTL_MPS_MASK (0x7FF)
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#define DEPCTL0_MPS_64 (0x0 << 0)
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#define DEPCTL0_MPS_32 (0x1 << 0)
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#define DEPCTL0_MPS_16 (0x2 << 0)
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#define DEPCTL0_MPS_8 (0x3 << 0)
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#define DEPCTL_MPS_BULK_512 (512 << 0)
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#define DEPCTL_MPS_INT_MPS_16 (16 << 0)
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#define DIEPCTL0_NEXT_EP_BIT (11)
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/* INEPINT/OUTEPINT device IN/OUT endpoint interrupt register */
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#define BACK2BACK_SETUP_RECEIVED (0x1 << 6)
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#define INTKNEPMIS (0x1 << 5)
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#define INTKN_TXFEMP (0x1 << 4)
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#define NON_ISO_IN_EP_TIMEOUT (0x1 << 3)
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#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1 << 3)
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#define AHB_ERROR (0x1 << 2)
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#define EPDISBLD (0x1 << 1)
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#define TRANSFER_DONE (0x1 << 0)
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/* Device Configuration Register DCFG */
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#define DEV_SPEED_HIGH_SPEED_20 (0x0 << 0)
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#define DEV_SPEED_FULL_SPEED_20 (0x1 << 0)
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#define DEV_SPEED_LOW_SPEED_11 (0x2 << 0)
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#define DEV_SPEED_FULL_SPEED_11 (0x3 << 0)
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#define EP_MISS_CNT(x) (x << 18)
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#define DEVICE_ADDRESS(x) (x << 4)
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/* Masks definitions */
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#define GINTMSK_INIT (INT_OUT_EP | INT_IN_EP | INT_RESUME | INT_ENUMDONE\
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| INT_RESET | INT_SUSPEND)
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#define DOEPMSK_INIT (CTRL_OUT_EP_SETUP_PHASE_DONE |\
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AHB_ERROR | TRANSFER_DONE)
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#define DIEPMSK_INIT (NON_ISO_IN_EP_TIMEOUT | AHB_ERROR | TRANSFER_DONE \
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| INTKNEPMIS)
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#define GAHBCFG_INIT (USBDEVINIT_DMA_EN | USBDEVINIT_GLBL_INTR_EN\
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| (USBDEVINIT_HBSTLEN_INCR4 <<\
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USBDEVINIT_HBSTLEN_SHIFT))
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/* Device Endpoint X Transfer Size Register INEPTSFSIZ() */
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#define DIEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DIEPT_SIZ_XFER_SIZE(x) (x << 0)
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/* Device OUT Endpoint X Transfer Size Register OUTEPTSFSIZ() */
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#define DOEPT_SIZ_PKT_CNT(x) (x << 19)
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#define DOEPT_SIZ_XFER_SIZE(x) (x << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP0 (0x7F << 0)
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#define DOEPT_SIZ_XFER_SIZE_MAX_EP (0x7FFF << 0)
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/* Device Endpoint-N Control Register INEPCFG()/OUTEPCFG() */
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#define DIEPCTL_TX_FIFO_NUM(x) (x << 22)
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#define DIEPCTL_TX_FIFO_NUM_MASK (~DIEPCTL_TX_FIFO_NUM(0xF))
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/* Device ALL Endpoints Interrupt Register (USBEPINT) */
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#define DAINT_IN_EP_INT(x) (x << 0)
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#define DAINT_OUT_EP_INT(x) (x << 16)
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#endif
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