506 lines
13 KiB
C
506 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2022 ArtInChip Technology Co.,Ltd
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* Author: Hao Xiong <hao.xiong@artinchip.com>
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*/
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#ifndef _ARTINCHIP_CRYPTO_H_
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#define _ARTINCHIP_CRYPTO_H_
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#define RSA2048_SIGN_LEN 256
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#define RSA2048_KEY_LEN 256
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#define SHA256_BYTE_LEN 32
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#define MD5_BYTE_LEN 16
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#define AES128_KEY_LEN 16
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#define AES192_KEY_LEN 24
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#define AES256_KEY_LEN 32
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#define DES64_KEY_LEN 8
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#define MD5_DIGEST_SIZE 16
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#define SHA1_DIGEST_SIZE 20
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#define SHA224_DIGEST_SIZE 28
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#define SHA256_DIGEST_SIZE 32
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#define SHA384_DIGEST_SIZE 48
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#define SHA512_DIGEST_SIZE 64
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#define MD5_BLOCK_SIZE 16
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#define SHA1_BLOCK_SIZE 64
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#define SHA224_BLOCK_SIZE 64
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#define SHA256_BLOCK_SIZE 64
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#define SHA384_BLOCK_SIZE 128
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#define SHA512_BLOCK_SIZE 128
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#define MD5_CE_OUT_LEN 16
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#define SHA1_CE_OUT_LEN 20
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#define SHA224_CE_OUT_LEN 32
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#define SHA256_CE_OUT_LEN 32
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#define SHA384_CE_OUT_LEN 64
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#define SHA512_CE_OUT_LEN 64
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#define MD5_H0 0x67452301UL
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#define MD5_H1 0xefcdab89UL
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#define MD5_H2 0x98badcfeUL
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#define MD5_H3 0x10325476UL
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#define BE_SHA1_H0 0x01234567UL
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#define BE_SHA1_H1 0x89abcdefUL
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#define BE_SHA1_H2 0xfedcba98UL
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#define BE_SHA1_H3 0x76543210UL
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#define BE_SHA1_H4 0xf0e1d2c3UL
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#define BE_SHA224_H0 0xd89e05c1UL
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#define BE_SHA224_H1 0x07d57c36UL
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#define BE_SHA224_H2 0x17dd7030UL
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#define BE_SHA224_H3 0x39590ef7UL
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#define BE_SHA224_H4 0x310bc0ffUL
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#define BE_SHA224_H5 0x11155868UL
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#define BE_SHA224_H6 0xa78ff964UL
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#define BE_SHA224_H7 0xa44ffabeUL
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#define BE_SHA256_H0 0x67e6096aUL
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#define BE_SHA256_H1 0x85ae67bbUL
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#define BE_SHA256_H2 0x72f36e3cUL
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#define BE_SHA256_H3 0x3af54fa5UL
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#define BE_SHA256_H4 0x7f520e51UL
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#define BE_SHA256_H5 0x8c68059bUL
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#define BE_SHA256_H6 0xabd9831fUL
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#define BE_SHA256_H7 0x19cde05bUL
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#define BE_SHA384_H0 0xd89e05c15d9dbbcbULL
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#define BE_SHA384_H1 0x07d57c362a299a62ULL
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#define BE_SHA384_H2 0x17dd70305a015991ULL
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#define BE_SHA384_H3 0x39590ef7d8ec2f15ULL
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#define BE_SHA384_H4 0x310bc0ff67263367ULL
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#define BE_SHA384_H5 0x11155868874ab48eULL
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#define BE_SHA384_H6 0xa78ff9640d2e0cdbULL
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#define BE_SHA384_H7 0xa44ffabe1d48b547ULL
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#define BE_SHA512_H0 0x08c9bcf367e6096aULL
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#define BE_SHA512_H1 0x3ba7ca8485ae67bbULL
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#define BE_SHA512_H2 0x2bf894fe72f36e3cULL
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#define BE_SHA512_H3 0xf1361d5f3af54fa5ULL
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#define BE_SHA512_H4 0xd182e6ad7f520e51ULL
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#define BE_SHA512_H5 0x1f6c3e2b8c68059bULL
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#define BE_SHA512_H6 0x6bbd41fbabd9831fULL
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#define BE_SHA512_H7 0x79217e1319cde05bULL
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#define ALG_UNIT_SYMM (0)
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#define ALG_UNIT_HASH (1)
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#define ALG_UNIT_ASYM (2)
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#define ALG_DIR_ENCRYPT (0)
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#define ALG_DIR_DECRYPT (1)
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#define ALG_AES_ECB (0x00)
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#define ALG_AES_CBC (0x01)
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#define ALG_AES_CTR (0x02)
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#define ALG_AES_XTS (0x03)
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#define ALG_AES_CTS (0x04)
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#define ALG_DES_ECB (0x10)
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#define ALG_DES_CBC (0x11)
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#define ALG_TDES_ECB (0x20)
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#define ALG_TDES_CBC (0x21)
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#define ALG_RSA (0x30)
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#define ALG_SHA1 (0x40)
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#define ALG_SHA224 (0x41)
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#define ALG_SHA256 (0x42)
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#define ALG_SHA384 (0x43)
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#define ALG_SHA512 (0x44)
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#define ALG_MD5 (0x45)
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#define ALG_HMAC_SHA1 (0x46)
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#define ALG_HMAC_SHA256 (0x47)
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#define ALG_TRNG (0x50)
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#define CTR_BIT_WIDTH_16 (0)
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#define CTR_BIT_WIDTH_32 (1)
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#define CTR_BIT_WIDTH_64 (2)
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#define CTR_BIT_WIDTH_128 (3)
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#define KEY_SIZE_64 (0x00)
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#define KEY_SIZE_128 (0x01)
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#define KEY_SIZE_192 (0x02)
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#define KEY_SIZE_256 (0x03)
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#define KEY_SIZE_512 (0x04)
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#define KEY_SIZE_1024 (0x05)
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#define KEY_SIZE_2048 (0x06)
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/*
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* Key source
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* - User input key(RAM or Secure SRAM)
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* - eFuse key
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*/
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#define CE_KEY_SRC_USER (0)
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#define CE_KEY_SRC_SSK (1)
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#define CE_KEY_SRC_HUK (2)
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#define CE_KEY_SRC_PNK (3)
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#define CE_KEY_SRC_PSK0 (4)
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#define CE_KEY_SRC_PSK1 (5)
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#define CE_KEY_SRC_PSK2 (6)
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#define CE_KEY_SRC_PSK3 (7)
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#define AES_BLOCK_SIZE 16
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#define AES_MIN_KEY_LEN 16
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#define AES_MAX_KEY_LEN 32
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#define CE_WORK_BUF_LEN 1024
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/*----- RSA Control Codes: Mode Parameters: Key Bits -----*/
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typedef enum rsa_key_bits {
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RSA_KEY_BITS_192 = 0, // 192 Key bits
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RSA_KEY_BITS_256, // 256 Key bits
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RSA_KEY_BITS_512, // 512 Key bits
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RSA_KEY_BITS_1024, // 1024 Key bits
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RSA_KEY_BITS_2048, // 2048 Key bits
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RSA_KEY_BITS_3072, // 3072 Key bits
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RSA_KEY_BITS_4096 // 4096 Key bits
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} rsa_key_bits_t;
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typedef enum rsa_padding_type {
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RSA_PADDING_MODE_NO = 0, // RSA NO Padding Mode
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RSA_PADDING_MODE_PKCS1, // RSA PKCS1 Padding Mode
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RSA_PADDING_MODE_PKCS1_OAEP, // RSA PKCS1 OAEP Padding Mode
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RSA_PADDING_MODE_SSLV23, // RSA SSLV23 Padding Mode
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RSA_PADDING_MODE_X931, // RSA X931 Padding Mode
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RSA_PADDING_MODE_PSS // RSA PSS Padding Mode
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} rsa_padding_type_t;
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typedef enum rsa_hash_type {
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RSA_HASH_TYPE_MD5 = 0,
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RSA_HASH_TYPE_SHA1,
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RSA_HASH_TYPE_SHA224,
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RSA_HASH_TYPE_SHA256,
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RSA_HASH_TYPE_SHA384,
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RSA_HASH_TYPE_SHA512
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} rsa_hash_type_t;
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typedef struct rsa_context {
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void *n; // Pointer to the public modulus
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void *e; // Pointer to the public exponent
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void *d; // Pointer to the private exponent
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rsa_key_bits_t key_bits; // RSA KEY BITS
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rsa_padding_type_t padding_type;// RSA PADDING TYPE
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} rsa_context_t;
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/** brief RSA State **/
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typedef struct rsa_state {
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u8 busy : 1; // Calculate busy flag
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u8 error : 1; // Calculate error flag
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} rsa_state_t;
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typedef struct rsa_middle {
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u32 pout[64];
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u8 *pouts;
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u32 *pout_size;
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u32 u32keywords;
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u8 *pdst;
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u32 u32padding;
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u32 u32dst_words;
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u32 u32type;
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u32 rsa_state;
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} rsa_middle_t;
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/****** RSA Event *****/
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typedef enum rsa_event {
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RSA_EVENT_COMPLETE = 0, // rsa event completed
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RSA_EVENT_VERIFY_SUCCESS,
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RSA_EVENT_VERIFY_FAILED,
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RSA_EVENT_ERROR, // error event
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} rsa_event_t;
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/****** SHA mode ******/
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typedef enum sha_mode {
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SHA_MODE_1 = 1U, // SHA_1 mode
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SHA_MODE_256, // SHA_256 mode
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SHA_MODE_224, // SHA_224 mode
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SHA_MODE_512, // SHA_512 mode
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SHA_MODE_384, // SHA_384 mode
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SHA_MODE_512_256, // SHA_512_256 mode
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SHA_MODE_512_224 // SHA_512_224 mode
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} sha_mode_t;
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/****** SHA State ******/
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typedef struct sha_state {
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u32 busy : 1; // Calculate busy flag
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u32 error : 1; // Calculate error flag
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} sha_state_t;
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typedef struct sha_context {
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sha_mode_t mode; // SHA mode
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u32 total[2]; // Number of bytes processed
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u32 state[16]; // Intermediate digest state
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u8 buffer[128]; // Data block being processed
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} sha_context_t;
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/****** SHA Event ******/
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typedef enum sha_event {
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SHA_EVENT_COMPLETE = 0U, // Calculate completed
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SHA_EVENT_ERROR // Calculate error
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} sha_event_t;
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/*
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* all buffer address should be aligned to 8 bytes
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*/
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struct aes_priv {
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u8 align_buf[CE_WORK_BUF_LEN];
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u8 key[AES_MAX_KEY_LEN];
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u8 iv_in[AES_BLOCK_SIZE];
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u8 iv_out[AES_BLOCK_SIZE];
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u8 key_len;
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};
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#define SHA_MAX_OUTPUT_LEN 64
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struct sha_priv {
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u8 align_buf[CE_WORK_BUF_LEN];
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u8 digest[SHA_MAX_OUTPUT_LEN];
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u32 alg_tag;
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u32 out_len;
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u32 digest_len;
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};
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struct rsa_priv {
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u8 align_buf[CE_WORK_BUF_LEN];
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};
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struct crypto_priv {
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struct aes_priv *aes;
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struct rsa_priv *rsa;
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struct sha_priv *sha;
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};
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struct aes_ecb_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 direction : 1; /* bit[8] */
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u32 r0 : 7; /* bit[15:9] */
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u32 key_src : 4; /* bit[19:16] */
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u32 key_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 key_addr;
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u8 r2[28]; /* Pad to 36 bytes */
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};
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struct aes_cbc_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 direction : 1; /* bit[8] */
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u32 r0 : 7; /* bit[15:9] */
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u32 key_src : 4; /* bit[19:16] */
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u32 key_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 key_addr;
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u32 iv_addr;
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u8 r2[24]; /* Pad to 36 bytes */
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};
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/*
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* CTS-CBC-CS3(Kerberos)
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*/
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struct aes_cts_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 direction : 1; /* bit[8] */
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u32 r0 : 7; /* bit[15:9] */
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u32 key_src : 4; /* bit[19:16] */
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u32 key_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 key_addr;
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u32 iv_addr;
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u8 r2[24]; /* Pad to 36 bytes */
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};
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struct aes_ctr_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 direction : 1; /* bit[8] */
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u32 r0 : 7; /* bit[15:9] */
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u32 key_src : 4; /* bit[19:16] */
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u32 key_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 key_addr;
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u32 ctr_in_addr;
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u32 ctr_out_addr;
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u8 r2[20]; /* Pad to 36 bytes */
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};
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struct aes_xts_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 direction : 1; /* bit[8] */
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u32 r0 : 7; /* bit[15:9] */
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u32 key_src : 4; /* bit[19:16] */
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u32 key_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 key_addr;
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u32 tweak_addr;
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u8 r2[24]; /* Pad to 36 bytes */
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};
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struct des_ecb_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 direction : 1; /* bit[8] */
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u32 r0 : 7; /* bit[15:9] */
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u32 key_src : 4; /* bit[19:16] */
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u32 key_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 key_addr;
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u8 r2[28]; /* Pad to 36 bytes */
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};
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struct des_cbc_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 direction : 1; /* bit[8] */
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u32 r0 : 7; /* bit[15:9] */
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u32 key_src : 4; /* bit[19:16] */
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u32 key_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 key_addr;
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u32 iv_addr;
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u8 r2[24]; /* Pad to 36 bytes */
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};
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struct rsa_alg_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 r0 : 12;/* bit[19:8] */
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u32 op_siz : 4; /* bit[23:20] */
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u32 r1 : 8; /* bit[31:24] */
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u32 m_addr;
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u32 d_e_addr;
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u8 r2[24]; /* Pad to 36 bytes */
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};
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struct hash_alg_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 r0 : 1; /* bit[8] */
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u32 iv_mode : 1; /* bit[9] */
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u32 r1 : 22;/* bit[31:10] */
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u32 r2;
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u32 iv_addr;
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u8 r3[24]; /* Pad to 36 bytes */
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};
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struct hmac_alg_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 r0 : 1; /* bit[8] */
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u32 iv_mode : 1; /* bit[9] */
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u32 r1 : 22;/* bit[31:10] */
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u32 hmac_key_addr;
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u32 iv_addr;
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u8 r2[24]; /* Pad to 36 bytes */
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};
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struct trng_alg_desc {
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u32 alg_tag : 8; /* bit[7:0] */
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u32 r1 : 24;/* bit[31:8] */
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u8 r2[32]; /* Pad to 36 bytes */
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};
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union alg_desc {
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u8 alg_tag;
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struct aes_ecb_desc aes_ecb;
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struct aes_cbc_desc aes_cbc;
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struct aes_ctr_desc aes_ctr;
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struct aes_cts_desc aes_cts;
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struct aes_xts_desc aes_xts;
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struct des_ecb_desc des_ecb;
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struct des_cbc_desc des_cbc;
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struct rsa_alg_desc rsa;
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struct hash_alg_desc hash;
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struct hmac_alg_desc hmac;
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struct trng_alg_desc trng;
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};
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struct data_desc {
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u32 first_flag : 1; /* bit[0] */
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u32 last_flag : 1; /* bit[1] */
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u32 r1 : 30;/* bit[31:2] */
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u32 total_bytelen;
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u32 in_addr;
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u32 in_len;
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u32 out_addr;
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u32 out_len;
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};
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struct task_desc {
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union alg_desc alg;
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struct data_desc data;
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u32 next;
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};
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/*
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* struct gunzip_ops - Driver model Gunzip operations
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*
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* The uclass interface is implemented by all gunzip devices which
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* use driver model.
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*/
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struct dm_crypto_ops {
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/**
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* Preparing gzip parameters.
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* @dev: the device
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* @dst: Destination for uncompressed data
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* @dstlen: Size of destination buffer
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* @src: Source data to decompress
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* @lenp: Returns length of uncompressed data
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*
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* Return: 0 if OK, -1 on error
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*/
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int (*init)(struct udevice *dev);
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/**
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* Decompress gzipped data.
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* @dev: the device
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*
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* Return: 0 if OK, -1 on error
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*/
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int (*start)(struct udevice *dev, struct task_desc *task);
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/**
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* Decompress gzipped data.
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* @dev: the device
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*
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* Return: 0 if OK, -1 on error
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*/
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int (*poll_finish)(struct udevice *dev, u32 alg_unit);
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/**
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* Decompress gzipped data.
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* @dev: the device
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*
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* Return: 0 if OK, -1 on error
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*/
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void (*pending_clear)(struct udevice *dev, u32 alg_unit);
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/**
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* Decompress gzipped data.
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* @dev: the device
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*
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* Return: 0 if OK, -1 on error
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*/
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int (*get_err)(struct udevice *dev, u32 alg_unit);
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/**
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* Release crypto device
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* @dev: the device
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*
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*/
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void (*release)(struct udevice *dev);
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};
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int crypto_init_device(struct udevice **dev);
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int aes_init(struct udevice *dev);
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void aes_exit(struct udevice *dev);
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int aes_set_encrypt_key(struct udevice *dev, void *key, u32 key_len);
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int aes_set_decrypt_key(struct udevice *dev, void *key, u32 key_len);
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int aes_ecb_encrypt(struct udevice *dev, void *in, void *out, u32 size);
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int aes_ecb_decrypt(struct udevice *dev, void *in, void *out, u32 size);
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int aes_cbc_encrypt(struct udevice *dev, void *in, void *out, u32 size,
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void *iv);
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int aes_cbc_decrypt(struct udevice *dev, void *in, void *out, u32 size,
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void *iv);
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int rsa_init(struct udevice *dev);
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void rsa_exit(struct udevice *dev);
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int rsa_public_encrypt(struct udevice *dev, rsa_context_t *context, void *src,
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u32 src_size, void *out);
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int rsa_private_decrypt(struct udevice *dev, rsa_context_t *context, void *src,
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u32 src_size, void *out, u32 *out_size);
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int rsa_private_encrypt(struct udevice *dev, rsa_context_t *context, void *src,
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u32 src_size, void *out);
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int rsa_public_decrypt(struct udevice *dev, rsa_context_t *context, void *src,
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u32 src_size, void *out, u32 *out_size);
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int sha_init(struct udevice *dev);
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void sha_exit(struct udevice *dev);
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int sha_start(struct udevice *dev, sha_context_t *context, sha_mode_t mode);
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int sha_update(struct udevice *dev, sha_context_t *context, const void *input,
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u32 size, int is_last);
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int sha_finish(struct udevice *dev, sha_context_t *context, void *output,
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u32 *out_size);
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#endif /* _ARTINCHIP_CRYPTO_H_ */
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