710 lines
19 KiB
Plaintext
710 lines
19 KiB
Plaintext
/*
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* Copyright (C) 2020-2022 ArtInChip Technology Co., Ltd.
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/artinchip,aic-cmu.h>
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#include <dt-bindings/reset/artinchip,aic-reset.h>
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#include <dt-bindings/dma/d211-dma.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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chosen {
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opensbi-domains {
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compatible = "opensbi,domain,config";
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device: device {
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compatible = "opensbi,domain,memregion";
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base = <0x0 0x00000000>;
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order = <30>;
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mmio;
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};
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mem0: mem {
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compatible = "opensbi,domain,memregion";
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base = <0x0 0x80000000>;
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order = <30>;
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};
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pmp_domain: pmp_domain {
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compatible = "opensbi,domain,instance";
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possible-harts = <&cpu0>;
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regions = <&device 0x3>, <&mem0 0x7>;
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boot-hart = <&cpu0>;
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system-reset-allowed;
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};
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <10000000>;
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cpu0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64gcxthead";
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mmu-type = "riscv,sv39";
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cpu-icache = "32KB";
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cpu-dcache = "32KB";
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cpu-tlb = "1024 4-ways";
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cpu-cacheline = "64Bytes";
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opensbi-domain = <&pmp_domain>;
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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};
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};
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};
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clocks {
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osc24m: clock-hosc {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24m";
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};
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rc1m: clock-mosc {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <1000000>;
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clock-output-names = "rc1m";
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};
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osc32k: clock-losc {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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clint0: clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>;
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reg = <0x0 0x2000000 0x0 0x10000>;
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clint,has-no-64bit-mmio;
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};
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plic0: interrupt-controller@c000000 {
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#interrupt-cells = <2>;
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compatible = "riscv,plic0";
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interrupt-controller;
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interrupts-extended = <&cpu0_intc 0xffffffff &cpu0_intc 9>;
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reg = <0x0 0xc000000 0x0 0x400000>;
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reg-names = "control";
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riscv,max-priority = <7>;
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riscv,ndev=<159>;
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};
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dma: dma-controller@10000004 {
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compatible = "artinchip,aic-dma-v1.0";
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reg = <0x0 0x20000000 0x0 0x1000>;
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interrupts-extended = <&plic0 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_DMA>;
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resets = <&rst RESET_DMA>;
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#dma-cells = <1>;
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status = "okay";
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};
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crypto: crypto-engine@10020000 {
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compatible = "artinchip,aic-crypto-v1.0";
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reg = <0x0 0x20020000 0x0 0x1000>;
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interrupts-extended = <&plic0 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_CE>;
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resets = <&rst RESET_CE>;
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status = "okay";
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};
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aicudc: udc@10200000 {
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compatible = "artinchip,aic-udc-v1.0";
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reg = <0x0 0x10200000 0x0 0x1000>;
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interrupts-extended = <&plic0 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_USBD>, <&cmu CLK_USB_PHY0>;
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clock-names = "udc_clk";
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resets = <&rst RESET_USBD>, <&rst RESET_USBPHY0>;
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reset-names = "aicudc", "aicudc-ecc";
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status = "okay";
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// phys = <&usbphy0>;
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// phy-names = "usb2-phy";
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};
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usbh0: usb@10210000 {
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compatible = "artinchip,aic-usbh-v1.0";
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reg = <0x0 0x20210000 0x0 0x100>;
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interrupts-extended = <&plic0 35 IRQ_TYPE_LEVEL_HIGH>, <&plic0 4 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_USBH0>;
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clock-names = "usbh";
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resets = <&rst RESET_USBH0>;
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reset-names = "usbh";
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dr_mode = "host";
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// phys = <&usbphy0>;
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// phy-names = "usb2-phy";
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};
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usbh1: usb@10220000 {
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compatible = "artinchip,aic-usbh-v1.0";
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reg = <0x0 0x20220000 0x0 0x100>;
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interrupts-extended = <&plic0 37 IRQ_TYPE_LEVEL_HIGH>,
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<&plic0 38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_USBH1>;
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clock-names = "usbh";
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resets = <&rst RESET_USBH1>, <&rst RESET_USBPHY1>;
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reset-names = "usbh", "usbh-phy";
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dr_mode = "host";
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// phys = <&usbphy1>;
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// phy-names = "usb2-phy";
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};
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usbphy: phy {
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compatible = "artinchip,aic-usb-phy";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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usbphy0: usb-phy@1020004 {
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#phy-cells = <0>;
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reg = <0x0 0x1020004 0x0 0x400>;
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clocks = <&cmu CLK_USB_PHY0>;
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clock-names = "phyclk";
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resets = <&rst RESET_USBPHY0>;
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reset-names = "usbphy";
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};
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usbphy1: usb-phy@10210004 {
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#phy-cells = <0>;
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reg = <0x0 0x1021004 0x0 0x400>;
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clocks = <&cmu CLK_USB_PHY1>;
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clock-names = "phyclk";
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resets = <&rst RESET_USBPHY1>;
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reset-names = "usbphy";
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};
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};
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gmac0: ethernet@10280000 {
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compatible = "artinchip,aic-gmac";
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#local-mac-address = [2e f6 01 e3 76 b6];
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reg = <0x0 0x20280000 0x0 0x10000>;
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interrupts-extended = <&plic0 39 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&cmu CLK_GMAC0>;
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clock-names = "gmac";
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resets = <&rst RESET_GMAC0>;
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reset-names = "gmac";
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};
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gmac1: ethernet@10290000 {
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compatible = "artinchip,aic-gmac";
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#local-mac-address = [2e f6 01 e3 76 b7];
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reg = <0x0 0x20290000 0x0 0x10000>;
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interrupts-extended = <&plic0 40 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&cmu CLK_GMAC1>;
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clock-names = "gmac";
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resets = <&rst RESET_GMAC1>;
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reset-names = "gmac";
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};
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spi0: spi@10400000 {
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compatible = "artinchip,aic-spi";
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reg = <0x0 0x20400000 0x0 0x1000>;
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interrupts-extended = <&plic0 44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SPI0>;
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resets = <&rst RESET_SPI0>;
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dmas = <&dma DMA_SPI0>, <&dma DMA_SPI0>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <24000000>;
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};
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spi1: spi@10410000 {
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compatible = "artinchip,aic-spi";
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reg = <0x0 0x20410000 0x0 0x1000>;
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interrupts-extended = <&plic0 45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SPI1>;
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resets = <&rst RESET_SPI1>;
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dmas = <&dma DMA_SPI1>, <&dma DMA_SPI1>;
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dma-names = "rx", "tx";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <24000000>;
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};
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pbus: pbus@107F0000 {
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compatible = "artinchip,aic-pbus-v1.0";
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reg = <0x0 0x207F0000 0x0 0x1000>;
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clocks = <&cmu CLK_PBUS>;
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resets = <&rst RESET_PBUS>;
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};
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sdmc0: sdmc@10440000 {
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compatible = "artinchip,aic-sdmc";
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reg = <0x0 0x20440000 0x0 0x1000>;
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interrupts-extended = <&plic0 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SDMC0>;
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clock-names = "ciu";
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resets = <&rst RESET_SDMC0>;
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reset-names = "reset";
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#address-cells = <1>;
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#size-cells = <0>;
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max-frequency = <24000000>;
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clock-frequency = <48000000>;
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bus-width = <4>;
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fifo-depth = <128>;
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};
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sdmc1: sdmc@10450000 {
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compatible = "artinchip,aic-sdmc";
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reg = <0x0 0x20450000 0x0 0x1000>;
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interrupts-extended = <&plic0 47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SDMC1>;
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clock-names = "ciu";
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resets = <&rst RESET_SDMC1>;
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reset-names = "reset";
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#address-cells = <1>;
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#size-cells = <0>;
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max-frequency = <24000000>;
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clock-frequency = <48000000>;
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bus-width = <4>;
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fifo-depth = <128>;
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};
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sdmc2: sdmc@10460000 {
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compatible = "artinchip,aic-sdmc";
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reg = <0x0 0x20460000 0x0 0x1000>;
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interrupts-extended = <&plic0 48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SDMC2>;
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clock-names = "ciu";
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resets = <&rst RESET_SDMC2>;
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reset-names = "reset";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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cmu: clock@18020000 {
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compatible = "artinchip,aic-cmu-v1.0";
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reg = <0 0x20020000 0 0x1000>;
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clocks = <&osc24m>, <&rc1m>, <&osc32k>;
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clock-names = "osc24m", "rc1m", "osc32k";
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#clock-cells = <1>;
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status = "okay";
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};
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rst: reset@18020004 {
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compatible = "artinchip,aic-reset-v1.0";
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reg = <0 0x20020000 0 0x1000>;
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#reset-cells = <1>;
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status = "okay";
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};
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rtc: rtc@18030000 {
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compatible = "artinchip,aic-rtc-v1.0";
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reg = <0x0 0x20030000 0x0 0x1000>;
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interrupts-extended = <&plic0 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_RTC>;
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resets = <&rst RESET_RTC>;
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};
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mtop: mtop@184ff000 {
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compatible = "artinchip,aic-mtop";
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reg = <0x0 0x204ff000 0x0 0x1000>;
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interrupts-extended = <&plic0 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_MTOP>;
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resets = <&rst RESET_MTOP>;
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status = "okay";
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};
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syscfg: syscfg@18000000 {
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compatible = "artinchip,aic-syscfg";
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reg = <0x0 0x20000000 0x0 0x1000>;
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clocks = <&cmu CLK_SYSCFG>;
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resets = <&rst RESET_SYSCFG>;
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status = "okay";
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};
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i2s0: i2s@18600000 {
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#sound-dai-cells = <0>;
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compatible = "artinchip,aic-i2s-v1.0";
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reg = <0x0 0x22600000 0x0 0x400>;
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interrupts-extended = <&plic0 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_I2S0>;
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resets = <&rst RESET_I2S0>;
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dmas = <&dma DMA_I2S0>, <&dma DMA_I2S0>;
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dma-names = "rx", "tx";
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};
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i2s1: i2s@18601000 {
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#sound-dai-cells = <0>;
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compatible = "artinchip,aic-i2s-v1.0";
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reg = <0x0 0x22601000 0x0 0x400>;
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interrupts-extended = <&plic0 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_I2S1>;
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resets = <&rst RESET_I2S1>;
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dmas = <&dma DMA_I2S1>, <&dma DMA_I2S1>;
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dma-names = "rx", "tx";
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};
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codec: codec@18610000 {
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#sound-dai-cells = <0>;
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compatible = "artinchip,aic-codec-v1.0";
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reg = <0x0 0x22610000 0x0 0x400>;
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interrupts-extended = <&plic0 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_CODEC>;
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resets = <&rst RESET_CODEC>;
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dmas = <&dma DMA_CODEC>, <&dma DMA_CODEC>;
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dma-names = "rx", "tx";
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};
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pinctrl: pinctrl@19200000 {
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compatible = "artinchip,aic-pinctrl-v1.0";
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reg = <0x0 0x23200000 0x0 0x800>;
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};
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uart0: serial@10000000 {
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compatible = "artinchip,aic-uart", "snps,dw-apb-uart", "ns16550a";
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reg = <0x0 0x10000000 0x0 0x100>;
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interrupts-extended = <&plic0 10 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_UART0>;
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clock-frequency = <3686400>;
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resets = <&rst RESET_UART0>;
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dmas = <&dma DMA_UART0>, <&dma DMA_UART0>;
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dma-names = "rx", "tx";
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};
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uart1: serial@19211000 {
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compatible = "artinchip,aic-uart";
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reg = <0x0 0x19211000 0x0 0x400>;
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interrupts-extended = <&plic0 77 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cmu CLK_UART1>;
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resets = <&rst RESET_UART1>;
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dmas = <&dma DMA_UART1>, <&dma DMA_UART1>;
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dma-names = "rx", "tx";
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};
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uart2: serial@19212000 {
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compatible = "artinchip,aic-uart";
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reg = <0x0 0x19212000 0x0 0x400>;
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interrupts-extended = <&plic0 78 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cmu CLK_UART2>;
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resets = <&rst RESET_UART2>;
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dmas = <&dma DMA_UART2>, <&dma DMA_UART2>;
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dma-names = "rx", "tx";
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};
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uart3: serial@19213000 {
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compatible = "artinchip,aic-uart";
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reg = <0x0 0x19213000 0x0 0x400>;
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interrupts-extended = <&plic0 79 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&cmu CLK_UART3>;
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resets = <&rst RESET_UART3>;
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dmas = <&dma DMA_UART3>, <&dma DMA_UART3>;
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dma-names = "rx", "tx";
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};
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uart4: serial@19214000 {
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compatible = "artinchip,aic-uart";
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reg = <0x0 0x19214000 0x0 0x400>;
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interrupts-extended = <&plic0 80 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
|
|
clocks = <&cmu CLK_UART4>;
|
|
resets = <&rst RESET_UART4>;
|
|
dmas = <&dma DMA_UART4>, <&dma DMA_UART4>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
uart5: serial@19215000 {
|
|
compatible = "artinchip,aic-uart";
|
|
reg = <0x0 0x19215000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cmu CLK_UART5>;
|
|
resets = <&rst RESET_UART5>;
|
|
dmas = <&dma DMA_UART5>, <&dma DMA_UART5>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
uart6: serial@19216000 {
|
|
compatible = "artinchip,aic-uart";
|
|
reg = <0x0 0x19216000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cmu CLK_UART6>;
|
|
resets = <&rst RESET_UART6>;
|
|
dmas = <&dma DMA_UART6>, <&dma DMA_UART6>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
uart7: serial@19217000 {
|
|
compatible = "artinchip,aic-uart";
|
|
reg = <0x0 0x19217000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
clocks = <&cmu CLK_UART7>;
|
|
resets = <&rst RESET_UART7>;
|
|
dmas = <&dma DMA_UART7>, <&dma DMA_UART7>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
|
|
i2c0: i2c@19220000 {
|
|
compatible = "artinchip,aic-i2c";
|
|
reg = <0x0 0x23220000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_I2C0>;
|
|
resets = <&rst RESET_I2C0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c@19221000 {
|
|
compatible = "artinchip,aic-i2c";
|
|
reg = <0x0 0x23221000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_I2C1>;
|
|
resets = <&rst RESET_I2C1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c@19222000 {
|
|
compatible = "artinchip,aic-i2c";
|
|
reg = <0x0 0x23222000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_I2C2>;
|
|
resets = <&rst RESET_I2C2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c@19223000 {
|
|
compatible = "artinchip,aic-i2c";
|
|
reg = <0x0 0x23223000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 87 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_I2C3>;
|
|
resets = <&rst RESET_I2C3>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
can0: can@19230000 {
|
|
compatible = "artc,artc-can";
|
|
reg = <0x0 0x23230000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_CAN0>;
|
|
resets = <&rst RESET_CAN0>;
|
|
};
|
|
|
|
can1: can@19231000 {
|
|
compatible = "artc,artc-can";
|
|
reg = <0x0 0x23231000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_CAN1>;
|
|
resets = <&rst RESET_CAN1>;
|
|
};
|
|
|
|
pwm: pwm@19240000 {
|
|
compatible = "artinchip,aic-pwm-v1.0";
|
|
reg = <0x0 0x23240000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&cmu CLK_PWM>, <&cmu CLK_PLL_INT1>;
|
|
clock-names = "pwm", "sysclk";
|
|
resets = <&rst RESET_PWM>;
|
|
clock-rate = <24000000>;
|
|
};
|
|
|
|
cir: cir@19260000 {
|
|
compatible = "artinchip,aic-cir";
|
|
reg = <0x0 0x23260000 0x0 0x400>;
|
|
interrupts-extended = <&plic0 95 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_CIR>;
|
|
resets = <&rst RESET_CIR>;
|
|
};
|
|
|
|
rgb0: rgb@18800000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "artinchip,aic-rgb-v1.0";
|
|
reg = <0x0 0x22800000 0x0 0x1000>;
|
|
clocks = <&cmu CLK_RGB>, <&cmu CLK_SCLK>;
|
|
clock-names = "rgb0", "sclk";
|
|
resets = <&rst RESET_RGB>;
|
|
reset-names = "rgb0";
|
|
};
|
|
|
|
lvds0: lvds@18810000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "artinchip,aic-lvds-v1.0";
|
|
reg = <0x0 0x22810000 0x0 0x1000>;
|
|
clocks = <&cmu CLK_LVDS>, <&cmu CLK_SCLK>;
|
|
clock-names = "lvds0", "sclk";
|
|
resets = <&rst RESET_LVDS>;
|
|
reset-names = "lvds0";
|
|
};
|
|
|
|
dsi0: dsi@18820000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "artinchip,aic-mipi-dsi-v1.0";
|
|
reg = <0x0 0x22820000 0x0 0x1000>;
|
|
clocks = <&cmu CLK_MIPIDSI>, <&cmu CLK_SCLK>;
|
|
clock-names = "dsi0", "sclk";
|
|
resets = <&rst RESET_MIPIDSI>;
|
|
reset-names = "dsi0";
|
|
interrupts-extended = <&plic0 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
format = "rgb888";
|
|
mode = "video-burst";
|
|
lane_num = <4>;
|
|
virtual_channel_num = <0>;
|
|
};
|
|
|
|
de0: de@18a00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "artinchip,aic-de-v1.0";
|
|
reg = <0x0 0x22a00000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_DE>, <&cmu CLK_PIX>;
|
|
clock-names = "de0", "pix";
|
|
resets = <&rst RESET_DE>;
|
|
reset-names = "de0";
|
|
mclk = <200000000>;
|
|
};
|
|
|
|
display-fb {
|
|
compatible = "artinchip,aic-framebuffer";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
fb0: fb@0 {
|
|
reg = <0x0 0x0>;
|
|
};
|
|
};
|
|
|
|
ge0: ge@18b00000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "artinchip,aic-ge-v1.0";
|
|
reg = <0x0 0x22b00000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 60 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_GE>;
|
|
clock-names = "ge";
|
|
resets = <&rst RESET_GE>;
|
|
reset-names = "ge";
|
|
};
|
|
|
|
dvp0: dvp@18830000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "artinchip,aic-dvp-v1.0";
|
|
reg = <0x0 0x22830000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_DVP>;
|
|
clock-rate = <200000000>;
|
|
resets = <&rst RESET_DVP>;
|
|
};
|
|
|
|
wdt0: watchdog@19000000 {
|
|
compatible = "artinchip,aic-wdt-v1.0";
|
|
reg = <0x0 0x23000000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 64 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_WDOG>;
|
|
resets = <&rst RESET_WDOG>;
|
|
};
|
|
|
|
adcim: adcim@19250000 {
|
|
compatible = "artinchip,aic-adcim-v1.0";
|
|
reg = <0x0 0x23250000 0x0 0x1000>;
|
|
clocks = <&cmu CLK_ADCIM>;
|
|
resets = <&rst RESET_ADCIM>;
|
|
};
|
|
|
|
gpai: gpai@19251000 {
|
|
compatible = "artinchip,aic-gpai-v1.0";
|
|
reg = <0x0 0x23251000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 92 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_GPAI>, <&cmu CLK_APB1>;
|
|
clock-names = "gpai", "pclk";
|
|
resets = <&rst RESET_GPAI>;
|
|
};
|
|
|
|
rtp: rtp@19252000 {
|
|
compatible = "artinchip,aic-rtp-v1.0";
|
|
reg = <0x0 0x23252000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 93 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_RTP>;
|
|
resets = <&rst RESET_RTP>;
|
|
};
|
|
|
|
tsen: tsen@19253000 {
|
|
compatible = "artinchip,aic-tsen-v1.0";
|
|
reg = <0x0 0x23253000 0x0 0x1000>;
|
|
interrupts-extended = <&plic0 94 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cmu CLK_TSEN>, <&cmu CLK_APB1>;
|
|
clock-names = "tsen", "pclk";
|
|
resets = <&rst RESET_TSEN>;
|
|
};
|
|
};
|
|
};
|