336 lines
8.9 KiB
C
336 lines
8.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2023 ArtInChip Inc.
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*/
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#include <common.h>
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#include <command.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass-internal.h>
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#include <linux/delay.h>
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#include <div64.h>
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#include "clk-aic.h"
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#include "ctype.h"
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#if CONFIG_IS_ENABLED(CMD_CLK)
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struct aic_clks aic_clk_names[] = {
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/* Fixed rate clock */
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{ CLK_DUMMY, "CLK_DUMMY" },
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{ CLK_OSC24M, "CLK_OSC24M" },
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{ CLK_OSC32K, "CLK_OSC32K" },
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{ CLK_RC1M, "CLK_RC1M" },
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/* PLL clock */
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{ CLK_PLL_INT0, "CLK_PLL_INT0" },
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{ CLK_PLL_INT1, "CLK_PLL_INT1" },
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{ CLK_PLL_FRA0, "CLK_PLL_FRA0" },
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{ CLK_PLL_FRA1, "CLK_PLL_FRA1" },
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{ CLK_PLL_FRA2, "CLK_PLL_FRA2" },
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/* system clock */
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{ CLK_AXI0, "CLK_AXI0" },
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{ CLK_AHB0, "CLK_AHB0" },
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{ CLK_APB0, "CLK_APB0" },
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{ CLK_APB1, "CLK_APB1" },
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{ CLK_CPU, "CLK_CPU" },
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/* Peripheral clock */
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{ CLK_DMA, "CLK_DMA" },
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{ CLK_CE, "CLK_CE" },
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{ CLK_USBD, "CLK_USBD" },
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{ CLK_USBH0, "CLK_USBH0" },
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{ CLK_USBH1, "CLK_USBH1" },
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{ CLK_USB_PHY0, "CLK_USB_PHY0" },
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{ CLK_USB_PHY1, "CLK_USB_PHY1" },
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{ CLK_GMAC0, "CLK_GMAC0" },
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{ CLK_GMAC1, "CLK_GMAC1" },
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{ CLK_SPI0, "CLK_SPI0" },
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{ CLK_SPI1, "CLK_SPI1" },
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{ CLK_SPI2, "CLK_SPI2" },
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{ CLK_SPI3, "CLK_SPI3" },
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{ CLK_SDMC0, "CLK_SDMC0" },
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{ CLK_SDMC1, "CLK_SDMC1" },
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{ CLK_SDMC2, "CLK_SDMC2" },
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{ CLK_SYSCFG, "CLK_SYSCFG" },
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{ CLK_RTC, "CLK_RTC" },
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{ CLK_SPIENC, "CLK_SPIENC" },
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{ CLK_I2S0, "CLK_I2S0" },
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{ CLK_I2S1, "CLK_I2S1" },
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{ CLK_CODEC, "CLK_CODEC" },
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{ CLK_RGB, "CLK_RGB" },
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{ CLK_LVDS, "CLK_LVDS" },
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{ CLK_MIPIDSI, "CLK_MIPIDSI" },
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{ CLK_DE, "CLK_DE" },
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{ CLK_GE, "CLK_GE" },
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{ CLK_VE, "CLK_VE" },
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{ CLK_WDOG, "CLK_WDOG" },
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{ CLK_SID, "CLK_SID" },
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{ CLK_GTC, "CLK_GTC" },
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{ CLK_GPIO, "CLK_GPIO" },
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{ CLK_UART0, "CLK_UART0" },
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{ CLK_UART1, "CLK_UART1" },
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{ CLK_UART2, "CLK_UART2" },
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{ CLK_UART3, "CLK_UART3" },
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{ CLK_UART4, "CLK_UART4" },
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{ CLK_UART5, "CLK_UART5" },
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{ CLK_UART6, "CLK_UART6" },
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{ CLK_UART7, "CLK_UART7" },
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{ CLK_I2C0, "CLK_I2C0" },
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{ CLK_I2C1, "CLK_I2C1" },
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{ CLK_I2C2, "CLK_I2C2" },
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{ CLK_I2C3, "CLK_I2C3" },
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{ CLK_CAN0, "CLK_CAN0" },
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{ CLK_CAN1, "CLK_CAN1" },
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{ CLK_PWM, "CLK_PWM" },
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{ CLK_ADCIM, "CLK_ADCIM" },
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{ CLK_GPAI, "CLK_GPAI" },
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{ CLK_RTP, "CLK_RTP" },
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{ CLK_TSEN, "CLK_TSEN" },
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{ CLK_CIR, "CLK_CIR" },
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{ CLK_DVP, "CLK_DVP" },
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{ CLK_PBUS, "CLK_PBUS" },
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{ CLK_MTOP, "CLK_MTOP" },
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{ CLK_DM, "CLK_DM" },
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{ CLK_PWMCS, "CLK_PWMCS" },
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{ CLK_PSADC, "CLK_PSADC" },
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{ CLK_DDR, "CLK_DDR" },
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/* Display clock */
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{ CLK_PIX, "CLK_PIX" },
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{ CLK_SCLK, "CLK_SCLK" },
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/* Output clock */
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{ CLK_OUT0, "CLK_OUT0" },
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{ CLK_OUT1, "CLK_OUT1" },
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{ CLK_OUT2, "CLK_OUT2" },
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{ CLK_OUT3, "CLK_OUT3" },
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{ AIC_CLK_END, "AIC_CLK_END" },
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};
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#define GET_NUM 4
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int soc_clk_dump(void)
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{
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struct udevice *dev;
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struct clk clk;
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ulong rate;
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int i, ret;
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struct aic_clk_priv *priv;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(artinchip_cmu), &dev);
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if (ret)
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return ret;
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priv = dev_get_priv(dev);
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printf("------------------------------------\n");
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printf("Clk-ID\t| NAME | Hz\n");
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for (i = 0; i < AIC_CLK_END; i++) {
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clk.id = aic_clk_names[i].id;
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clk.dev = dev;
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rate = clk_get_rate(&clk);
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printf(" %u\t %-14s %lu\n", i, aic_clk_names[i].name, rate);
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}
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printf("\n------------------------------------\n");
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return 0;
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}
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static int aic_clk_dump_mux(u32 clk_start, u32 clk_cnt)
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{
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struct udevice *dev;
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struct clk clk;
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ulong rate;
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int i, ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(artinchip_cmu), &dev);
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if (ret)
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return ret;
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printf("------------------------------------\n");
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printf("Clk-ID\t| NAME | Hz\n");
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for (i = clk_start; i < (clk_start + clk_cnt); i++) {
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clk.id = aic_clk_names[i].id;
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clk.dev = dev;
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rate = clk_get_rate(&clk);
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printf(" %u\t %-14s %lu\n", i, aic_clk_names[i].name, rate);
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}
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printf("\n------------------------------------\n");
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printf("0: Fixed rate clock 1: PLL clock 2: System clock\n");
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printf("3: Peripheral clock 4: Display clock 5: Output clock\n");
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printf("none: all clocks\n");
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return 0;
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}
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static int do_aic_clk_dump(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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struct udevice *dev;
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struct aic_clk_priv *priv;
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struct aic_clk_tree *tree;
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int ret;
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ulong ch;
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if (argc < 2) {
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ret = aic_clk_dump_mux(0, AIC_CLK_END);
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return 0;
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}
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(artinchip_cmu), &dev);
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if (ret)
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return ret;
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priv = dev_get_priv(dev);
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tree = priv->tree;
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printf("------------------------------------\n");
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ch = dectoul(argv[1], NULL);
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switch (ch) {
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case AIC_CLK_FIXED_RATE:
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printf("\tFixed rate clock info\n");
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aic_clk_dump_mux(tree->fixed_rate_base, tree->fixed_rate_cnt);
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break;
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case AIC_CLK_PLL:
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printf("\tPLL clock info\n");
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aic_clk_dump_mux(tree->pll_base, tree->pll_cnt);
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break;
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case AIC_CLK_SYSTEM:
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printf("\tSystem clock info\n");
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aic_clk_dump_mux(tree->system_base, tree->system_cnt);
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break;
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case AIC_CLK_PERIPHERAL:
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printf("\tPeripheral clock\n");
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aic_clk_dump_mux(tree->periph_base, tree->periph_cnt);
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break;
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case AIC_CLK_DISP:
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printf("\tDisplay clock info\n");
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aic_clk_dump_mux(tree->disp_base, tree->disp_cnt);
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break;
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case AIC_CLK_OUTPUT:
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printf("\tOutput clock info\n");
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aic_clk_dump_mux(tree->clkout_base, tree->clkout_cnt);
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break;
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default:
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ret = aic_clk_dump_mux(0, AIC_CLK_END);
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break;
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}
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if (ret < 0) {
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printf("Clock dump error %d\n", ret);
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ret = CMD_RET_FAILURE;
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}
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return 0;
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}
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static int do_aic_clk_get(struct cmd_tbl *cmdtp, int falg, int argc,
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char *const argv[])
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{
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struct udevice *dev;
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struct aic_clks aic_clks;
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struct clk clk;
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int ret, i, j;
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ulong rate, ch;
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if (argc < 2) {
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printf("please input [module name] or [clk id]. such:SPI SPI0 ...\n");
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return CMD_RET_USAGE;
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} else if (argc > (GET_NUM + 1)) {
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printf("You can only enter %d indexes at most!\n", GET_NUM);
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return CMD_RET_USAGE;
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}
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(artinchip_cmu), &dev);
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if (ret)
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return ret;
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printf("------------------------------------\n");
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printf("Clk-ID\t| NAME | Hz\n");
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for (j = 1; j < argc; j++) {
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if (isalpha(argv[j][0]) == 0) {
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ch = dectoul(argv[j], NULL);
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if (ch >= AIC_CLK_END)
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break;
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clk.id = aic_clk_names[ch].id;
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clk.dev = dev;
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rate = clk_get_rate(&clk);
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printf(" %lu\t %-14s %lu\n", aic_clk_names[ch].id,
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aic_clk_names[ch].name, rate);
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} else {
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for (i = 0; i < AIC_CLK_END; i++) {
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aic_clks.name = aic_clk_names[i].name;
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aic_clks.name += 4;
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ret = strncmp(aic_clks.name, argv[j], strlen(argv[j]));
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if (ret == 0) {
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clk.id = aic_clk_names[i].id;
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clk.dev = dev;
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rate = clk_get_rate(&clk);
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printf(" %lu\t %-14s %lu\n", aic_clk_names[i].id,
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aic_clk_names[i].name, rate);
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}
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}
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}
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}
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printf("\n------------------------------------\n");
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return 0;
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}
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static int do_aic_clk_set(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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struct udevice *dev;
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struct clk clk;
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int ret;
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ulong freq, pre_freq, index;
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if (argc < 3)
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return CMD_RET_USAGE;
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index = dectoul(argv[1], NULL);
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freq = dectoul(argv[2], NULL);
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_DRIVER_GET(artinchip_cmu), &dev);
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if (ret)
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return ret;
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printf("------------------------------------\n");
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clk.id = index;
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clk.dev = dev;
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pre_freq = clk_get_rate(&clk);
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ret = clk_set_rate(&clk, freq);
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if (ret == 0)
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printf("Clock frequency is set successsfully!\n");
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printf("Clk-ID\t| NAME | Hz\n");
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printf(" %lu\t %-14s %lu ----> %lu\n", aic_clk_names[index].id,
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aic_clk_names[index].name, pre_freq, freq);
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freq = clk_get_rate(&clk);
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printf("-\n");
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printf(" %lu\t %-14s %lu\n", aic_clk_names[index].id,
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aic_clk_names[index].name, freq);
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printf("\n------------------------------------\n");
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return 0;
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}
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static char clk_help_text[] =
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"ArtInChip clk command\n"
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"------------------------------------\n"
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"aic_clk dump [type] -all clock info \n"
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" [type] 0: Fixed rate clock 1: PLL cloc 2: System clock\n"
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" 3: Peripheral clock 4: Display clock 5: Output clock\n"
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" none: all clocks\n"
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"aic_clk get [id] or [name] -get clk info [name]: SPI, SPI0...\n"
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"aic_clk set [id] [Hz] -set clock frequency\n";
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U_BOOT_CMD_WITH_SUBCMDS(aic_clk, "ArtInChip clk command", clk_help_text,
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U_BOOT_SUBCMD_MKENT(dump, 2, 0, do_aic_clk_dump),
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U_BOOT_SUBCMD_MKENT(get, GET_NUM + 2, 1, do_aic_clk_get),
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U_BOOT_SUBCMD_MKENT(set, 3, 0, do_aic_clk_set));
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#endif
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