104 lines
3.2 KiB
JSON
104 lines
3.2 KiB
JSON
{
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"dram": { // DDR init parameters
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"ddr3": {
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"type": "0x00000003",
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"memsize": "0x8000000",
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"freq": "672000000",
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"zq": "0x80005d5d",
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"odt": "0x00000004",
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"para1": "0x000030DA",
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"para2": "0x02000000",
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"mr0": "0x00001C70",
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"mr1": "0x00000040",
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"mr2": "0x00000018",
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"mr3": "0x00000000",
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"mr4": "0x00000000",
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"mr5": "0x00000400",
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"mr6": "0x00000848",
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"tpr0": "0x0048A192",
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"tpr1": "0x01B1A94B",
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"tpr2": "0x00061043",
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"tpr3": "0x78787896",
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"tpr4": "0x00000000",
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"tpr5": "0x00000000",
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"tpr6": "0x00000000",
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"tpr7": "0x00000000",
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"tpr8": "0x00000000",
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"tpr9": "0x00000C0C",
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"tpr10": "0x00001900",
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"tpr11": "0x16160A0A",
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"tpr12": "0x12120000",
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"tpr13": "0x0001E001",
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"tpr14": "0x00000000",
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"tpr15": "0x00000000",
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"tpr16": "0x00000000",
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"tpr17": "0x00000000",
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"tpr18": "0x00000000",
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},
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},
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"system": {
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"uart": { // PBP's uart setting
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"main": {
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// "uart_id": "0", // UART0 for log output
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// "uart_tx_pin_cfg_reg": "0x18700080", // PA0
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x18700084", // PA1
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// "uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "0", // UART0 for log output
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// "uart_tx_pin_cfg_reg": "0x18700E88", // PN2
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// "uart_tx_pin_cfg_val": "0x324",
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// "uart_rx_pin_cfg_reg": "0x18700E8C", // PN3
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// "uart_rx_pin_cfg_val": "0x324",
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"uart_id": "1", // UART1 for log output
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"uart_tx_pin_cfg_reg": "0x18700090", // PA4
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"uart_tx_pin_cfg_val": "0x325",
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"uart_rx_pin_cfg_reg": "0x18700094", // PA5
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"uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "3", // UART3 for log output
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// "uart_tx_pin_cfg_reg": "0x187004B8", // PE14
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x187004BC", // PE15
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// "uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "4", // UART4 for log output
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// "uart_tx_pin_cfg_reg": "0x18700198", // PB6
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x1870019C", // PB7
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// "uart_rx_pin_cfg_val": "0x325",
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// "uart_id": "5", // UART5 for log output
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// "uart_tx_pin_cfg_reg": "0x18700490", // PE4
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// "uart_tx_pin_cfg_val": "0x325",
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// "uart_rx_pin_cfg_reg": "0x18700494", // PE5
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// "uart_rx_pin_cfg_val": "0x325",
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},
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},
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"jtag": {
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"jtag_only": "0", // 1: Boot code stop in PBP after DDR init and jtag init
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"main": {
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"jtag_id": "0",
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"jtag_do_pin_cfg_reg": "0x187000A0", // PA8
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"jtag_do_pin_cfg_val": "0x336",
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"jtag_di_pin_cfg_reg": "0x187000A4", // PA9
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"jtag_di_pin_cfg_val": "0x336",
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"jtag_ms_pin_cfg_reg": "0x187000A8", // PA10
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"jtag_ms_pin_cfg_val": "0x336",
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"jtag_ck_pin_cfg_reg": "0x187000AC", // PA11
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"jtag_ck_pin_cfg_val": "0x336",
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// "jtag_do_pin_cfg_reg": "0x1870028C", // PC3
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// "jtag_do_pin_cfg_val": "0x336",
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// "jtag_di_pin_cfg_reg": "0x18700284", // PC1
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// "jtag_di_pin_cfg_val": "0x336",
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// "jtag_ms_pin_cfg_reg": "0x18700280", // PC0
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// "jtag_ms_pin_cfg_val": "0x336",
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// "jtag_ck_pin_cfg_reg": "0x18700294", // PC5
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// "jtag_ck_pin_cfg_val": "0x336",
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},
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},
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},
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}
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