67 lines
2.0 KiB
C
67 lines
2.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2021 ArtInChip Technology Co., Ltd
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* Dehuang Wu <dehuang.wu@artinchip.com>
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*/
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#ifndef __AIC_UPG_NAND_FWC_SPL_H__
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#define __AIC_UPG_NAND_FWC_SPL_H__
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#include <linux/kernel.h>
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#include <linux/sizes.h>
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#include "upg_internal.h"
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#define SPL_NAND_IMAGE_BACKUP_NUM 4
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#define PAGE_CNT_PER_BLOCK 64
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#define PAGE_TABLE_MAX_ENTRY 101
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#define SLICE_DEFAULT_SIZE 2048
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#define PAGE_TABLE_USE_SIZE 2048
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#define PAGE_MAX_SIZE 4096
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#define SPL_CANDIDATE_BLOCK_NUM 18
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#define SPL_INVALID_BLOCK_IDX 0xFFFFFFFF
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#define SPL_INVALID_PAGE_ADDR 0xFFFFFFFF
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struct nand_page_table_head {
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char magic[4]; /* AICP: AIC Page table */
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u32 entry_cnt;
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u16 page_size;
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u8 pad[10]; /* Padding it to fit size 20 bytes */
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};
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/*
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* FSBL page data store in 4 block's NAND Page. This structure is used to keep
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* all 4 NAND page address that storing FSBL page data, and keep that page data
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* checksum value(Actually is ~checksum (inverted)).
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*/
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struct nand_page_table_entry {
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u32 pageaddr[SPL_NAND_IMAGE_BACKUP_NUM]; /* Page address in block */
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u32 checksum; /* Page data checksum/crc32 value */
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};
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/*
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* Page Table
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*
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* Page table store page and data checksum information of FSBL.
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*
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* FSBL data will be splited into a lot of 2KB slices, each slice use one NAND
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* page to store it. Programmer and BROM don't care the actual NAND page size
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* is 2KB or 4KB or greater, just use the first 2KB(Not support page size less
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* than 2KB NAND).
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*
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* Every slice has 4 backup, that means 4 pages in 4 different good blocks.
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* Page table is used to keep these page address information and checksum for
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* every slice.
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*
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* Page table always store in the first page of blocks.
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*/
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struct nand_page_table {
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struct nand_page_table_head head;
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struct nand_page_table_entry entry[PAGE_TABLE_MAX_ENTRY];
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};
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s32 nand_fwc_spl_reserve_blocks(void);
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s32 nand_fwc_spl_prepare(struct fwc_info *fwc);
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s32 nand_fwc_spl_writer(struct fwc_info *fwc, u8 *buf, s32 len);
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#endif /* __AIC_UPG_NAND_FWC_SPL_H__ */
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