237 lines
5.4 KiB
C
237 lines
5.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef _AC102_H_
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#define _AC102_H_
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#define CHIP_SOFT_RST 0x00
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#define PWR_CTRL1 0x01
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#define PWR_CTRL2 0x02
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#define SYS_FUNC_CTRL 0x03
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#define ADC_CLK_SET 0x04
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#define DAC_CLK_SET 0x05
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#define SYS_CLK_ENA 0x06
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#define I2S_CTRL 0x07
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#define I2S_BCLK_CTRL 0x08
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#define I2S_LRCK_CTRL1 0x09
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#define I2S_LRCK_CTRL2 0x0A
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#define I2S_FMT_CTRL1 0x0B
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#define I2S_FMT_CTRL2 0x0C
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#define I2S_FMT_CTRL3 0x0D
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#define I2S_SLOT_CTRL 0x0E
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#define I2S_TX_CTRL 0x0F
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#define I2S_TXCHMP_CTRL 0x11
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#define I2S_TX_MIX_SRC 0x13
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#define I2S_RXCHMP_CTRL 0x16
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#define I2S_RX_MIX_SRC 0x18
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#define ADC_DIG_CTRL 0x19
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#define ADC_DVC 0x1A
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#define DAC_DIG_CTRL 0x1B
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#define DAC_DVC 0x1C
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#define DAC_MIX_SRC 0x1D
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#define DIG_PADDRV_CTRL 0x1F
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#define ADC_ANA_CTRL1 0x20
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#define DAC_ANA_CTRL1 0x25
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#define DAC_ANA_CTRL2 0x26
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#define DAC_ANA_CTRL3 0x27
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#define DAC_ANA_CTRL4 0x28
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#define AGC_STA 0x30
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#define AGC_CTRL 0x31
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#define AGC_DEBT 0x32
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#define AGC_TGLVL 0x33
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#define AGC_MAXG 0x34
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#define AGC_AVGC1 0x35
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#define AGC_AVGC2 0x36
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#define AGC_AVGC3 0x37
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#define AGC_AVGC4 0x38
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#define AGC_DECAYT1 0x39
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#define AGC_DECAYT2 0x3A
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#define AGC_ATTACKT1 0x3B
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#define AGC_ATTACKT2 0x3C
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#define AGC_NTH 0x3D
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#define AGC_NAVGC1 0x3E
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#define AGC_NAVGC2 0x3F
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#define AGC_NAVGC3 0x40
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#define AGC_NAVGC4 0x41
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#define HPF_COEF1 0x42
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#define HPF_COEF2 0x43
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#define HPF_COEF3 0x44
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#define HPF_COEF4 0x45
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#define AGC_OPT 0x46
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#define EQ_CTRL 0x4F
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#define EQ1_B0_H 0x50
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#define EQ1_B0_M 0x51
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#define EQ1_B0_L 0x52
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#define EQ1_B1_H 0x53
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#define EQ1_B1_M 0x54
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#define EQ1_B1_L 0x55
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#define EQ1_B2_H 0x56
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#define EQ1_B2_M 0x57
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#define EQ1_B2_L 0x58
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#define EQ1_A1_H 0x59
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#define EQ1_A1_M 0x5A
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#define EQ1_A1_L 0x5B
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#define EQ1_A2_H 0x5C
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#define EQ1_A2_M 0x5D
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#define EQ1_A2_L 0x5E
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#define EQ2_B0_H 0x60
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#define EQ2_B0_M 0x61
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#define EQ2_B0_L 0x62
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#define EQ2_B1_H 0x63
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#define EQ2_B1_M 0x64
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#define EQ2_B1_L 0x65
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#define EQ2_B2_H 0x66
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#define EQ2_B2_M 0x67
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#define EQ2_B2_L 0x68
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#define EQ2_A1_H 0x69
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#define EQ2_A1_M 0x6A
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#define EQ2_A1_L 0x6B
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#define EQ2_A2_H 0x6C
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#define EQ2_A2_M 0x6D
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#define EQ2_A2_L 0x6E
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#define EQ3_B0_H 0x70
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#define EQ3_B0_M 0x71
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#define EQ3_B0_L 0x72
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#define EQ3_B1_H 0x73
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#define EQ3_B1_M 0x74
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#define EQ3_B1_L 0x75
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#define EQ3_B2_H 0x76
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#define EQ3_B2_M 0x77
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#define EQ3_B2_L 0x78
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#define EQ3_A1_H 0x79
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#define EQ3_A1_M 0x7A
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#define EQ3_A1_L 0x7B
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#define EQ3_A2_H 0x7C
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#define EQ3_A2_M 0x7D
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#define EQ3_A2_L 0x7E
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/* AC102 codec register bit define */
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/* PWR_CTRL1 */
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#define ALDO_VCTRL 5
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#define DLDO_VCTRL 2
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#define MBIAS_VCTRL 0
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/* PWR_CTRL1 */
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#define IREF_CTRL 5
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#define ALDO_EN 4
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#define DLDO_EN 3
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#define MBIAS_EN 2
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#define VREF_EN 1
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#define IREF_EN 0
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/* SYS_FUNC_CTRL */
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#define VREF_SPUP_STA 6
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#define DAC_ANA_OUT_EN 0
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/* SYS_CLK_ENA */
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#define SYSCLK_EN 5
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#define I2S_CLK_EN 4
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#define EQ_CLK_EN 3
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#define DAC_DIGITAL_CLK_EN 2
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#define AGC_HPF_CLK_EN 1
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#define ADC_DIGITAL_CLK_EN 0
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/* I2S_CTRL */
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#define BCLK_IOEN 7
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#define LRCK_IOEN 6
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#define SDO_EN 4
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#define TXEN 2
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#define RXEN 1
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#define I2SGEN 0
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/* I2S_BCLK_CTRL */
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#define EDGE_TRANSFER 5
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#define BCLK_POLARITY 4
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#define BCLK_DIV 0
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/* I2S_LRCK_CTRL1 */
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#define LRCK_POLARITY 4
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#define LRCK_PERIODH 0
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/* I2S_FMT_CTRL1 */
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#define MODE_SEL 4
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#define OFFSET 2
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#define TX_SLOT_HIZ 1
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#define TX_STATE 0
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/* I2S_FMT_CTRL2 */
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#define I2S_FMT_CTRL2_SW 4
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#define I2S_FMT_CTRL2_SR 0
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/* I2S_FMT_CTRL3 */
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#define TX_RX_MLS 7
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#define SEXT 5
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#define OUT_MUTE 3
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#define LRCK_WIDTH 2
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#define TX_RX_PDM 0
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/* I2S_SLOT_CTRL */
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#define RX_CHSEL 2
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#define TX_CHSEL 0
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/* I2S_TX_CHMP_CTRL */
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#define TX_CH2_MAP 1
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#define TX_CH1_MAP 0
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/* I2S_TX_MIX_SRC */
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#define TX_MIXR_GAIN 6
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#define TX_MIXL_GAIN 4
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#define TX_MIXR_SRC 2
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#define TX_MIXL_SRC 0
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/* I2S_RX_CHMP_CTRL */
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#define RX_CH2_MAP 2
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#define RX_CH1_MAP 0
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/* I2S_RX_MIX_SRC */
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#define RX_MIX_GAIN 2
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#define RX_MIX_SRC 0
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/* ADC_DIG_CTRL */
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#define ADC_PTN_SEL 4
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#define ADOUT_DTS 2
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#define ADOUT_DLY_EN 1
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#define ADC_DIG_EN 0
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/* DAC_DIG_CTRL */
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#define DVC_ZCD_EN 6
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#define DITHER_SGM 3
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#define DAC_PTN_SEL 1
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#define DAC_DIG_EN 0
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/* DAC_MIX_SRC */
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#define DAC_MIX_GAIN 2
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#define DAC_MIX_SRC_BIT 0
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/* DIG_PADDRV_CTRL */
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#define SDOUT_DRV 4
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#define LRCK_DRV 2
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#define BCLK_DRV 0
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/* ADC_ANA_CTRL1 */
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#define PGA_GAIN_CTRL 3
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#define PGA_CTRL_RCM 1
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#define ADC_GEN 0
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/* DAC_ANA_CTRL1 */
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#define VRDA_EN 5
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/* DAC_ANA_CTRL2 */
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#define LINEODIFEN 4
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#define LINEOAMPGAIN 0
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/* AGC_CTRL */
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#define AGC_ENABLE 4
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#define HPF_ENABLE 3
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#define NOISE_DETECT_ENABLE 2
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#define AGC_HYS_SET 0
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/*********************some config value**********************/
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//I2S BCLK POLARITY Control
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#define BCLK_NORMAL_DRIVE_N_SAMPLE_P 0
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#define BCLK_INVERT_DRIVE_P_SAMPLE_N 1
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//I2S LRCK POLARITY Control
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#define LRCK_LEFT_LOW_RIGHT_HIGH 0
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#define LRCK_LEFT_HIGH_RIGHT_LOW 1
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//I2S Format Selection
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#define PCM_FORMAT 0
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#define LEFT_JUSTIFIED_FORMAT 1
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#define RIGHT_JUSTIFIED_FORMAT 2
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//I2S Sign Extend in slot
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#define ZERO_OR_AUDIIO_GAIN_PADDING_LSB 0
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#define SIGN_EXTENSION_MSB 1
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#define TRANSFER_ZERO_AFTER 3
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//ADC Digital Debug Control
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#define ADC_PTN_NORMAL 0
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#define ADC_PTN_0x5A5A5A 1
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#define ADC_PTN_0x123456 2
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#define ADC_PTN_I2S_RX_DATA 3
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#endif
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