571 lines
17 KiB
C
571 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2020-2024 ArtInChip Inc.
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*/
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#include <common.h>
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#include <mapmem.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass-internal.h>
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#include "clk-aic.h"
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#include <dt-bindings/clock/artinchip,aic-cmu.h>
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#define PLL_INT0_GEN_REG (0x0000)
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#define PLL_INT1_GEN_REG (0x0004)
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#define PLL_FRA0_GEN_REG (0x0020)
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#define PLL_FRA1_GEN_REG (0x0024)
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#define PLL_FRA2_GEN_REG (0x0028)
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#define PLL_INT0_CFG_REG (0x0040)
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#define PLL_INT1_CFG_REG (0x0044)
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#define PLL_FRA0_CFG_REG (0x0060)
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#define PLL_FRA1_CFG_REG (0x0064)
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#define PLL_FRA2_CFG_REG (0x0068)
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#define PLL_FRA0_SDM_REG (0x0080)
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#define PLL_FRA1_SDM_REG (0x0084)
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#define PLL_FRA2_SDM_REG (0x0088)
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#define PLL_COM_REG (0x00A0)
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#define PLL_IN_REG (0x00A4)
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#define CLK_OUT0_REG (0x00E0)
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#define CLK_OUT1_REG (0x00E4)
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#define CLK_OUT2_REG (0x00E8)
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#define CLK_OUT3_REG (0x00EC)
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#define CLK_AXI0_REG (0x0100)
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#define CLK_AHB0_REG (0x0110)
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#define CLK_APB0_REG (0x0120)
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#define CLK_APB1_REG (0x0124)
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#define CLK_CPU_REG (0x0200)
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#define CLK_DM_REG (0x0204)
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#define CLK_DISP_REG (0x0220)
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#define CLK_DMA_REG (0x0410)
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#define CLK_CE_REG (0x0418)
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#define CLK_USBD_REG (0x041C)
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#define CLK_USBH0_REG (0x0420)
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#define CLK_USBH1_REG (0x0424)
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#define CLK_USBPHY0_REG (0x0430)
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#define CLK_USBPHY1_REG (0x0434)
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#define CLK_GMAC0_REG (0x0440)
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#define CLK_GMAC1_REG (0x0444)
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#define CLK_SPI0_REG (0x0460)
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#define CLK_SPI1_REG (0x0464)
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#define CLK_SPI2_REG (0x0468)
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#define CLK_SPI3_REG (0x046C)
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#define CLK_SDMC0_REG (0x0470)
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#define CLK_SDMC1_REG (0x0474)
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#define CLK_SDMC2_REG (0x0478)
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#define CLK_PBUS_REG (0x04A0)
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#define CLK_SYSCFG_REG (0x0800)
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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#define CLK_RTC_REG (0x0804)
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#else
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#define CLK_RTC_REG (0x0908)
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#endif
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#define CLK_SPIENC_REG (0x0810)
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#define CLK_PWMCS_REG (0x0814)
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#define CLK_PSADC_REG (0x0818)
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#define CLK_MTOP_REG (0x081C)
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#define CLK_I2S0_REG (0x0820)
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#define CLK_I2S1_REG (0x0824)
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#define CLK_CODEC_REG (0x0830)
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#define CLK_RGB_REG (0x0880)
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#define CLK_LVDS_REG (0x0884)
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#define CLK_MIPIDSI_REG (0x0888)
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#define CLK_DE_REG (0x08c0)
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#define CLK_GE_REG (0x08c4)
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#define CLK_VE_REG (0x08c8)
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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#define CLK_WDOG_REG (0x0900)
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#else
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#define CLK_WDOG_REG (0x020C)
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#endif
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#define CLK_SID_REG (0x0904)
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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#define CLK_GTC_REG (0x0908)
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#define CLK_GPIO_REG (0x091C)
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#define CLK_UART0_REG (0x0920)
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#define CLK_UART1_REG (0x0924)
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#define CLK_UART2_REG (0x0928)
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#define CLK_UART3_REG (0x092C)
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#define CLK_UART4_REG (0x0930)
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#define CLK_UART5_REG (0x0934)
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#define CLK_UART6_REG (0x0938)
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#define CLK_UART7_REG (0x093C)
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#else
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#define CLK_GTC_REG (0x090C)
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#define CLK_GPIO_REG (0x083C)
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#define CLK_UART0_REG (0x0840)
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#define CLK_UART1_REG (0x0844)
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#define CLK_UART2_REG (0x0848)
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#define CLK_UART3_REG (0x084C)
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#define CLK_UART4_REG (0x0850)
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#define CLK_UART5_REG (0x0854)
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#define CLK_UART6_REG (0x0858)
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#define CLK_UART7_REG (0x085C)
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#endif
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#define CLK_I2C0_REG (0x0960)
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#define CLK_I2C1_REG (0x0964)
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#define CLK_I2C2_REG (0x0968)
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#define CLK_I2C3_REG (0x096C)
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#define CLK_CAN0_REG (0x0980)
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#define CLK_CAN1_REG (0x0984)
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#define CLK_PWM_REG (0x0990)
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#define CLK_ADCIM_REG (0x09A0)
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#define CLK_GPAI_REG (0x09A4)
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#define CLK_RTP_REG (0x09A8)
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#define CLK_TSEN_REG (0x09AC)
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#define CLK_CIR_REG (0x09B0)
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struct aic_clk_plat {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_artinchip_aic_cmu_v1_0 dtplat;
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#endif
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};
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static struct aic_fixed_rate clk_fixed_rates[] = {
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/* id rate */
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CLK_FIXED_RATE(CLK_DUMMY, 0),
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CLK_FIXED_RATE(CLK_OSC24M, 24000000),
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CLK_FIXED_RATE(CLK_OSC32K, 32768),
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CLK_FIXED_RATE(CLK_RC1M, 1000000),
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};
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static struct aic_pll clk_plls[] = {
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CLK_PLL(CLK_PLL_INT0, PLL_INT0_GEN_REG, PLL_INT0_CFG_REG,
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0, AIC_PLL_INT),
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CLK_PLL(CLK_PLL_INT1, PLL_INT1_GEN_REG, PLL_INT1_CFG_REG,
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0, AIC_PLL_INT),
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// CLK_PLL(CLK_PLL_FRA0, PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG,
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// PLL_FRA0_SDM_REG, AIC_PLL_SDM),
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CLK_PLL(CLK_PLL_FRA0, PLL_FRA0_GEN_REG, PLL_FRA0_CFG_REG,
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PLL_FRA0_SDM_REG, AIC_PLL_FRA),
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CLK_PLL(CLK_PLL_FRA1, PLL_FRA1_GEN_REG, PLL_FRA1_CFG_REG,
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PLL_FRA1_SDM_REG, AIC_PLL_FRA),
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// CLK_PLL_VIDEO(CLK_PLL_FRA2, PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG,
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// PLL_FRA2_SDM_REG, AIC_PLL_SDM, 0, 1200000000),
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CLK_PLL_VIDEO(CLK_PLL_FRA2, PLL_FRA2_GEN_REG, PLL_FRA2_CFG_REG,
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PLL_FRA2_SDM_REG, AIC_PLL_FRA, 0, 1200000000),
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};
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static u32 axi0_src_sels[] = {CLK_OSC24M, CLK_PLL_INT1};
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static u32 ahb0_src_sels[] = {CLK_OSC24M, CLK_PLL_INT1};
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static u32 apb0_src_sels[] = {CLK_OSC24M, CLK_PLL_INT1};
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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static u32 apb1_src_sels[] = {CLK_OSC24M, CLK_PLL_INT1};
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#else
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static u32 apb1_src_sels[] = {CLK_OSC24M};
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#endif
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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static u32 cpu_src_sels[] = {CLK_OSC24M, CLK_PLL_INT0, CLK_DUMMY, CLK_OSC32K};
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#else
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static u32 cpu_src_sels[] = {CLK_OSC24M, CLK_PLL_INT0};
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#endif
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static struct aic_sys_clk clk_syss[] = {
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CLK_SYS_BUS(CLK_AXI0, CLK_AXI0_REG, axi0_src_sels,
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ARRAY_SIZE(axi0_src_sels), 8, 1, 0, 5),
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CLK_SYS_BUS(CLK_AHB0, CLK_AHB0_REG, ahb0_src_sels,
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ARRAY_SIZE(ahb0_src_sels), 8, 1, 0, 5),
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CLK_SYS_BUS(CLK_APB0, CLK_APB0_REG, apb0_src_sels,
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ARRAY_SIZE(apb0_src_sels), 8, 1, 0, 5),
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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CLK_SYS_BUS(CLK_APB1, CLK_APB1_REG, apb1_src_sels,
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ARRAY_SIZE(apb1_src_sels), 8, 1, 0, 5),
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CLK_SYS_BUS(CLK_CPU, CLK_CPU_REG, cpu_src_sels,
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ARRAY_SIZE(cpu_src_sels), 8, 2, 0, 5),
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#else
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CLK_SYS_BUS(CLK_APB1, CLK_APB1_REG, apb1_src_sels,
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ARRAY_SIZE(apb1_src_sels), 8, 1, 0, 0),
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CLK_SYS_BUS(CLK_CPU, CLK_CPU_REG, cpu_src_sels,
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ARRAY_SIZE(cpu_src_sels), 8, 1, 0, 5),
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#endif
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};
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static struct aic_periph_clk clk_periphs[] = {
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/* id parent reg */
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AIC_CLK_PERIPH(CLK_DMA, CLK_AHB0, CLK_DMA_REG),
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AIC_CLK_PERIPH(CLK_CE, CLK_PLL_INT1, CLK_CE_REG),
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#if !defined(CONFIG_SPL_BUILD)
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AIC_CLK_PERIPH(CLK_USBD, CLK_AHB0, CLK_USBD_REG),
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AIC_CLK_PERIPH(CLK_USBH0, CLK_AHB0, CLK_USBH0_REG),
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AIC_CLK_PERIPH(CLK_USBH1, CLK_AHB0, CLK_USBH1_REG),
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AIC_CLK_PERIPH(CLK_USB_PHY0, CLK_OSC24M, CLK_USBPHY0_REG),
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AIC_CLK_PERIPH(CLK_USB_PHY1, CLK_OSC24M, CLK_USBPHY1_REG),
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AIC_CLK_PERIPH(CLK_GMAC0, CLK_PLL_INT1, CLK_GMAC0_REG),
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AIC_CLK_PERIPH(CLK_GMAC1, CLK_PLL_INT1, CLK_GMAC1_REG),
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#endif
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AIC_CLK_PERIPH(CLK_SPI0, CLK_PLL_FRA0, CLK_SPI0_REG),
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AIC_CLK_PERIPH(CLK_SPI1, CLK_PLL_FRA0, CLK_SPI1_REG),
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#if !defined(CONFIG_SPL_BUILD)
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AIC_CLK_PERIPH(CLK_SPI2, CLK_PLL_FRA0, CLK_SPI2_REG),
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AIC_CLK_PERIPH(CLK_SPI3, CLK_PLL_FRA0, CLK_SPI3_REG),
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#endif
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AIC_CLK_PERIPH(CLK_SDMC0, CLK_PLL_FRA0, CLK_SDMC0_REG),
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AIC_CLK_PERIPH(CLK_SDMC1, CLK_PLL_FRA0, CLK_SDMC1_REG),
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#if !defined(CONFIG_SPL_BUILD)
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AIC_CLK_PERIPH(CLK_SDMC2, CLK_PLL_FRA0, CLK_SDMC2_REG),
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AIC_CLK_PERIPH(CLK_PBUS, CLK_AHB0, CLK_PBUS_REG),
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AIC_CLK_PERIPH(CLK_SYSCFG, CLK_OSC24M, CLK_SYSCFG_REG),
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#endif
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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AIC_CLK_PERIPH(CLK_RTC, CLK_APB0, CLK_RTC_REG),
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#else
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AIC_CLK_PERIPH(CLK_RTC, CLK_OSC32K, CLK_RTC_REG),
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#endif
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AIC_CLK_PERIPH(CLK_SPIENC, CLK_AHB0, CLK_SPIENC_REG),
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#if !defined(CONFIG_SPL_BUILD)
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AIC_CLK_PERIPH(CLK_PWMCS, CLK_PLL_INT1, CLK_PWMCS_REG),
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AIC_CLK_PERIPH(CLK_PSADC, CLK_OSC24M, CLK_PSADC_REG),
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AIC_CLK_PERIPH(CLK_I2S0, CLK_PLL_FRA1, CLK_I2S0_REG),
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AIC_CLK_PERIPH(CLK_I2S1, CLK_PLL_FRA1, CLK_I2S1_REG),
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AIC_CLK_PERIPH(CLK_CODEC, CLK_PLL_FRA1, CLK_CODEC_REG),
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#endif
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AIC_CLK_PERIPH(CLK_RGB, CLK_SCLK, CLK_RGB_REG),
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AIC_CLK_PERIPH(CLK_LVDS, CLK_SCLK, CLK_LVDS_REG),
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AIC_CLK_PERIPH(CLK_MIPIDSI, CLK_PLL_FRA2, CLK_MIPIDSI_REG),
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AIC_CLK_PERIPH(CLK_DE, CLK_PLL_INT1, CLK_DE_REG),
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AIC_CLK_PERIPH(CLK_GE, CLK_PLL_INT1, CLK_GE_REG),
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AIC_CLK_PERIPH(CLK_VE, CLK_PLL_INT1, CLK_VE_REG),
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AIC_CLK_PERIPH(CLK_PWM, CLK_PLL_INT1, CLK_PWM_REG),
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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AIC_CLK_PERIPH(CLK_WDOG, CLK_APB1, CLK_WDOG_REG),
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#else
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AIC_CLK_PERIPH(CLK_WDOG, CLK_OSC32K, CLK_WDOG_REG),
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#endif
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AIC_CLK_PERIPH(CLK_SID, CLK_OSC24M, CLK_SID_REG),
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AIC_CLK_PERIPH(CLK_GTC, CLK_APB1, CLK_GTC_REG),
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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AIC_CLK_PERIPH(CLK_GPIO, CLK_APB1, CLK_GPIO_REG),
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AIC_CLK_PERIPH(CLK_UART0, CLK_APB1, CLK_UART0_REG),
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AIC_CLK_PERIPH(CLK_UART1, CLK_APB1, CLK_UART1_REG),
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AIC_CLK_PERIPH(CLK_UART2, CLK_APB1, CLK_UART2_REG),
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AIC_CLK_PERIPH(CLK_UART3, CLK_APB1, CLK_UART3_REG),
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AIC_CLK_PERIPH(CLK_UART4, CLK_APB1, CLK_UART4_REG),
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AIC_CLK_PERIPH(CLK_UART5, CLK_APB1, CLK_UART5_REG),
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AIC_CLK_PERIPH(CLK_UART6, CLK_APB1, CLK_UART6_REG),
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AIC_CLK_PERIPH(CLK_UART7, CLK_APB1, CLK_UART7_REG),
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#else
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AIC_CLK_PERIPH(CLK_GPIO, CLK_APB0, CLK_GPIO_REG),
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AIC_CLK_PERIPH(CLK_UART0, CLK_PLL_INT1, CLK_UART0_REG),
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AIC_CLK_PERIPH(CLK_UART1, CLK_PLL_INT1, CLK_UART1_REG),
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AIC_CLK_PERIPH(CLK_UART2, CLK_PLL_INT1, CLK_UART2_REG),
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AIC_CLK_PERIPH(CLK_UART3, CLK_PLL_INT1, CLK_UART3_REG),
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AIC_CLK_PERIPH(CLK_UART4, CLK_PLL_INT1, CLK_UART4_REG),
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AIC_CLK_PERIPH(CLK_UART5, CLK_PLL_INT1, CLK_UART5_REG),
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AIC_CLK_PERIPH(CLK_UART6, CLK_PLL_INT1, CLK_UART6_REG),
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AIC_CLK_PERIPH(CLK_UART7, CLK_PLL_INT1, CLK_UART7_REG),
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#endif
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#if !defined(CONFIG_SPL_BUILD)
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AIC_CLK_PERIPH(CLK_I2C0, CLK_APB1, CLK_I2C0_REG),
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AIC_CLK_PERIPH(CLK_I2C1, CLK_APB1, CLK_I2C1_REG),
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AIC_CLK_PERIPH(CLK_I2C2, CLK_APB1, CLK_I2C2_REG),
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AIC_CLK_PERIPH(CLK_I2C3, CLK_APB1, CLK_I2C3_REG),
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AIC_CLK_PERIPH(CLK_CAN0, CLK_APB1, CLK_CAN0_REG),
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AIC_CLK_PERIPH(CLK_CAN1, CLK_APB1, CLK_CAN1_REG),
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AIC_CLK_PERIPH(CLK_ADCIM, CLK_OSC24M, CLK_ADCIM_REG),
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AIC_CLK_PERIPH(CLK_GPAI, CLK_APB1, CLK_GPAI_REG),
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AIC_CLK_PERIPH(CLK_RTP, CLK_APB1, CLK_RTP_REG),
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AIC_CLK_PERIPH(CLK_TSEN, CLK_APB1, CLK_TSEN_REG),
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AIC_CLK_PERIPH(CLK_CIR, CLK_APB1, CLK_CIR_REG),
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#endif
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};
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static struct aic_disp_clk clk_disps[] = {
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CLK_DISP(CLK_SCLK, CLK_PLL_FRA2, CLK_DISP_REG, 0, 3, 0, 0, 0, 0, 0, 0),
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CLK_DISP(CLK_PIX, CLK_SCLK, CLK_DISP_REG, 0, 0, 4, 5, 10, 2, 12, 2),
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};
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#ifdef CONFIG_CLK_ARTINCHIP_V0_1
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static u32 outclk_src_sels[] = {CLK_PLL_INT0, CLK_PLL_INT1, CLK_PLL_FRA0,
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CLK_PLL_FRA1, CLK_PLL_FRA2, CLK_OSC24M,
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CLK_OSC32K, CLK_RC1M};
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#else
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static u32 outclk_src_sels[] = {CLK_PLL_INT1, CLK_PLL_FRA1, CLK_PLL_FRA2};
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#endif
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static struct aic_clk_out clk_output[] = {
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/* id reg */
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AIC_CLK_OUT(CLK_OUT0, CLK_OUT0_REG),
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AIC_CLK_OUT(CLK_OUT1, CLK_OUT1_REG),
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AIC_CLK_OUT(CLK_OUT2, CLK_OUT2_REG),
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AIC_CLK_OUT(CLK_OUT3, CLK_OUT3_REG),
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};
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struct aic_clk_tree aic_clktree = {
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.fixed_rate_base = CLK_DUMMY,
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.fixed_rate_cnt = ARRAY_SIZE(clk_fixed_rates),
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.pll_base = CLK_PLL_INT0,
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.pll_cnt = ARRAY_SIZE(clk_plls),
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.system_base = CLK_AXI0,
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.system_cnt = ARRAY_SIZE(clk_syss),
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.periph_base = CLK_DMA,
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.periph_cnt = ARRAY_SIZE(clk_periphs),
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.disp_base = CLK_PIX,
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.disp_cnt = ARRAY_SIZE(clk_disps),
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.clkout_base = CLK_OUT0,
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.clkout_cnt = ARRAY_SIZE(clk_output),
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.fixed_rate = clk_fixed_rates,
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.plls = clk_plls,
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.system = clk_syss,
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.periph = clk_periphs,
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.disp = clk_disps,
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.clkout = clk_output,
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};
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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static void aic_pll_init_platdata(struct udevice *dev)
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{
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struct aic_clk_plat *plat = dev_get_plat(dev);
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struct dtd_artinchip_aic_cmu_v1_0 *dtplat = &plat->dtplat;
|
|
struct aic_clk_priv *priv = dev_get_priv(dev);
|
|
struct clk clk;
|
|
|
|
priv->base = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
|
|
clk.dev = dev;
|
|
|
|
clk.id = CLK_PLL_INT0;
|
|
clk_set_rate(&clk, dtplat->pll_int0);
|
|
|
|
clk.id = CLK_PLL_INT1;
|
|
clk_set_rate(&clk, dtplat->pll_int1);
|
|
|
|
clk.id = CLK_PLL_FRA0;
|
|
clk_set_rate(&clk, dtplat->pll_frac0);
|
|
|
|
clk.id = CLK_PLL_FRA1;
|
|
clk_set_rate(&clk, dtplat->pll_frac1);
|
|
|
|
clk.id = CLK_PLL_FRA2;
|
|
clk_set_rate(&clk, dtplat->pll_frac2);
|
|
}
|
|
#else
|
|
static void aic_pll_init_ofdata(struct udevice *dev)
|
|
{
|
|
struct aic_clk_priv *priv = dev_get_priv(dev);
|
|
int ret;
|
|
u32 value, freq;
|
|
struct clk clk;
|
|
|
|
priv->base = dev_read_addr_ptr(dev);
|
|
|
|
ret = dev_read_u32(dev, "pll-int0", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_PLL_INT0;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
|
|
ret = dev_read_u32(dev, "pll-int1", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_PLL_INT1;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
|
|
ret = dev_read_u32(dev, "pll-frac0", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_PLL_FRA0;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
|
|
ret = dev_read_u32(dev, "pll-frac1", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_PLL_FRA1;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
|
|
ret = dev_read_u32(dev, "pll-frac2", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_PLL_FRA2;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
}
|
|
|
|
static void aic_system_clock_init(struct udevice *dev)
|
|
{
|
|
int ret;
|
|
u32 value, freq;
|
|
struct clk clk, pclk;
|
|
|
|
/* Set axi0 bus clock */
|
|
ret = dev_read_u32(dev, "axi0", &value);
|
|
if (!ret) {
|
|
pclk.dev = dev;
|
|
clk.id = CLK_AXI0;
|
|
clk.dev = dev;
|
|
if (value == 24000000) {
|
|
pclk.id = CLK_OSC24M;
|
|
} else {
|
|
pclk.id = CLK_PLL_INT1;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
}
|
|
clk_set_parent(&clk, &pclk);
|
|
}
|
|
|
|
/* Set ahb0 bus clock */
|
|
ret = dev_read_u32(dev, "ahb0", &value);
|
|
if (!ret) {
|
|
pclk.dev = dev;
|
|
clk.id = CLK_AHB0;
|
|
clk.dev = dev;
|
|
if (value == 24000000) {
|
|
pclk.id = CLK_OSC24M;
|
|
} else {
|
|
pclk.id = CLK_PLL_INT1;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
}
|
|
clk_set_parent(&clk, &pclk);
|
|
}
|
|
|
|
/* Set apb0 bus clock */
|
|
ret = dev_read_u32(dev, "apb0", &value);
|
|
if (!ret) {
|
|
pclk.dev = dev;
|
|
clk.id = CLK_APB0;
|
|
clk.dev = dev;
|
|
if (value == 24000000) {
|
|
pclk.id = CLK_OSC24M;
|
|
} else {
|
|
pclk.id = CLK_PLL_INT1;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
}
|
|
clk_set_parent(&clk, &pclk);
|
|
}
|
|
|
|
/* Set apb1 bus clock */
|
|
ret = dev_read_u32(dev, "apb1", &value);
|
|
if (!ret) {
|
|
pclk.dev = dev;
|
|
clk.id = CLK_APB1;
|
|
clk.dev = dev;
|
|
if (value == 24000000) {
|
|
pclk.id = CLK_OSC24M;
|
|
} else {
|
|
pclk.id = CLK_PLL_INT1;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
}
|
|
clk_set_parent(&clk, &pclk);
|
|
}
|
|
|
|
/* Set CPU parent */
|
|
pclk.dev = dev;
|
|
pclk.id = CLK_PLL_INT0;
|
|
clk.id = CLK_CPU;
|
|
clk.dev = dev;
|
|
clk_set_parent(&clk, &pclk);
|
|
|
|
/* Set clk_out0 frequency */
|
|
ret = dev_read_u32(dev, "clk-out0", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_OUT0;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
|
|
/* Set clk_out1 frequency */
|
|
ret = dev_read_u32(dev, "clk-out1", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_OUT1;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
|
|
/* Set clk_out2 frequency */
|
|
ret = dev_read_u32(dev, "clk-out2", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_OUT2;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
|
|
/* Set clk_out3 frequency */
|
|
ret = dev_read_u32(dev, "clk-out3", &value);
|
|
if (!ret) {
|
|
clk.id = CLK_OUT3;
|
|
clk.dev = dev;
|
|
freq = clk_get_rate(&clk);
|
|
if (freq != value)
|
|
clk_set_rate(&clk, value);
|
|
clk_enable(&clk);
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static int aic_clk_probe(struct udevice *dev)
|
|
{
|
|
aic_clk_common_init(dev, &aic_clktree);
|
|
#if CONFIG_IS_ENABLED(OF_PLATDATA)
|
|
aic_pll_init_platdata(dev);
|
|
#else
|
|
aic_pll_init_ofdata(dev);
|
|
#endif
|
|
aic_system_clock_init(dev);
|
|
|
|
dev_info(dev, "%s done\n", __func__);
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id aic_clk_ids[] = {
|
|
{ .compatible = "artinchip,aic-cmu-v1.0", },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(artinchip_cmu) = {
|
|
.name = "artinchip_aic_cmu_v1_0",
|
|
.id = UCLASS_CLK,
|
|
.of_match = aic_clk_ids,
|
|
.probe = aic_clk_probe,
|
|
.priv_auto = sizeof(struct aic_clk_priv),
|
|
.plat_auto = sizeof(struct aic_clk_plat),
|
|
.ops = &artinchip_clk_ops,
|
|
};
|
|
|